CN101188225A - 半导体封装结构 - Google Patents
半导体封装结构 Download PDFInfo
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Abstract
本发明是有关一种半导体封装结构,该半导体封装结构包括有基板、中介基板(例如:电路积层板(Circuitry Laminate))、形成于中介基板上的金属层、第一芯片和第二芯片,其中该中介基板设置于基板上且覆盖基板上的开口的至少一部分,藉此在基板中界定出一容置空间以容置第一芯片于其中,而第二芯片是设置于中介基板或金属层上。金属层是电性连接至基板而接地,第一芯片是通过中介基板而电性连接至基板上。因此,可以提供电磁干扰屏蔽的效果,并能够符合微小化的要求,还可降低芯片受损的几率。
Description
技术领域
本发明涉及一种半导体封装结构,特别是涉及一种具有电磁干扰(EMI)屏蔽效果的半导体封装结构。
背景技术
随着微小化以及高运作速度需求的增加,具有复数个半导体芯片的半导体封装构造(亦即多芯片封装构造)在许多电子装置中越来越吸引人。多芯片封装构造可以藉由将处理器、记忆体(memory,即存储介质,存储器,内存等,以下均称为记忆体)以及逻辑芯片组合在单一的封装构造中,来使印刷电路板连接线路所导致的系统运作速度限制为最小化。此外,多芯片封装构造还可以减少芯片间连接线路的长度,而能够降低信号(即讯号)延迟以及存取的时间。
然而,特别是对于高频元件而言,芯片之间所产生的射频会造成严重的电磁干扰,因而影响芯片的性能。因此,必须加入特定的结构设计,以减少电磁干扰的现象发生。现有习知技术是直接加入一导电元件于两芯片之间,以阻隔两芯片之间的电磁干扰。然而,此种现有技术必须在两芯片的相关结构均完成之后再一起进行封胶,使得两芯片暴露在外的时间过长,因而增加了芯片受损的机率。此外,此种现有技术会增加其所制作的封装结构的尺寸,而不容易符合微小化的要求。
由此可见,上述现有的半导体封装结构在产品结构使用上,显然仍存在有不便与缺陷,而亟待加以进一步改进。为了解决上述存在的问题,相关厂商莫不费尽心思来谋求解决之道,但长久以来一直未见适用的设计被发展完成,而一般产品又没有适切的结构能够解决上述问题,此显然是相关业者急欲解决的问题。因此如何能创设一种新的半导体封装结构,实属当前重要研发课题之一,亦成为当前业界极需改进的目标。
有鉴于上述现有的半导体封装结构存在的缺陷,本发明人基于从事此类产品设计制造多年丰富的实务经验及专业知识,并配合学理的运用,积极加以研究创新,以期创设一种新的半导体封装结构,能够改进一般现有的半导体封装结构,使其更具有实用性。经过不断的研究、设计,并经反复试作样品及改进后,终于创设出确具实用价值的本发明。
发明内容
本发明的目的在于,克服现有的半导体封装结构存在的缺陷,而提供一种新的半导体封装结构,所要解决的技术问题是使其可以克服电磁干扰的问题,并能够符合微小化的要求,非常适于实用。
本发明的另一目的在于,提供一种新的半导体封装结构,所要解决的技术问题是使其能够降低芯片受损的机率,从而更加适于实用。
本发明的目的及解决其技术问题是采用以下技术方案来实现的。依据本发明提出的一种半导体封装结构,其至少包括:一基板,具有一第一表面、相对该第一表面的一第二表面及贯穿该第一表面及该第二表面的一开口,该第一表面上设置有复数个第一电性接点及复数个第二电性接点,其中该些第二电性接点是相对于该些第一电性接点远离该开口;一中介基板,具有一第三表面及相对该第三表面的一第四表面,该中介基板的该第三表面上设有复数个第三电性接点及复数个第四电性接点,其中该中介基板是叠置于该基板的该第一表面上且覆于该开口的至少一部分及该些第三电性接点,并界定出一容置空间,该些第三电性接点与该些第一电性接点是电性连接;一金属层,形成于该中介基板的该第四表面上;一第一芯片,设置于该容置空间内且电性连接至该些第四接点;以及一第二芯片,设置于金属层上,且电性连接至该基板的该些第二电性接点。
本发明的目的及解决其技术问题还可采用以下技术措施进一步实现。
前述的半导体封装结构,其更至少包括复数个电性连接元件,用以电性连接该第一芯片至该中介基板的该些第四电性接点,其中该些电性连接元件是选自由焊线、金属突块以及异方性导电胶膜(Anisotropic ConductiveFilm;ACF)所组成的一族群。
前述的半导体封装结构,其更至少包括一封胶材料,用以填充该容置空间并封住该第一芯片。
前述的半导体封装结构,其中所述的基板具有复数个第五电性接点,该金属层是电性连接于该些第五电性接点。
前述的半导体封装结构,其更至少包括一封胶材料,用以封住该第一表面的一部分、该中介基板、该第二芯片。
前述的半导体封装结构,其更至少包括一点胶材料,用以包覆该第一芯片与该中介基板的电性连接处。
本发明的目的及解决其技术问题还采用以下的技术方案来实现。依据本发明提出的一种半导体封装结构,其至少包括:一基板,具有一第一表面、相对该第一表面的一第二表面及贯穿该第一表面及该第二表面的一开口,该第一表面上设置有复数个第一电性接点及复数个第二电性接点,其中该些第二电性接点是相对于该些第一电性接点远离该开口;一中介基板,具有一第三表面及相对该第三表面的一第四表面,该中介基板的该第三表面上设有复数个第三电性接点及复数个第四电性接点,其中该中介基板是叠置于该基板的该第一表面上且覆于该开口的至少一部分及该些第三电性接点,并界定出一容置空间,该些第三电性接点与该些第一电性接点是电性连接;一金属层,形成于该中介基板的该第四表面上;一第一芯片,设置于该容置空间内且电性连接至该些第四接点;以及一第二芯片,设置于该中介基板的该第四表面上,且电性连接至该基板的该些第二电性接点。
本发明的目的及解决其技术问题还可采用以下技术措施进一步实现。
前述的半导体封装结构,其更至少包括复数个电性连接元件,用以电性连接该第一芯片至该中介基板的该些第四电性接点,其中该些电性连接元件是选自由焊线、金属突块以及异方性导电胶膜所组成的一族群。
前述的半导体封装结构,其更至少包括一封胶材料,用以填充该容置空间并封住该第一芯片。
前述的半导体封装结构,其中所述的基板具有复数个第五电性接点,该金属层是电性连接于该些第五电性接点。
前述的半导体封装结构,其更至少包括一封胶材料,用以封住该第一表面的一部分、该中介基板、该第二芯片。
前述的半导体封装结构,其更至少包括一点胶材料,用以包覆该第一芯片与该中介基板的电性连接处。
本发明与现有技术相比具有明显的优点和有益效果。由以上技术方案可知,本发明的主要技术内容如下:
为了达到上述目的,根据本发明的实施例,该半导体封装结构,至少包括:基板、中介基板、金属层、第一芯片和第二芯片,其中第一芯片可为例如:打线(Wire Bond)型式的芯片或倒装(Flip Chip)型式的芯片,第二芯片可为例如:打线型式的芯片。基板具有第一表面、相对第一表面的第二表面和贯穿第一表面和第二表面的开口,且该第一表面上具有复数个第一电性接点以及复数个第二电性接点,其中第二电性接点是相对于第一电性接点远离该开口。中介基板是由例如:电路积层板(Circuitry Laminate)所制成。中介基板具有第三表面及相对第三表面的第四表面,中介基板的第三表面上设有复数个第三电性接点及复数个第四电性接点,其中中介基板是叠置于基板的第一表面上且覆于其开口的至少一部分及第三电性接点,并界定出一容置空间,而第三电性接点与该些第一电性接点是电性连接。金属层是形成于中介基板的第四表面上。第一芯片是设置于容置空间内,且电性连接至第四接点。第二芯片是设置于金属层或中介基板的第四表面上,且电性连接至该些第二电性接点。该半导体封装结构更至少包括封胶材料,该封胶材料是用以填充前述的容置空间,并密封住第一芯片;和/或密封住基板的第一表面的一部分、中介基板、第二芯片以及相关的焊线。此外,当第一芯片为倒 型式的芯片时,可在施加封胶材料前,先使用点胶材料来包覆第一芯片与中介基板的电性连接处。
借由上述技术方案,本发明半导体封装结构至少具有下列优点及有益效果:
1、本发明新的半导体封装结构,可以有效的克服电磁干扰的问题,并能够符合微小化的要求,非常适于实用。
2、本发明的半导体封装结构,可以降低芯片受损的机率。
综上所述,本发明是有关一种半导体封装结构,该半导体封装结构包括有基板、中介基板(例如:电路积层板(Circuitry Laminate))、形成于中介基板上的金属层、第一芯片和第二芯片,其中该中介基板设置于基板上且覆盖基板上的开口的至少一部分,藉此在基板中界定出一容置空间以容置第一芯片于其中,而第二芯片是设置于中介基板或金属层上。金属层是电性连接至基板而接地,第一芯片是通过中介基板而电性连接至基板上。因此,可以提供电磁干扰屏蔽的效果,并能够符合微小化的要求,还可降低芯片受损的机率。本发明具有上述诸多优点及实用价值,其不论在产品结构或功能上皆有较大的改进,在技术上有显著的进步,并产生了好用及实用的效果,且较现有的半导体封装结构具有增进的突出功效,从而更加适于实用,诚为一新颖、进步、实用的新设计。
上述说明仅是本发明技术方案的概述,为了能够更清楚了解本发明的技术手段,而可依照说明书的内容予以实施,并且为了让本发明的上述和其他目的、特征和优点能够更明显易懂,以下特举较佳实施例,并配合附图,详细说明如下。
附图说明
图1A是根据本发明一实施例的半导体封装结构的示意图。
图1B是根据本发明又一实施例的半导体封装结构的示意图。
图2是根据本发明再一实施例的半导体封装结构的示意图。
具体实施方式
为更进一步阐述本发明为达成预定发明目的所采取的技术手段及功效,以下结合附图及较佳实施例,对依据本发明提出的半导体封装结构其具体实施方式、结构、步骤、特征及其功效,详细说明如后。
有关本发明的前述及其他技术内容、特点及功效,在以下配合参考图式较佳实施例的详细说明中将可清楚的呈现。通过具体实施方式的说明,当可对本发明为达成预定目的所采取的技术手段及功效得一更加深入且具体的了解,然而所附图式仅是提供参考与说明之用,并非用来对本发明加以限制。
虽然本发明可以表现为不同形式的实施例,但附图所示及在下文中所说明的技术内容是本发明的较佳实施例,并请了解本文所揭示的仅是为本发明的范例,并非用以将本发明限制于图示及/或所描述的特定实施例中。
本发明半导体封装结构,可为由设置在中介基板上方的打线型式的芯片与设置在中介基板下方的倒装型式的芯片所组成;或由设置在中介基板上方的打线型式的芯片与设置在中介基板下方的打线型式的芯片所组成。
请参图1A所示,是根据本发明一实施例半导体封装结构的示意图,本发明的半导体封装结构,主要包括基板100,其中该基板100具有表面102和相对于表面102的表面103,并且形成设有贯穿表面102和103的开口108。表面102上设置有复数个电性接点104、106和107,其中电性接点106、电性接点107是相对于电性接点104远离该开口。中介基板120设置于基板100的表面102上,并且覆盖住开口108的全部或一部分,因而在基板100中界定出一容置空间(图中未标示)。
上述的中介基板120,具有表面122和相对于表面122的表面123。
该中介基板120的表面122,其周边设置有复数个电性接点124,该电性接点124是面对基板100的表面102,其中该电性接点124是分别电性连接于基板100的电性接点104。中介基板120的表面122上更设置有复数个电性接点126,该电性接点126是暴露于前述的容置空间中,且电性接点126是分别电性连接于电性接点114。
该中介基板120的表面123,其上设置有金属层121,中介基板120的表面123是位于中介基板120上的相对表面122的表面。然而,该金属层121亦可以设置在中介基板120上除表面122的任意表面,故本发明并不限制于此。该金属层121可由金属化中介基板120的一表面而形成。
该中介基板120,可由例如:电路积层板(Circuitry Laminate)所制成。
以焊线144将上述金属层121电性连接于基板100的电性接点107而接地,以产生电磁干扰屏蔽的效果。第一芯片110设于中介基板120的表面122上,并容置于前述的容置空间内,其中,该第一芯片110可以通过例如导电粘着材料层(图中未绘示)而设置在中介基板120的表面122上。第一芯片110的面向第二芯片130的表面112,其上形成设有复数个电性接点114,该电性接点114是分别电性连接于中介基板120的电性接点126,而形成复数个电性连接。其中,该些电性连接可以为例如:复数个金属突块或复数个异方性导电胶膜(Anisotropic Conductive Film;ACF)。以填充封胶材料150于前述的容置空间,来密封住第一芯片110,因而完成对第一芯片110的保护,减少第一芯片110暴露于外的时间。第一芯片110为倒装型式的芯片,故可在进行封模之前,以点胶材料来包覆第一芯片110与中介基板120的电性连接处。可通过导电粘着材料层(图中未绘示),来设置第二芯片130于中介基板120的金属层121上;其中,第二芯片130的表面132上形成设有复数个电性接点134。该电性接点134是藉由焊线142而分别电性连接于基板100上的电性接点106。以使用封胶材料152来密封住表面102的一部分、中介基板120、第二芯片130及焊线142和焊线144,因而完成对第二芯片130的保护。
由于在设置第二芯片130时,第一芯片110已完全密封住,故可避免受到制程中的伤害。另外,第一芯片110是容置于前述中介基板120覆盖住基板100的开口108所形成的容置空间中,故可以减少半导体封装结构的尺寸,因而能够符合微小化的要求。由于第一芯片110是通过中介基板120而电性连接至基板100,并未直接电性连接至基板100,故更可有效地阻隔第一芯片110和第二芯片130之间的电磁干扰。
请参阅图1B所示,是根据本发明又一实施例的半导体封装结构的示意图。本发明该又一实施例与图1A所示实施例不同之处在于,金属层121是设置于中介基板120的表面123的周边,而未形成于中介基板120的表面123的中间区域。本实施例是设置第二芯片130于中介基板120的表面123的该中间区域上。
请参阅图2所示,是根据本发明再一实施例的半导体封装结构的示意图,其中,第一芯片210和第二芯片130均是打线型式的芯片。除了第一芯片210是打线型式的芯片外,本实施例所示的半导体封装结构是类似于图1A所示的实施例。第一芯片210是设置于中介基板120的表面122上,并容置于前述的容置空间中,其中,第一芯片210可通过例如导电粘着材料层(图中未绘示)而设置在中介基板120的表面122上。第一芯片210的表面212是背对第二芯片130,并具有复数个电性接点214,并且电性接点214是通过焊线240分别电性连接于中介基板120的电性接点126。
因此,上述的实施例的半导体封装结构,可以提供电磁干扰屏蔽的效果,并能够符合微小化的要求,还可降低芯片受损的机率。
以上所述,仅是本发明的较佳实施例而已,并非对本发明作任何形式上的限制,虽然本发明已以较佳实施例揭露如上,然而并非用以限定本发明,任何熟悉本专业的技术人员,在不脱离本发明技术方案范围内,当可利用上述揭示的方法及技术内容作出些许的更动或修饰为等同变化的等效实施例,但凡是未脱离本发明技术方案的内容,依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰,均仍属于本发明技术方案的范围内。
Claims (12)
1.一种半导体封装结构,其特征在于其至少包括:
一基板,具有一第一表面、相对该第一表面的一第二表面及贯穿该第一表面及该第二表面的一开口,该第一表面上设置有复数个第一电性接点及复数个第二电性接点,其中该些第二电性接点是相对于该些第一电性接点远离该开口;
一中介基板,具有一第三表面及相对该第三表面的一第四表面,该中介基板的该第三表面上设有复数个第三电性接点及复数个第四电性接点,其中该中介基板是叠置于该基板的该第一表面上且覆于该开口的至少一部分及该些第三电性接点,并界定出一容置空间,该些第三电性接点与该些第一电性接点是电性连接;
一金属层,形成于该中介基板的该第四表面上;
一第一芯片,设置于该容置空间内且电性连接至该些第四接点;以及
一第二芯片,设置于金属层上,且电性连接至该基板的该些第二电性接点。
2.根据权利要求1所述的半导体封装结构,其特征在于其更至少包括复数个电性连接元件,用以电性连接该第一芯片至该中介基板的该些第四电性接点,其中该些电性连接元件是选自由焊线、金属突块以及异方性导电胶膜所组成的一族群。
3.根据权利要求1所述的半导体封装结构,其特征在于其更至少包括一封胶材料,用以填充该容置空间并封住该第一芯片。
4.根据权利要求1所述的半导体封装结构,其特征在于其中所述的基板具有复数个第五电性接点,该金属层是电性连接于该些第五电性接点。
5.根据权利要求1所述的半导体封装结构,其特征在于其更至少包括一封胶材料,用以封住该第一表面的一部分、该中介基板、该第二芯片。
6.根据权利要求1所述的半导体封装结构,其特征在于其更至少包括一点胶材料,用以包覆该第一芯片与该中介基板的电性连接处。
7.一种半导体封装结构,其特征在于其至少包括:
一基板,具有一第一表面、相对该第一表面的一第二表面及贯穿该第一表面及该第二表面的一开口,该第一表面上设置有复数个第一电性接点及复数个第二电性接点,其中该些第二电性接点是相对于该些第一电性接点远离该开口;
一中介基板,具有一第三表面及相对该第三表面的一第四表面,该中介基板的该第三表面上设有复数个第三电性接点及复数个第四电性接点,其中该中介基板是叠置于该基板的该第一表面上且覆于该开口的至少一部分及该些第三电性接点,并界定出一容置空间,该些第三电性接点与该些第一电性接点是电性连接;
一金属层,形成于该中介基板的该第四表面上;
一第一芯片,设置于该容置空间内且电性连接至该些第四接点;以及
一第二芯片,设置于该中介基板的该第四表面上,且电性连接至该基板的该些第二电性接点。
8.根据权利要求7所述的半导体封装结构,其特征在于其更至少包括复数个电性连接元件,用以电性连接该第一芯片至该中介基板的该些第四电性接点,其中该些电性连接元件是选自由焊线、金属突块以及异方性导电胶膜所组成的一族群。
9.根据权利要求7所述的半导体封装结构,其特征在于其更至少包括一封胶材料,用以填充该容置空间并封住该第一芯片。
10.根据权利要求7所述的半导体封装结构,其特征在于其中所述的基板具有复数个第五电性接点,该金属层是电性连接于该些第五电性接点。
11.根据权利要求7所述的半导体封装结构,其特征在于其更至少包括一封胶材料,用以封住该第一表面的一部分、该中介基板、该第二芯片。
12.根据权利要求7所述的半导体封装结构,其特征在于其更至少包括一点胶材料,用以包覆该第一芯片与该中介基板的电性连接处。
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US7566962B2 (en) | 2009-07-28 |
US20080150110A1 (en) | 2008-06-26 |
CN100511671C (zh) | 2009-07-08 |
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