CN104218006A - 半导体封装 - Google Patents

半导体封装 Download PDF

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Publication number
CN104218006A
CN104218006A CN201410230720.7A CN201410230720A CN104218006A CN 104218006 A CN104218006 A CN 104218006A CN 201410230720 A CN201410230720 A CN 201410230720A CN 104218006 A CN104218006 A CN 104218006A
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semiconductor chip
casting portion
semiconductor
substrate
chip
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郑泰成
张珉硕
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Samsung Electro Mechanics Co Ltd
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Samsung Electro Mechanics Co Ltd
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
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Abstract

本发明的半导体封装包括：基板；多芯片封装，该多芯片封装安装在所述基板的上表面，并包括至少一个半导体芯片；半导体芯片，该半导体芯片以面朝上(face-up)的方式安装在所述基板的背面；第一浇注部，该第一浇注部密封所述多芯片封装；以及第二浇注部，该第二浇注部密封所述第三半导体芯片。

Description

半导体封装
技术领域
本发明涉及半导体封装。
背景技术
随着近年来的安装有半导体封装的产品轻薄小型化和要求更多功能，半导体封装技术处于使用如在半导体封装内安装多个半导体芯片的SIP(System in Package：系统封装)和POP(Package on Package：堆叠式封装)等方式的趋势。虽然这种半导体封装为了增加容量而增加层叠的半导体芯片裸片的数量，但是，在对半导体芯片裸片单一地进行层叠的情况下，层叠数越增加，封装整体厚度也越增加，因此，存在不能达到产品的轻薄小型化的倾向。为解决该问题，即能增加半导体封装的容量还能缩小封装整体的厚度的技术已成为需要。
作为对此的解决方案，现有一种在在下部层叠的封装的情况下，在布线基板(PCB)内部内置有半导体芯片裸片的嵌入式(embedded)PCB，该嵌入式PCB通过将层叠的半导体芯片裸片内置于布线基板的内部，使与其对应的层叠厚度减小，从而能够减小整个封装的厚度。此外，通过将半导体芯片内置于布线基板的内部，能够使相应半导体的布线由布线基板的内部布线所代替，从而使整体布线单一化，提高产品性能。
此外，对采用于智能电话或平板电脑等的移动产品中的器件的封装持续要求小型化、高性能化，通过使所述封装小型化而开发一种在相同空间内附加更多的功能或在剩余空间尽可能地增加电池容量的研究。特别是，在不是主要部件且具有附加功能的部件中对小型化的要求更加强烈。
而且，如现有技术文献所记载的专利文献所公开，根据以往使用多芯片SIP(single chip package：单片封装)方式的半导体封装技术，在安装半导体芯片时，需要较宽的封装面积，这种封装方式相对来说整体封装尺寸不适合采用在处于轻薄小型化趋势的移动产品中，并存在由所述封装的尺寸大小造成的封装翘曲(warpage)的问题。
现有技术文献
专利文献
专利文献1：2010-0045193KR
发明内容
本发明是为了解决上述现有问题而提出，本发明的目的在于提供一种半导体封装，该半导体封装通过在基板的上表面和背面安装半导体芯片的方式来减小整体封装的尺寸，从而能够使采用半导体封装的移动产品轻薄小型化。
根据本发明的实施例的半导体封装包括：基板；多芯片封装，该多芯片封装安装在所述基板的上表面，并包括至少一个半导体芯片；半导体芯片，该半导体芯片以面朝上(face-up)的方式安装在所述基板的背面；第一浇注部，该第一浇注部密封所述多芯片封装；以及第二浇注部，该第二浇注部密封所述半导体芯片。
此外，所述多芯片封装包括倒装焊接(flip-chip bonding)在所述基板的上表面的第一半导体芯片和以面朝上的方式层叠在所述第一半导体芯片上的第二半导体芯片。
此外，所述半导体芯片倒装焊接在所述基板的背面。
此外，所述第一浇注部的厚度h1与所述第二浇注部的厚度h2的比h1：h2为1：0.8至1。
此外，所述半导体封装还包括通孔，该通孔形成在所述第二浇注部的两侧面，并与所述基板和外部端子进行电连接。
此外，所述通孔的直径为0.2mm以上、1.0mm以下。
根据本发明的实施例的半导体封装的制造方法包括：半导体芯片安装步骤，在基板的上表面安装包括至少一个半导体芯片的多芯片封装，在所述基板的下表面安装半导体芯片；浇注部形成步骤，形成密封所述多芯片封装的第一浇注部和密封所述半导体芯片的第二浇注部；以及通孔形成步骤，在所述第二浇注部的两侧面上形成通孔以与所述基板进行电连接。
此外，在所述半导体芯片安装步骤中，所述多芯片封装包括倒装焊接在所述基板的第一半导体芯片和以面朝上的方式层叠在所述第一半导体芯片上的第二半导体芯片。
此外，在所述半导体芯片安装步骤中，所述半导体芯片倒装焊接在所述基板的背面。
此外，在所述浇注部形成步骤中，所述第一浇注部的厚度h1与所述第二浇注部的厚度h2的比h1：h2为1：0.8至1。
此外，在所述通孔形成步骤中，所述通孔的直径为0.2mm以上、1.0mm以下。
根据本发明，不是通过将半导体芯片等安装在基板的一面的SIP(singleline in package)方式，而是通过将半导体芯片安装在所述基板的上表面和背面的方式减小整体封装的尺寸，从而能够使采用半导体封装的移动产品轻薄小型化。
此外，在形成有第一浇注部和第二浇注部以密封安装于基板的上表面和背面的半导体芯片等的结构中，能够通过所述第一浇注部和第二浇注部的厚度和材料的可选择性来改善半导体封装的翘曲。
附图说明
图1是示出根据本发明的实施例的半导体封装的剖视图。
图2是示出根据本发明的另一个实施例的半导体封装的剖视图。
图3a至图3c是示出根据本发明的实施例的半导体封装的制造方法的图。
附图标记说明
10：     半导体封装          100：    基板
101：    第一布线端子        102：    第二布线端子
103：    过孔                110：    第一半导体芯片
111：    第一焊料球          112：    粘接层
120：    第二半导体芯片      121：    芯片焊垫
122：    接合线              130：    半导体芯片
131：    焊料球              140：    无源元件
150：    第一浇注部          160：    第二浇注部
170：    通孔                180：    外部端子
190：    第二焊料球          200：    多芯片封装
a：      通孔的直径
具体实施方式
通过与附图相关联的以下的详细说明和优选实施例，本发明的目的、特定的优点以及新颖的特征将变得更加清楚。应注意，在本说明书中，对各附图的构成要素标注附图标记时，限于相同的构成要素，即使显示在不同的附图中，也尽可能标注为相同的附图标记。此外，“一面”、“另一面”、“第一”、“第二”等用语是为了将一个构成要素与其它构成要素进行区分而使用的，构成要素并不被所述用语所限制。以下，在对本发明进行说明时，将省略有可能不必要地混淆本发明的要旨的相关公知技术的详细说明。
以下，参照附图对本发明的优选实施例进行详细说明。
图1是示出根据本发明的实施例的半导体封装的剖视图，图2是示出根据本发明的另一个实施例的半导体封装的剖视图。如图1和2所示，本发明的第一实施例的半导体封装10包括基板100、多芯片封装200、半导体芯片130、第一浇注部150以及第二浇注部160。
基板100可以是通常作为层间绝缘材料使用的复合高分子树脂(半固化片、ABF(Ajinomoto Buildup Film)、FR-4或BT(Bismaleimide Triazine)等环氧类树脂)，但是并不限定于此，作为基板100还可以利用覆铜箔层压板(CCL)。
另外，在基板100的上表面形成有通过倒装焊接方式以及接合线122与多芯片封装200电连接的第一布线端子101，并在基板100的下表面形成有通过倒装焊接方式与半导体芯片130电连接的第二布线端子102。在此，第一布线端子101和第二布线端子102通过过孔103相互进行电连接。
此外，在基板100的两面安装有无源元件140，这种无源元件140可以是与多芯片封装200和半导体芯片100相关的电阻R、电感L、电容C。
多芯片封装200安装在基板100的上表面，并包括至少一个半导体芯片。在此，多芯片封装200包括倒装焊接在基板100的上表面的第一半导体芯片110和以面朝上的方式层叠在第一半导体芯片110上的第二半导体芯片120。
即，第一半导体芯片110通过第一焊料球111与基板100进行电连接，第二半导体芯片120以面朝上的方式层叠在第一半导体芯片110上，通过芯片焊垫121和接合线122与第一布线端子101进行电连接。
此外，在第二半导体芯片120的下表面形成有以液状或膜形态构成的粘接层，并与第一半导体芯片110的上表面粘接，第一半导体芯片110和第二半导体芯片120作为与AP(application processor：应用处理器)相关的元件，可以包括移动用CPU(central processing unit：中央处理单元)或GPU(graphicsprocessing unit：图像处理单元)。
半导体芯片130以面朝上的方式安装在基板100的背面，焊料球131通过倒装焊接的方式与第二布线端子102进行电连接。在此，半导体芯片130作为与存储器设备相关的元件，可以包括DDR或DDR2RAM，优选是作为下一代移动用DRAM，功耗低且能对Mobile CPU或GPU供给流畅的DATA的WIDE I/O RAM。
为了保护分别安装在基板100的两面的多芯片封装200和半导体芯片130等不受外部冲击，第一浇注部150和第二浇注部160形成为能够密封多芯片封装200和半导体芯片130等。
在此，第一浇注部150和第二浇注部160可以通过将安装有半导体芯片等的基板100投入到成型模具(未图示)中后，通过模具浇口注入环氧(epoxy)类的浇注树脂来实现的传递模塑(transfer molding)工序来形成，通过所述模塑工序能够提高半导体芯片等与基板之间的焊接可靠性。此外，关于形成第一浇注部150和第二浇注部160的方法和材料，可以由本领域技术人员应用公知的技术进行变更。
此外，优选将第一浇注部150和第二浇注部160形成为使第一浇注部150的厚度h1与第二浇注部160的厚度h2的比h1：h2为1：0.8至1。即，通过使第一浇注部150和第二浇注部160的厚度之差在第一浇注部150的厚度h1的20％以内，从而能够改善半导体封装10的尺寸和翘曲现象。
通孔170形成在基板100的背面的第二浇注部160的两侧面以与第二布线端子102电连接，通孔170内部可以填充有包括导电性膏、金属镀敷(Metalplating)或金属球连接(metal ball attach)的导电性金属物质。
即，通孔170形成为与形成于基板100背面的第二布线端子102和形成于第二浇注部160的两侧面的外部端子180进行电连接，从而使第二布线端子102能够通过通孔170与外部进行电接触。
此外，如图1所示，通孔170可以通过第二焊料球190与外部连接(BGA类型)，但是，也可以如图2所示，通过外部端子180与外部连接(LGA类型)。
另外，通孔170的直径a形成在0.2mm以上、1.0mm以下的范围内，从而能够减小半导体封装10的侧面尺寸，由此能够实现整体封装的轻薄小型化。
如上所述，半导体封装不是通过将半导体芯片等安装在基板的一面的SIP方式，而是通过将半导体芯片安装在所述基板的上表面和背面的方式，能够使整体封装的尺寸减小，从而能够使采用半导体封装的移动产品轻薄小型化。
此外，在形成有第一浇注部和第二浇注部以密封安装于基板的上表面和背面的半导体芯片等的结构中，能够通过所述第一浇注部和第二浇注部的厚度以及材料的可选择性来改善半导体封装的翘曲。
图3a至图3c是示出根据本发明的实施例的半导体封装的制造方法的图，以下，对半导体封装的制造方法进行说明。
如图3a所示，在半导体芯片安装步骤中，在基板100的上表面和背面分别安装包括至少一个半导体芯片的多芯片封装200和半导体芯片130，多芯片封装200可以包括倒装焊接在基板100上的第一半导体芯片110和以面朝上的方式层叠在所述第一半导体芯片110上的第二半导体芯片120，半导体芯片130通过焊料球131倒装焊接在基板100的背面。
如图3b所示，在浇注部形成步骤中，形成第一浇注部150和第二浇注部160以密封分别安装在基板100的两面的多芯片封装200和半导体芯片130。在此，第一浇注部150和第二浇注部160可以通过将安装有半导体芯片等的基板100投入到成型模具(未图示)中后，通过模子浇口注入环氧类的浇注树脂来实现的传递模塑工序形成，关于形成第一浇注部150和第二浇注部160的方法和材料可以由本领域技术人员应用公知的技术进行变更。
此外，优选可以将第一浇注部150和第二浇注部160，形成为使第一浇注部150的厚度h1与第二浇注部160的厚度h2的比h1：h2为1：0.8至1。
如图3c所示，在通孔形成步骤中，在形成于基板100的背面的第一浇注部150的两侧面上形成通孔170，以与第二布线电极102电连接，通孔170内部可以填充有包括导电性膏、金属镀覆或金属球连接的导电性金属物质。
在此，通孔170的直径a形成在0.2mm以上、1.0mm以下的范围内，从而能减小半导体封装10的侧面尺寸，由此能够实现整体封装的整体上的轻薄小型化。
以上，通过具体实施例对本发明进行了详细说明，但是，这只是为了对本发明进行具体说明，根据本发明的半导体封装并不限定于此，显然，在本发明的技术思想范围内，可以由本领域技术人员进行变形或改良从而更加明确。
本发明的单一的变形或变更都属于本发明的领域，本发明的具体保护范围应由随附的权利要求书来确定。

Claims (11)

1.一种半导体封装，包括：
基板；
多芯片封装，该多芯片封装安装在所述基板的上表面，并包括至少一个半导体芯片；
半导体芯片，该半导体芯片以面朝上的方式安装在所述基板的背面；
第一浇注部，该第一浇注部密封所述多芯片封装；以及
第二浇注部，该第二浇注部密封所述半导体芯片。
2.根据权利要求1所述的半导体封装，其特征在于，
所述多芯片封装包括：
第一半导体芯片，该第一半导体芯片倒装焊接在所述基板的上表面；以及
第二半导体芯片，该第二半导体芯片以面朝上的方式层叠在所述第一半导体芯片上。
3.根据权利要求1所述的半导体封装，其特征在于，
所述半导体芯片倒装焊接在所述基板的背面。
4.根据权利要求1所述的半导体封装，其特征在于，
所述第一浇注部的厚度(h1)与所述第二浇注部的厚度(h2)的比(h1：h2)为1：0.8至1。
5.根据权利要求1所述的半导体封装，其特征在于，
所述半导体封装还包括通孔，该通孔形成在所述第二浇注部的两侧面，并与所述基板和外部端子进行电连接。
6.根据权利要求5所述的半导体封装，其特征在于，
所述通孔的直径为0.2mm以上、1.0mm以下。
7.一种半导体封装的制造方法，包括：
半导体芯片安装步骤，在基板的上表面安装包括至少一个半导体芯片的多芯片封装，在所述基板的下表面安装半导体芯片；
浇注部形成步骤，形成密封所述多芯片封装的第一浇注部和密封所述半导体芯片的第二浇注部；以及
通孔形成步骤，在所述第二浇注部的两侧面上形成通孔以与所述基板进行电连接。
8.根据权利要求7所述的半导体封装的制造方法，其特征在于，
在所述半导体芯片安装步骤中，所述多芯片封装包括：
第一半导体芯片，该第一半导体芯片倒装焊接在所述基板上；以及
第二半导体芯片，该第二半导体芯片以面朝上的方式层叠在所述第一半导体芯片上。
9.根据权利要求7所述的半导体封装的制造方法，其特征在于，
在所述半导体芯片安装步骤中，所述半导体芯片倒装焊接在所述基板的背面。
10.根据权利要求7所述的半导体封装的制造方法，其特征在于，
在所述浇注部形成步骤中，所述第一浇注部的厚度(h1)与所述第二浇注部的厚度(h2)的比(h1：h2)为1：0.8至1。
11.根据权利要求7所述的半导体封装的制造方法，其特征在于，
在所述通孔形成步骤中，所述通孔的直径为0.2mm以上、1.0mm以下。
CN201410230720.7A 2013-05-28 2014-05-28 半导体封装 Pending CN104218006A (zh)

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