CN110943050B - 一种封装结构及堆叠式封装结构 - Google Patents

一种封装结构及堆叠式封装结构 Download PDF

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CN110943050B
CN110943050B CN201811118363.XA CN201811118363A CN110943050B CN 110943050 B CN110943050 B CN 110943050B CN 201811118363 A CN201811118363 A CN 201811118363A CN 110943050 B CN110943050 B CN 110943050B
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package
circuit carrier
component
stacked
electrical connection
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CN110943050A (zh
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李衡军
陈丽霞
王林国
张滨
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ZTE Corp
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Priority to PCT/CN2019/106103 priority patent/WO2020057483A1/zh
Priority to EP19861380.4A priority patent/EP3855489A4/en
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Abstract

本文公开了一种封装结构及堆叠式封装结构，封装结构包括：其中设置有电路载板的封装体和电性连接部，电性连接部设置在封装体的外部，还包括：导电结构；导电结构设置在封装体的至少一个侧面的外表面，用于电性连接电路载板和电性连接部。由于封装体的至少一个侧面设置了用于电性连接电路载板和电性连接部的导电结构，从而使得电路载板的面积不再被占用，避免了导致供元器件贴装的衬底电路载板的面积的缩减。

Description

一种封装结构及堆叠式封装结构
技术领域
本发明实施例涉及封装技术领域，尤指一种封装结构及堆叠式封装结构。
背景技术
封装结构是指将多个元器件设置在封装体的衬底电路载板上形成的一种结构，然而由于所有元器件都是贴装在衬底电路载板上，因此占用的衬底电路载板面积较大，从而当封装结构安装在外部电路基板上时会占用较大的基板面积。
相关技术中，为了缩小封装结构所占用的外部电路基板的面积，通常在封装体表面设置焊盘，然后在封装体内部设置电性连接焊盘与衬底电路载板的导电结构，从而使得一部分元器件能够贴装于焊盘上。
然而，该方案由于在封装体内部设置了电性连接焊盘与衬底电路载板的导电结构，因此使得衬底电路载板的面积被大量占用，从而导致供元器件贴装的衬底电路载板的面积的缩减。
发明内容
为了解决上述技术问题，本发明实施例提供了一种封装结构及堆叠式封装结构，能够避免供元器件贴装的衬底电路载板的面积的缩减。
为了达到本发明实施例的目的，本发明实施例提供了一种封装结构，包括：其中设置有电路载板的封装体和电性连接部，所述电性连接部设置在所述封装体的外部，还包括：导电结构；
所述导电结构设置在所述封装体的至少一个侧面的外表面，用于电性连接所述电路载板和所述电性连接部。
本发明实施例还提供了一种堆叠式封装结构，包括：第一元器件结构以及如权利要求2所述的封装结构；
其中，所述第一元器件结构设置在所述电性连接部上。
本发明实施例还提供了一种堆叠式封装结构，包括：第三元器件结构以及如权利要求3所述的封装结构；
其中，所述第三元器件结构设置在所述电路载板的上表面上。
本发明实施例还提供了一种堆叠式封装结构，包括：第五元器件结构以及如权利要求5所述的封装结构；
其中，所述第五元器件结构设置在所述封装体的上表面的电性连接部上。
所述封装体的侧面的导电结构与外部电路基板电性连接。
本发明实施例还提供了一种堆叠式封装结构，包括：第六元器件结构以及如权利要求6所述的封装结构；
其中，所述第六元器件结构设置在所述封装体的顶部的电性连接部上。
由于封装体的至少一个侧面设置了用于电性连接所述电路载板和所述电性连接部的导电结构，从而使得电路载板的面积不再被占用，避免了导致供元器件贴装的衬底电路载板的面积的缩减。
本发明实施例的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明实施例而了解。本发明实施例的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本发明实施例技术方案的进一步理解，并且构成说明书的一部分，与本申请的实施例一起用于解释本发明实施例的技术方案，并不构成对本发明实施例技术方案的限制。
图1为本发明实施例提供的一种封装结构的示意图；
图2为本发明实施例提供的另一种封装结构的示意图；
图3为本发明实施例提供的又一种封装结构的示意图；
图4为本发明实施例提供的又一种封装结构的示意图；
图5为本发明实施例提供的又一种封装结构的示意图；
图6为本发明实施例提供的一种堆叠式封装结构的示意图；
图7为本发明实施例提供的另一种堆叠式封装结构的示意图；
图8为本发明实施例提供的又一种堆叠式封装结构的示意图；
图9为本发明实施例提供的又一种堆叠式封装结构的示意图；
图10为本发明实施例提供的又一种堆叠式封装结构的示意图；
图11为本发明实施例提供的又一种堆叠式封装结构的示意图；
图12为本发明实施例提供的一种堆叠式封装体结构的立体结构示意图；
图13为本发明实施例提供的又一种堆叠式封装结构的示意图；
图14为本发明实施例提供的又一种堆叠式封装结构的示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚明白，下文中将结合附图对本发明实施例的实施例进行详细说明。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互任意组合。
现有技术中，在封装体内部设置的电性连接焊盘与衬底电路载板的导电结构主要包括：架空金属框架、铜柱和穿模孔(through mold via，TMV)。
架空金属框架：在衬底电路载板上安装一个架空的折叠框架，塑封完后在封装体的表面形成焊盘，供元器件贴装。在该方案中，金属框架的贴装会占用衬底电路载板一定的面积，而且金属框架贴装在衬底电路载板中的位置是固定位置，因此衬底电路载板上元器件的布局会受到限制，并且也不能够提供更多的焊盘，此外框架贴装的平整性影响到表面焊盘，也会影响到封装体的塑封制程。
铜柱：在衬底电路载板上设置贯穿整个封装体的铜柱，并且铜柱贯在封装体表面提供焊盘。在该方案中，虽然铜柱的占衬底电路载板的面积相对小，但是能够提供的表贴焊盘面积也小，并且铜柱数量不能太多，否则会占用较多衬底电路载板的表贴面积。
TMV：通过激光(laser)打孔，填塞导电介质，如锡膏，银浆等，在封装体表面提供焊盘，焊料、银浆实现衬底电路与封装体表贴器件的电性互连。在方案中，穿模孔占用了很多的衬底电路载板的表贴面积，此外焊料、银浆等提供的焊盘容易虚焊，可靠性不高。
为此，本发明实施例提供一种封装结构，该封装结构包括：其中设置有电路载板的封装体和电性连接部，电性连接部设置在封装体的外部，还包括：导电结构。
导电结构设置在封装体的至少一个侧面的外表面，用于电性连接电路载板和电性连接部。
具体的，电性连接部包括但不限于金属焊盘。导电结构包括但不限于导电面，导电面的材质包括但不限于金属和具有导电功能的非金属，例如合金。当导电面的材质是金属时，导电面包括但不限于通过溅射、电镀、化学沉镀、物理气相沉积，(Physical VaporDeposition，PVD)、端头电镀、烧结等方式形成。
具体的，电路载板可以是通过自身的金属连接线与封装体侧面的外表面的导电结构进行电性连接的，即电路载板的侧面的金属连接线能够穿过封装体且到达封装体外部，因此能够与导电结构实现电性互连。
需要说明的是，封装体的封装材料包括但不限于环氧塑封料(Epoxy MoldingCompound，EMC)、环氧树脂+玻纤形成的半固化片、Ajinomoto增层片(Ajinomoto Build-upFilms，ABF)胶、陶瓷等材料。
还需要说明的是，电路载板包括但不限于有机印刷电路板、陶瓷基板、引线(leadframe)框架基板等具有元器件安装、电气互连、机械支撑功能的电路载板。电路载板中至少包括一个元器件，元器件包括但不限于主动器件、被动器件等元器件。主动器件的封装形式可以是裸片、或者已封装好方形扁平无引脚封装(Quad Flat No-leadPackage，QFN)、焊球阵列封装(Ball Grid Array，BGA)、芯片级封装(Chip Scale Package，CSP)、晶圆片级芯片规模封装(Wafer Level Chip Scale Packaging，WLCSP)。封装体中的元器件包括但不限于通过表面贴装技术(Surface Mount Technology，SMT)、倒装芯片(flip chip，FC)和引线键合(Wire Bonding，WB)等互连工艺与的电路载板进行电性互连。
本发明实施例提供的封装结构，由于封装体的至少一个侧面设置了用于电性连接电路载板和电性连接部的导电结构，从而使得电路载板的面积不再被占用，避免了导致供元器件贴装的衬底电路载板的面积的缩减。
可选地，封装体的底部为电路载板。
电性连接部设置在封装体的顶部。
具体的，图1为本发明实施例提供的一种封装结构的示意图，如图1所示，本发明实施例提供的封装结构包括：设置有电路载板10的封装体20和电性连接部30，还包括：导电结构40，封装体20中包括：三个元器件50，电路载板10作为封装体20的底部，元器件50设置在电路载板10上，电性连接部30设置在封装体20的顶部，导电结构40设置在封装体20的左侧面的外表面，用于电性连接电路载板10和电性连接部30。
可选地，封装体的顶部为电路载板。
电性连接部设置在封装体的底部。
具体的，图2为本发明实施例提供的另一种封装结构的示意图，如图2所示，本发明实施例提供的封装结构包括：设置有电路载板10的封装体20和电性连接部30，还包括：导电结构40，封装体20中包括：三个元器件50，电路载板10作为封装体20的顶部，元器件50设置在电路载板10上，电性连接部30设置在封装体20的底部，导电结构40设置在封装体20的左侧面的外表面，用于电性连接电路载板10和电性连接部30。
可选地，电路载板与封装体的顶部和底部的距离均大于预设距离。
可选地，电性连接部设置在封装体的顶部或底部。
需要说明的是，电路载板与封装体的顶部和底部的距离均大于预设距离是为了能够在电路载板的双面上都贴装元器件。
具体的，图3为本发明实施例提供的又一种封装结构的示意图，如图3所示，本发明实施例提供的封装结构包括：其中设置有电路载板10的封装体20和电性连接部30，还包括：导电结构40，封装体20中包括：四个元器件50，电路载板10位于封装体20的内部且与封装体20的顶部和底部均有一定的距离，双面都贴装有元器件50，电性连接部30设置在封装体20的顶部，并导电结构40设置在封装体20的左侧面的外表面，用于电性连接电路载板10和电性连接部30。
具体的，图4为本发明实施例提供的又一种封装结构的示意图，如图4所示，本发明实施例提供的封装结构包括：其中设置有电路载板10的封装体20和电性连接部30，还包括：导电结构40，封装体20中包括：四个元器件50，电路载板10位于封装体20的内部且与封装体20的顶部和底部均有一定的距离，双面都贴装有元器件50，电性连接部30设置在封装体20的底部，并导电结构40设置在封装体20的左侧面的外表面，用于电性连接电路载板10和电性连接部30。
可选地，电性连接部设置在封装体的顶部和底部。
具体的，图5为本发明实施例提供的又一种封装结构的示意图，如图5所示，本发明实施例提供的封装结构包括：其中设置有电路载板10的封装体20和电性连接部30，还包括：导电结构40，封装体20中包括：四个元器件50，电路载板10位于封装体20的内部且与封装体20的顶部和底部均有一定的距离，双面都贴装有元器件50，电性连接部30设置在封装体20的顶部和底部，并导电结构40设置在封装体20的左侧面的外表面，用于电性连接电路载板10和电性连接部30。
本发明实施例提供一种堆叠式封装结构，包括：第一元器件结构以及封装结构。
其中，封装结构包括：设置有电路载板的封装体和电性连接部，电性连接部设置在封装体的外部；还包括：导电结。
导电结构设置在封装体的至少一个侧面的外表面，用于电性连接电路载板和电性连接部。
封装体的底部为电路载板。
电性连接部设置在封装体的顶部。
第一元器件结构设置在电性连接部上。
具体的，图6为本发明实施例提供的一种堆叠式封装结构的示意图，如图6所示，本发明实施例提供的堆叠式封装结构包括：第一元器件结构60以及封装结构，其中，封装结构包括：设置有电路载板10的封装体20和电性连接部30，还包括：导电结构40，封装体20中包括：三个元器件50，电路载板10作为封装体20的顶部，元器件50设置在电路载板10上，电性连接部30设置在封装体20的底部，导电结构40设置在封装体20的左侧面的外表面，用于电性连接电路载板10和电性连接部30，第一元器件结构60设置在电性连接部30上。
图7为本发明实施例提供的另一种堆叠式封装结构的示意图，如图7所示，在图6所示的堆叠式封装结构上，本发明实施例提供的堆叠式封装结构中的第一元器件结构还可以包括：架空元器件。
可选地，封装体的侧面的导电结构与外部电路基板电性连接。
可选地，本发明实施例提供的堆叠式封装结构还包括：第二元器件结构。所述第二元器件结构设置在所述电路载板10的下表面上。
可选地，第一元器件结构和第二元器件结构包括：至少一个元器件。
需要说明的是，第一元器件结构和第二元器件结构还可以是由多个元器件构成的封装体。
可选地，电路载板与外部电路基板电性连接。
本发明实施例提供一种堆叠式封装结构，包括：第三元器件结构和封装结构。
其中，封装结构包括：设置有电路载板的封装体和电性连接部，所述电性连接部设置在所述封装体的外部，还包括：导电结构。
导电结构设置在所述封装体的至少一个侧面的外表面，用于电性连接所述电路载板和所述电性连接部。
封装体的顶部为电路载板。
电性连接部设置在封装体的底部。
第三元器件结构设置在电路载板的上表面上。
具体的，图8为本发明实施例提供的又一种堆叠式封装结构的示意图，如图8所示，本发明实施例提供的堆叠式封装结构包括：第三元器件结构70以及封装结构，其中，封装结构包括：设置有电路载板10的封装体20和电性连接部30，还包括：导电结构40，封装体20中包括：三个元器件50，电路载板10作为封装体20的顶部，元器件50设置在电路载板10上，电性连接部30设置在封装体20的底部，导电结构40设置在封装体20的左侧面的外表面，用于电性连接电路载板10和电性连接部30，第三元器件结构70设置在电路载板40的上表面上。
需要说明的是，本发明实施例提供的堆叠式封装结构将电路载板10用于承载第三元器件结构70，可以充分利用电路载板的密集线路，实现更多元器件或者更多输入/输出(input/output，I/O)数的贴装，同时缩短与封装体内部电路的互连路径提高电路性能
可选地，封装体的侧面的导电结构与外部电路基板电性连接。
可选地，本发明实施例提供的堆叠式封装结构还包括：第四元器件结构。第四元器件结构设置在电性连接部30上。
可选地，述第三元器件结构和第四元器件结构包括：至少一个元器件。
可选地，电性连接部与外部电路基板电性连接。
本发明实施例提供一种堆叠式封装结构，包括：第五元器件结构以及封装结构。
其中，封装结构包括：其中设置有电路载板的封装体和电性连接部，电性连接部设置在封装体的外部，还包括：导电结构。
导电结构设置在封装体的至少一个侧面的外表面，用于电性连接电路载板和电性连接部。
电路载板与封装体的顶部和底部的距离均大于预设距离。
电性连接部设置在封装体的顶部或底部。
第五元器件结构设置在电性连接部上。
封装体的侧面的导电结构与外部电路基板电性连接。
具体的，图9为本发明实施例提供的又一种堆叠式封装结构的示意图，如图9所示，本发明实施例提供的堆叠式封装结构包括：第五元器件结构80以及封装结构，其中，封装结构包括：其中设置有电路载板10的封装体20和电性连接部30，还包括：导电结构40，封装体20中包括：四个元器件50，电路载板10位于封装体20的内部且与封装体20的顶部和底部均有一定的距离，双面都贴装有元器件50，电性连接部30设置在封装体20的顶部，并导电结构40设置在封装体20的左侧面的外表面，用于电性连接电路载板10和电性连接部30，第五元器件结构80设置在封装体的电性连接部30上(即设置在封装体顶部的电性连接部30上)。
图10为本发明实施例提供的又一种堆叠式封装结构的示意图，如图10所示，本发明实施例提供的堆叠式封装结构包括：第五元器件结构80以及封装结构，其中，封装结构包括：其中设置有电路载板10的封装体20和电性连接部30，还包括：导电结构40，封装体20中包括：四个元器件50，电路载板10位于封装体20的内部且与封装体20的顶部和底部均有一定的距离，双面都贴装有元器件50，电性连接部30设置在封装体20的底部，并导电结构40设置在封装体20的左侧面的外表面，用于电性连接电路载板10和电性连接部30，第五元器件结构80设置在封装体的电性连接部30上(即设置在封装体底部的电性连接部30上)。
本发明实施例提供又一种堆叠式封装结构，包括：第六元器件结构以及封装结构。
其中，封装结构包括：其中设置有电路载板的封装体和电性连接部，所述电性连接部设置在所述封装体的外部，还包括：导电结构。
所述导电结构设置在所述封装体的至少一个侧面的外表面，用于电性连接所述电路载板和所述电性连接部。
所述电路载板与所述封装体的顶部和底部的距离均大于预设距离。
电性连接部设置在所述封装体的顶部和底部。
所述第六元器件结构设置在所述封装体的顶部的电性连接部上。
具体的，图11为本发明实施例提供的又一种堆叠式封装结构的示意图，如图11所示，本发明实施例提供的堆叠式封装结构包括：第六元器件结构90以及封装结构，其中，封装结构包括：其中设置有电路载板10的封装体20和电性连接部30，还包括：导电结构40，封装体20中包括：四个元器件50，电路载板10位于封装体20的内部且与封装体20的顶部和底部均有一定的距离，双面都贴装有元器件50，电性连接部30设置在封装体20的底部，并导电结构40设置在封装体20的左侧面的外表面，用于电性连接电路载板10和电性连接部30，第六元器件结构90设置在封装体20的顶部的电性连接部30上。
可选地，所述封装体的侧面的导电结构与外部电路基板电性连接。
具体的，图12为本发明实施例提供的一种堆叠式封装体结构的立体结构示意图，其中，电性连接部30、元器件50和第六元器件结构90已省略，如图12所示，该堆叠式封装结构可以通过封装体的侧面的导电结构40与外部电路基板电性连接，这样一方面可以占用外部电路基板中更少的面积且双面散热，还可以在封装体的顶部和底部设置更多的电性连接部。图13为本发明实施例提供的又一种堆叠式封装结构的示意图，该实施例是从封装体侧面展示的结构示意图，如图13所示，封装体的顶部和底部均设置有电性连接部30，以供电器结构的贴装。
可选地，本发明实施例提供的堆叠式封装结构还包括：第七元器件结构。
所述第七元器件结构设置在所述封装体的底部的电性连接部上。
可选地，第六元器件结构和第七元器件结构包括：至少一个元器件。
可选地，述封装体的底部的电性连接部与外部电路基板电性连接。
需要说明的是，本发明实施例提供的堆叠式封装结构可以使得元器件结构堆叠在封装体上方，充分利用了Z方向的空间，缩小了模块的尺寸；此外，利用侧壁的空间做互连导通层，既减少了在外部电路基板上的占用面积，又为封装体内部的元器件提供了更大的贴装面积，还能够利用侧面导电结构达到散热的目的。而相较于其他堆叠电子封装结构，本发明实施例的优势在于Z向互连没有占用封装体的表贴空间，使得布线、器件布局更自由，并且侧面导电结构有利于散热、电磁屏蔽。
需要说明的是，本发明实施例提供的堆叠式封装结构可以包括两个及两个以上的封装结构，图14为本发明实施例提供的又一种堆叠式封装结构的示意图，如图14所示，该堆叠式封装结构包括2个封装结构。
虽然本发明实施例所揭露的实施方式如上，但所述的内容仅为便于理解本发明实施例而采用的实施方式，并非用以限定本发明实施例。任何本发明实施例所属领域内的技术人员，在不脱离本发明实施例所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本发明实施例的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (22)

1.一种封装结构，包括：其中设置有电路载板的封装体和电性连接部，所述电性连接部设置在所述封装体的外部，其特征在于，还包括：导电结构；
所述导电结构设置在所述封装体的至少一个侧面的外表面，用于电性连接所述电路载板和所述电性连接部；
所述封装体中包括元器件，所述元器件设置在所述电路载板上、且所述元器件是贴装在所述电路载板上的；
所述电路载板设置有金属连接线，所述电路载板的侧面的金属连接线穿过所述封装体且到达所述封装体外部，以实现所述电路载板与所述导电结构的电性互连；
两个及两个以上的所述封装结构在垂直于所述电路载板的方向上堆叠设置。
2.根据权利要求1所述的封装结构，其特征在于，所述封装体的底部为所述电路载板；
所述电性连接部设置在所述封装体的顶部。
3.根据权利要求1所述的封装结构，其特征在于，所述封装体的顶部为所述电路载板；
所述电性连接部设置在所述封装体的底部。
4.根据权利要求1所述的封装结构，其特征在于，所述电路载板与所述封装体的顶部和底部的距离均大于预设距离。
5.根据权利要求4所述的封装结构，其特征在于，所述电性连接部设置在所述封装体的顶部或底部。
6.根据权利要求4所述的封装结构，其特征在于，所述电性连接部设置在所述封装体的顶部和底部。
7.一种堆叠式封装结构，其特征在于，包括：第一元器件结构以及如权利要求2所述的封装结构；
其中，所述第一元器件结构设置在所述电性连接部上。
8.根据权利要求7所述的堆叠式封装结构，其特征在于，所述封装体的侧面的导电结构与外部电路基板电性连接。
9.根据权利要求8所述的堆叠式封装结构，其特征在于，还包括：第二元器件结构；
所述第二元器件结构设置在所述电路载板的下表面上。
10.根据权利要求9所述的堆叠式封装结构，其特征在于，所述第一元器件结构和所述第二元器件结构包括：至少一个元器件。
11.根据权利要求7所述的堆叠式封装结构，其特征在于，所述电路载板与外部电路基板电性连接。
12.一种堆叠式封装结构，其特征在于，包括：第三元器件结构以及如权利要求3所述的封装结构；
其中，所述第三元器件结构设置在所述电路载板的上表面上。
13.根据权利要求12所述的堆叠式封装结构，其特征在于，所述封装体的侧面的导电结构与外部电路基板电性连接。
14.根据权利要求13所述的堆叠式封装结构，其特征在于，还包括：第四元器件结构；
所述第四元器件结构设置在所述电性连接部上。
15.根据权利要求14所述的堆叠式封装结构，其特征在于，所述第三元器件结构和所述第四元器件结构包括：至少一个元器件。
16.根据权利要求12所述的堆叠式封装结构，其特征在于，所述电性连接部与外部电路基板电性连接。
17.一种堆叠式封装结构，其特征在于，包括：第五元器件结构以及如权利要求5所述的封装结构；
其中，所述第五元器件结构设置在所述电性连接部上；
所述封装体的侧面的导电结构与外部电路基板电性连接。
18.一种堆叠式封装结构，其特征在于，包括：第六元器件结构以及如权利要求6所述的封装结构；
其中，所述第六元器件结构设置在所述封装体的顶部的电性连接部上。
19.根据权利要求18所述的堆叠式封装结构，其特征在于，所述封装体的侧面的导电结构与外部电路基板电性连接。
20.根据权利要求19所述的堆叠式封装结构，其特征在于，还包括：第七元器件结构；
所述第七元器件结构设置在所述封装体的底部的电性连接部上。
21.根据权利要求20所述的堆叠式封装结构，其特征在于，所述第六元器件结构和所述第七元器件结构包括：至少一个元器件。
22.根据权利要求18所述的堆叠式封装结构，其特征在于，所述封装体的底部的电性连接部与外部电路基板电性连接。
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