CN101159436B - 解码设备及方法 - Google Patents
解码设备及方法 Download PDFInfo
- Publication number
- CN101159436B CN101159436B CN2007101822893A CN200710182289A CN101159436B CN 101159436 B CN101159436 B CN 101159436B CN 2007101822893 A CN2007101822893 A CN 2007101822893A CN 200710182289 A CN200710182289 A CN 200710182289A CN 101159436 B CN101159436 B CN 101159436B
- Authority
- CN
- China
- Prior art keywords
- submatrix
- bit
- ldpc
- limit message
- matrix
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
- H03M13/1162—Array based LDPC codes, e.g. array codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1111—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
- H03M13/1117—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms using approximations for check node processing, e.g. an outgoing message is depending on the signs and the minimum over the magnitudes of all incoming messages according to the min-sum rule
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1111—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
- H03M13/1117—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms using approximations for check node processing, e.g. an outgoing message is depending on the signs and the minimum over the magnitudes of all incoming messages according to the min-sum rule
- H03M13/112—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms using approximations for check node processing, e.g. an outgoing message is depending on the signs and the minimum over the magnitudes of all incoming messages according to the min-sum rule with correction functions for the min-sum rule, e.g. using an offset or a scaling factor
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1111—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
- H03M13/1117—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms using approximations for check node processing, e.g. an outgoing message is depending on the signs and the minimum over the magnitudes of all incoming messages according to the min-sum rule
- H03M13/1122—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms using approximations for check node processing, e.g. an outgoing message is depending on the signs and the minimum over the magnitudes of all incoming messages according to the min-sum rule storing only the first and second minimum values per check node
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1111—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
- H03M13/1125—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms using different domains for check node and bit node processing, wherein the different domains include probabilities, likelihood ratios, likelihood differences, log-likelihood ratios or log-likelihood difference pairs
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1131—Scheduling of bit node or check node processing
- H03M13/1137—Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1131—Scheduling of bit node or check node processing
- H03M13/114—Shuffled, staggered, layered or turbo decoding schedules
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
- H03M13/1185—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
- H03M13/615—Use of computational or mathematical techniques
- H03M13/616—Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6502—Reduction of hardware complexity or efficient processing
- H03M13/6505—Memory efficient implementations
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6577—Representation or format of variables, register sizes or word-lengths and quantization
- H03M13/658—Scaling by multiplication or division
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6577—Representation or format of variables, register sizes or word-lengths and quantization
- H03M13/6583—Normalization other than scaling, e.g. by subtraction
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
- H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Probability & Statistics with Applications (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- General Physics & Mathematics (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Algebra (AREA)
- Computing Systems (AREA)
- Error Detection And Correction (AREA)
Abstract
Description
LDPC解码器类型 | 单元类型 | 时钟 | 时间边缘 | 面积(mm<sup>2</sup>) | 功率 | 未编码数据吞吐量 |
现有技术的传统最小和LDPC解码器 | 低/标准Vt | 400/200MHz | 20% | 3.5 | 0.69W | 2.08Gbps |
基于重叠子矩阵的LDPC解码器:6输入的72比特引擎(6比特) | 标准Vt | 250MHz | 20% | 1.71 | 0.33W | 2.02Gbps |
Claims (10)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US84883406P | 2006-10-02 | 2006-10-02 | |
US60/848,834 | 2006-10-02 | ||
US11/709,078 US7644339B2 (en) | 2006-10-02 | 2007-02-21 | Overlapping sub-matrix based LDPC (low density parity check) decoder |
US11/709,078 | 2007-02-21 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101159436A CN101159436A (zh) | 2008-04-09 |
CN101159436B true CN101159436B (zh) | 2010-04-21 |
Family
ID=39012268
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2007101822893A Active CN101159436B (zh) | 2006-10-02 | 2007-10-08 | 解码设备及方法 |
Country Status (6)
Country | Link |
---|---|
US (3) | US7644339B2 (zh) |
EP (1) | EP1909394A3 (zh) |
KR (1) | KR100915368B1 (zh) |
CN (1) | CN101159436B (zh) |
HK (1) | HK1121595A1 (zh) |
TW (1) | TWI371168B (zh) |
Families Citing this family (52)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070245217A1 (en) * | 2006-03-28 | 2007-10-18 | Stmicroelectronics S.R.L. | Low-density parity check decoding |
KR100864838B1 (ko) * | 2006-12-05 | 2008-10-23 | 한국전자통신연구원 | 저밀도 패리티 검사 부호의 검사노드를 갱신하는 방법 및장치 |
KR100938068B1 (ko) * | 2007-01-30 | 2010-01-21 | 삼성전자주식회사 | 통신 시스템에서 신호 수신 장치 및 방법 |
TW200838160A (en) * | 2007-03-09 | 2008-09-16 | Univ Nat Chiao Tung | Cyclic comparison method of low density parity check decoder |
KR101227514B1 (ko) * | 2007-03-15 | 2013-01-31 | 엘지전자 주식회사 | Ldpc 부호화 및 복호화를 위한 모델 행렬을 구성하는방법 |
US8359522B2 (en) * | 2007-05-01 | 2013-01-22 | Texas A&M University System | Low density parity check decoder for regular LDPC codes |
US8010881B2 (en) * | 2007-07-02 | 2011-08-30 | Broadcom Corporation | Multi-code LDPC (low density parity check) decoder |
JP4596027B2 (ja) * | 2008-03-25 | 2010-12-08 | ブラザー工業株式会社 | 通信システム |
US8370711B2 (en) | 2008-06-23 | 2013-02-05 | Ramot At Tel Aviv University Ltd. | Interruption criteria for block decoding |
WO2009156935A1 (en) * | 2008-06-23 | 2009-12-30 | Ramot At Tel Aviv University Ltd. | Using damping factors to overcome ldpc trapping sets |
US20090319860A1 (en) * | 2008-06-23 | 2009-12-24 | Ramot At Tel Aviv University Ltd. | Overcoming ldpc trapping sets by decoder reset |
US20100037121A1 (en) * | 2008-08-05 | 2010-02-11 | The Hong Kong University Of Science And Technology | Low power layered decoding for low density parity check decoders |
EP2223431A1 (en) * | 2008-08-15 | 2010-09-01 | Lsi Corporation | Ram list-decoding of near codewords |
US8145986B2 (en) * | 2008-09-22 | 2012-03-27 | Broadcom Corporation | Multi-CSI (Cyclic Shifted Identity) sub-matrix based LDPC (Low Density Parity Check) codes |
US8161345B2 (en) | 2008-10-29 | 2012-04-17 | Agere Systems Inc. | LDPC decoders using fixed and adjustable permutators |
US9356623B2 (en) | 2008-11-26 | 2016-05-31 | Avago Technologies General Ip (Singapore) Pte. Ltd. | LDPC decoder variable node units having fewer adder stages |
US8335979B2 (en) * | 2008-12-08 | 2012-12-18 | Samsung Electronics Co., Ltd. | Contention-free parallel processing multimode LDPC decoder |
US8347167B2 (en) * | 2008-12-19 | 2013-01-01 | Lsi Corporation | Circuits for implementing parity computation in a parallel architecture LDPC decoder |
CN101903890B (zh) | 2009-03-05 | 2015-05-20 | Lsi公司 | 用于迭代解码器的改进的turbo均衡方法 |
JP2010212934A (ja) * | 2009-03-10 | 2010-09-24 | Toshiba Corp | 半導体装置 |
JP5440836B2 (ja) * | 2009-03-24 | 2014-03-12 | ソニー株式会社 | 受信装置及び方法、プログラム、並びに受信システム |
KR101321487B1 (ko) | 2009-04-21 | 2013-10-23 | 에이저 시스템즈 엘엘시 | 기입 검증을 사용한 코드들의 에러-플로어 완화 |
US8578256B2 (en) * | 2009-04-22 | 2013-11-05 | Agere Systems Llc | Low-latency decoder |
KR100953936B1 (ko) * | 2009-04-28 | 2010-04-22 | 엘아이지넥스원 주식회사 | Ldpc 복호화를 위한 복호화 방법 및 장치 |
US8677209B2 (en) * | 2009-11-19 | 2014-03-18 | Lsi Corporation | Subwords coding using different encoding/decoding matrices |
US8352847B2 (en) * | 2009-12-02 | 2013-01-08 | Lsi Corporation | Matrix vector multiplication for error-correction encoding and the like |
US8464142B2 (en) | 2010-04-23 | 2013-06-11 | Lsi Corporation | Error-correction decoder employing extrinsic message averaging |
US8499226B2 (en) | 2010-06-29 | 2013-07-30 | Lsi Corporation | Multi-mode layered decoding |
US8458555B2 (en) | 2010-06-30 | 2013-06-04 | Lsi Corporation | Breaking trapping sets using targeted bit adjustment |
US8504900B2 (en) | 2010-07-02 | 2013-08-06 | Lsi Corporation | On-line discovery and filtering of trapping sets |
US8621289B2 (en) | 2010-07-14 | 2013-12-31 | Lsi Corporation | Local and global interleaving/de-interleaving on values in an information word |
JP5310701B2 (ja) * | 2010-10-29 | 2013-10-09 | 株式会社Jvcケンウッド | 復号装置および復号方法 |
US8768990B2 (en) | 2011-11-11 | 2014-07-01 | Lsi Corporation | Reconfigurable cyclic shifter arrangement |
US20130139022A1 (en) * | 2011-11-28 | 2013-05-30 | Lsi Corporation | Variable Sector Size LDPC Decoder |
US20130139023A1 (en) * | 2011-11-28 | 2013-05-30 | Lsi Corporation | Variable Sector Size Interleaver |
US9037938B2 (en) * | 2012-10-30 | 2015-05-19 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Hardware architecture and implementation of low power layered multi-level LDPC decoder |
RU2012146685A (ru) | 2012-11-01 | 2014-05-10 | ЭлЭсАй Корпорейшн | База данных наборов-ловушек для декодера на основе разреженного контроля четности |
KR102068030B1 (ko) * | 2012-12-11 | 2020-01-20 | 삼성전자 주식회사 | 메모리 컨트롤러 및 그 동작방법 |
WO2015041480A1 (en) * | 2013-09-18 | 2015-03-26 | Samsung Electronics Co., Ltd. | Transmitter and signal processing method thereof |
KR102202385B1 (ko) * | 2013-09-18 | 2021-01-13 | 삼성전자주식회사 | 송신 장치 및 그의 신호 처리 방법 |
TWI536749B (zh) * | 2013-12-09 | 2016-06-01 | 群聯電子股份有限公司 | 解碼方法、記憶體儲存裝置與記憶體控制電路單元 |
CN105680877B (zh) * | 2014-11-19 | 2019-06-28 | 香港理工大学 | 一种cc-qc-ldpc码的构建方法及译码装置 |
CN104579362B (zh) * | 2014-12-30 | 2017-10-24 | 北京遥测技术研究所 | 一种空间通信系统中部分并行结构ldpc码译码系统及其方法 |
CN106209114B (zh) * | 2015-04-29 | 2019-11-12 | 深圳忆联信息系统有限公司 | 译码方法及装置 |
KR101666188B1 (ko) * | 2015-08-27 | 2016-10-13 | 고려대학교 산학협력단 | 중첩을 이용한 dvb-s2 기반 저밀도 패리티 검사(ldpc) 부호의 복호기 설계기법 |
US10367526B2 (en) * | 2015-11-23 | 2019-07-30 | Avago Technologies International Sales Pte. Limited | Irregular low density parity check processing system with non-uniform scaling |
CN108347298B (zh) * | 2017-01-24 | 2021-01-15 | 华为技术有限公司 | 一种编码的方法和通信装置 |
US10963337B2 (en) * | 2018-01-08 | 2021-03-30 | SK Hynix Inc. | Memory system with super chip-kill recovery and method of operating such memory system |
KR102092634B1 (ko) * | 2018-10-12 | 2020-04-23 | 고려대학교 산학협력단 | Ldpc 부호 복호기 및 복호 방법 |
KR20200114151A (ko) * | 2019-03-27 | 2020-10-07 | 에스케이하이닉스 주식회사 | 오류 정정 디코더 |
CN112583420B (zh) * | 2019-09-30 | 2024-01-09 | 上海华为技术有限公司 | 一种数据处理方法和译码器 |
KR102525414B1 (ko) * | 2020-07-29 | 2023-04-25 | 한국전자통신연구원 | LDPC(low-density parity-check) 부호의 복호화 방법 및 장치 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060123315A1 (en) * | 2004-11-08 | 2006-06-08 | Kabushiki Kaisha Toshiba | Decoder and method for decoding low-density parity-check code |
CN1805292A (zh) * | 2005-01-10 | 2006-07-19 | 美国博通公司 | 构建对应基于grs不规则ldpc码的奇偶校验矩阵的方法 |
CN1825770A (zh) * | 2005-02-26 | 2006-08-30 | 美国博通公司 | 解码ldpc编码信号的加速消息传递解码器和方法 |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3542756A (en) * | 1968-02-07 | 1970-11-24 | Codex Corp | Error correcting |
US3665396A (en) * | 1968-10-11 | 1972-05-23 | Codex Corp | Sequential decoding |
US4295218A (en) * | 1979-06-25 | 1981-10-13 | Regents Of The University Of California | Error-correcting coding system |
US6430233B1 (en) * | 1999-08-30 | 2002-08-06 | Hughes Electronics Corporation | Single-LNB satellite data receiver |
FR2799592B1 (fr) * | 1999-10-12 | 2003-09-26 | Thomson Csf | Procede de construction et de codage simple et systematique de codes ldpc |
US6473010B1 (en) * | 2000-04-04 | 2002-10-29 | Marvell International, Ltd. | Method and apparatus for determining error correction code failure rate for iterative decoding algorithms |
US6567465B2 (en) * | 2001-05-21 | 2003-05-20 | Pc Tel Inc. | DSL modem utilizing low density parity check codes |
US6633856B2 (en) * | 2001-06-15 | 2003-10-14 | Flarion Technologies, Inc. | Methods and apparatus for decoding LDPC codes |
US7246304B2 (en) * | 2001-09-01 | 2007-07-17 | Dsp Group Inc | Decoding architecture for low density parity check codes |
US7350130B2 (en) * | 2002-08-15 | 2008-03-25 | Broadcom Corporation | Decoding LDPC (low density parity check) code with new operators based on min* operator |
US7216283B2 (en) * | 2003-06-13 | 2007-05-08 | Broadcom Corporation | Iterative metric updating when decoding LDPC (low density parity check) coded signals and LDPC coded modulation signals |
US7296208B2 (en) * | 2003-07-03 | 2007-11-13 | The Directv Group, Inc. | Method and system for generating parallel decodable low density parity check (LDPC) codes |
US7406648B2 (en) * | 2003-12-24 | 2008-07-29 | Electronics And Telecommunications Research Institute | Methods for coding and decoding LDPC codes, and method for forming LDPC parity check matrix |
US7243287B2 (en) * | 2004-05-03 | 2007-07-10 | Broadcom Corporation | Decoding LDPC (Low Density Parity Check) code and graphs using multiplication (or addition in log-domain) on both sides of bipartite graph |
JP4282558B2 (ja) | 2004-06-30 | 2009-06-24 | 株式会社東芝 | 低密度パリティチェック符号復号器及び方法 |
US7127659B2 (en) * | 2004-08-02 | 2006-10-24 | Qualcomm Incorporated | Memory efficient LDPC decoding methods and apparatus |
CN101395804B (zh) * | 2004-09-17 | 2011-09-07 | Lg电子株式会社 | 使用ldpc码编码和解码的方法 |
US20060085720A1 (en) | 2004-10-04 | 2006-04-20 | Hau Thien Tran | Message passing memory and barrel shifter arrangement in LDPC (Low Density Parity Check) decoder supporting multiple LDPC codes |
WO2006059688A1 (ja) | 2004-12-02 | 2006-06-08 | Mitsubishi Denki Kabushiki Kaisha | 復号装置及び通信装置 |
KR100846869B1 (ko) * | 2004-12-16 | 2008-07-16 | 한국전자통신연구원 | 저 복잡도 ldpc복호 장치 및 그 방법 |
-
2007
- 2007-02-21 US US11/709,078 patent/US7644339B2/en not_active Expired - Fee Related
- 2007-08-24 EP EP07016656A patent/EP1909394A3/en not_active Withdrawn
- 2007-10-01 TW TW096136768A patent/TWI371168B/zh not_active IP Right Cessation
- 2007-10-02 KR KR1020070099446A patent/KR100915368B1/ko not_active IP Right Cessation
- 2007-10-08 CN CN2007101822893A patent/CN101159436B/zh active Active
-
2008
- 2008-09-19 HK HK08110393.4A patent/HK1121595A1/xx not_active IP Right Cessation
-
2010
- 2010-01-01 US US12/651,453 patent/US8230298B2/en not_active Expired - Fee Related
-
2012
- 2012-07-16 US US13/549,577 patent/US8327221B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060123315A1 (en) * | 2004-11-08 | 2006-06-08 | Kabushiki Kaisha Toshiba | Decoder and method for decoding low-density parity-check code |
CN1805292A (zh) * | 2005-01-10 | 2006-07-19 | 美国博通公司 | 构建对应基于grs不规则ldpc码的奇偶校验矩阵的方法 |
CN1825770A (zh) * | 2005-02-26 | 2006-08-30 | 美国博通公司 | 解码ldpc编码信号的加速消息传递解码器和方法 |
Also Published As
Publication number | Publication date |
---|---|
EP1909394A3 (en) | 2009-09-30 |
US20100138721A1 (en) | 2010-06-03 |
EP1909394A2 (en) | 2008-04-09 |
CN101159436A (zh) | 2008-04-09 |
TW200835168A (en) | 2008-08-16 |
KR20080031136A (ko) | 2008-04-08 |
US20120284583A1 (en) | 2012-11-08 |
US7644339B2 (en) | 2010-01-05 |
US8327221B2 (en) | 2012-12-04 |
HK1121595A1 (en) | 2009-04-24 |
US8230298B2 (en) | 2012-07-24 |
TWI371168B (en) | 2012-08-21 |
KR100915368B1 (ko) | 2009-09-03 |
US20080082868A1 (en) | 2008-04-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN101159436B (zh) | 解码设备及方法 | |
US11824558B2 (en) | Method and apparatus for encoding and decoding of low density parity check codes | |
CN101340194B (zh) | 解码ldpc编码信号的解码器 | |
US8516347B1 (en) | Non-binary LDPC extrinsic calculation unit (LECU) for iterative decoding | |
US20080104474A1 (en) | Low Density Parity Check (Ldpc) Decoder | |
US10848183B2 (en) | Method and apparatus for encoding and decoding low density parity check codes | |
US10727870B2 (en) | Method and apparatus for encoding and decoding low density parity check codes | |
EP1696574A1 (en) | AMP (Accelerated Message Passing) decoder adapted for LDPC (Low Density Parity Check) codes | |
US9362952B2 (en) | Apparatuses and methods for encoding and decoding of parity check codes | |
US9825650B2 (en) | Decoder architecture for cyclically-coupled quasi-cyclic low-density parity-check codes | |
EP2991231A1 (en) | Multilevel encoding and multistage decoding | |
CN101364809B (zh) | 解码器 | |
US9154261B2 (en) | Low density parity check (LDPC) coding in communication systems |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
REG | Reference to a national code |
Ref country code: HK Ref legal event code: DE Ref document number: 1121595 Country of ref document: HK |
|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
REG | Reference to a national code |
Ref country code: HK Ref legal event code: GR Ref document number: 1121595 Country of ref document: HK |
|
TR01 | Transfer of patent right | ||
TR01 | Transfer of patent right |
Effective date of registration: 20180514 Address after: Singapore Singapore Patentee after: Avago Technologies Fiber IP Singapore Pte. Ltd. Address before: Alton Park Road, Irvine, California, 16215, 92618-7013 Patentee before: Zyray Wireless Inc. |
|
TR01 | Transfer of patent right | ||
TR01 | Transfer of patent right |
Effective date of registration: 20190828 Address after: Singapore Singapore Patentee after: Annwa high tech Limited by Share Ltd Address before: Singapore Singapore Patentee before: Avago Technologies Fiber IP Singapore Pte. Ltd. |