KR100938068B1 - 통신 시스템에서 신호 수신 장치 및 방법 - Google Patents
통신 시스템에서 신호 수신 장치 및 방법 Download PDFInfo
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- KR100938068B1 KR100938068B1 KR1020070009472A KR20070009472A KR100938068B1 KR 100938068 B1 KR100938068 B1 KR 100938068B1 KR 1020070009472 A KR1020070009472 A KR 1020070009472A KR 20070009472 A KR20070009472 A KR 20070009472A KR 100938068 B1 KR100938068 B1 KR 100938068B1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0057—Block codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1111—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
- H03M13/1117—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms using approximations for check node processing, e.g. an outgoing message is depending on the signs and the minimum over the magnitudes of all incoming messages according to the min-sum rule
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6502—Reduction of hardware complexity or efficient processing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
- H04L1/0047—Decoding adapted to other signal detection operation
- H04L1/005—Iterative decoding, including iteration between signal detection and decoding operation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
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Abstract
Description
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비교기 | OUT | ||||||
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Claims (2)
- 통신 시스템에서 저밀도 패리티 검사(LDPC: Low Density Parity Check) 부호의 검사 노드 연산기의 신호 수신 방법에 있어서,직렬 연결된 1개의 입력기 및 dc-1개의 지연 노드들은 입력 메시지를 구성하는 dc개의 값들을 순차적으로 입력하는 제1과정과,비교기는 상기 지연 노드들로 입력된 dc-1개의 값들을 비교하여 최소인 값을 상기 검사 노드 연산기의 출력 메시지로서 출력하는 제2과정과,소정 제어에 따라 상기 입력 메시지를 구성하는 dc개의 값들의 순서를 순환이동하면서 상기 제1과정 및 상기 제2과정을 dc-1번 반복 수행하는 제3과정을 포함하는 LDPC 부호의 검사 노드 연산기의 신호 수신 방법.
- 통신 시스템의 저밀도 패리티 검사(LDPC: Low Density Parity Check) 부호의 검사노드 연산기 장치에 있어서,입력 메시지를 구성하는 dc개의 값들을 순차적으로 입력하는 직렬 연결된 1개의 입력기 및 dc-1개의 지연 노드들과,상기 지연 노드들로 입력된 dc-1개의 값들을 비교하는 비교기와,상기 비교기가 비교한 값들 중 최소인 값을 상기 검사 노드 연산기의 출력 메시지로서 출력하는 출력기와,소정 제어에 따라 상기 입력 메시지를 구성하는 dc개의 값들의 순서를 순환이동 시키면서, 상기 비교기의 동작을 dc번 반복 수행시키는 제어기를 포함하는 LDPC 부호의 검사 노드 연산기 장치.
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KR1020070009472A KR100938068B1 (ko) | 2007-01-30 | 2007-01-30 | 통신 시스템에서 신호 수신 장치 및 방법 |
US12/012,127 US8259591B2 (en) | 2007-01-30 | 2008-01-30 | Apparatus and method for receiving signal in a communication system |
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KR1020070009472A KR100938068B1 (ko) | 2007-01-30 | 2007-01-30 | 통신 시스템에서 신호 수신 장치 및 방법 |
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Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
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US8989050B2 (en) * | 2011-12-01 | 2015-03-24 | Telefonaktiebolaget L M Ericsson (Publ) | Graph-based distributed coordination methods for wireless communication networks |
US8879428B2 (en) * | 2011-12-01 | 2014-11-04 | Telefonaktiebolaget L M Ericsson (Publ) | Systems and method for graph-based distributed parameter coordination in a communication network |
US9743397B2 (en) | 2013-11-14 | 2017-08-22 | Telefonaktiebolaget L M Ericsson (Publ) | Reduced-size message pass in factor graphs for wireless communications networks |
WO2023023712A1 (en) * | 2021-08-23 | 2023-03-02 | Newsouth Innovations Pty Limited | Low-density parity-check decoder |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20040056972A (ko) * | 2002-12-24 | 2004-07-01 | 한국전자통신연구원 | 계산이 간단한 저밀도 패리티 검사 부호를 위한 메시지 전달 복호기 |
US7017106B2 (en) | 2002-08-15 | 2006-03-21 | Broadcom Corporation | Low density parity check (LDPC) code decoder using min*, min**, max* or max** and their respective inverses |
KR20060044395A (ko) * | 2004-03-22 | 2006-05-16 | 스미토모덴키고교가부시키가이샤 | 저밀도 패리티검사부호화방식에 따라서 실현되는 복호장치및 전처리장치 |
US7149953B2 (en) | 2004-02-03 | 2006-12-12 | Broadcom Corporation | Efficient LDPC code decoding with new minus operator in a finite precision radix system |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020034269A1 (en) * | 2000-07-28 | 2002-03-21 | Victor Demjanenko | Use of soft-decision or sum-product inner coders to improve the performance of outer coders |
US7415079B2 (en) * | 2000-09-12 | 2008-08-19 | Broadcom Corporation | Decoder design adaptable to decode coded signals using min* or max* processing |
US6847678B2 (en) * | 2002-04-25 | 2005-01-25 | Raytheon Company | Adaptive air interface waveform |
US7702986B2 (en) * | 2002-11-18 | 2010-04-20 | Qualcomm Incorporated | Rate-compatible LDPC codes |
US7174495B2 (en) * | 2003-12-19 | 2007-02-06 | Emmanuel Boutillon | LDPC decoder, corresponding method, system and computer program |
US7395494B2 (en) * | 2003-12-22 | 2008-07-01 | Electronics And Telecommunications Research Institute | Apparatus for encoding and decoding of low-density parity-check codes, and method thereof |
US7769798B2 (en) * | 2004-04-27 | 2010-08-03 | Amir Banihashemi | Full CMOS min-sum analog iterative decoders |
US7127659B2 (en) * | 2004-08-02 | 2006-10-24 | Qualcomm Incorporated | Memory efficient LDPC decoding methods and apparatus |
EP1909395B1 (en) * | 2005-07-13 | 2019-11-20 | Mitsubishi Electric Corporation | Communication apparatus and decoding method |
JP4320418B2 (ja) * | 2005-09-26 | 2009-08-26 | 日本電気株式会社 | 復号装置および受信装置 |
US20070245217A1 (en) * | 2006-03-28 | 2007-10-18 | Stmicroelectronics S.R.L. | Low-density parity check decoding |
US7607075B2 (en) * | 2006-07-17 | 2009-10-20 | Motorola, Inc. | Method and apparatus for encoding and decoding data |
US20080028282A1 (en) * | 2006-07-25 | 2008-01-31 | Legend Silicon | receiver architecture having a ldpc decoder with an improved llr update method for memory reduction |
US7831895B2 (en) * | 2006-07-25 | 2010-11-09 | Communications Coding Corporation | Universal error control coding system for digital communication and data storage systems |
US7644339B2 (en) * | 2006-10-02 | 2010-01-05 | Broadcom Corporation | Overlapping sub-matrix based LDPC (low density parity check) decoder |
-
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- 2008-01-30 US US12/012,127 patent/US8259591B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7017106B2 (en) | 2002-08-15 | 2006-03-21 | Broadcom Corporation | Low density parity check (LDPC) code decoder using min*, min**, max* or max** and their respective inverses |
KR20040056972A (ko) * | 2002-12-24 | 2004-07-01 | 한국전자통신연구원 | 계산이 간단한 저밀도 패리티 검사 부호를 위한 메시지 전달 복호기 |
US7149953B2 (en) | 2004-02-03 | 2006-12-12 | Broadcom Corporation | Efficient LDPC code decoding with new minus operator in a finite precision radix system |
KR20060044395A (ko) * | 2004-03-22 | 2006-05-16 | 스미토모덴키고교가부시키가이샤 | 저밀도 패리티검사부호화방식에 따라서 실현되는 복호장치및 전처리장치 |
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US8259591B2 (en) | 2012-09-04 |
KR20080071346A (ko) | 2008-08-04 |
US20080212549A1 (en) | 2008-09-04 |
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