CN101140876A - 闪速存储器件 - Google Patents

闪速存储器件 Download PDF

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CN101140876A
CN101140876A CNA2007101456384A CN200710145638A CN101140876A CN 101140876 A CN101140876 A CN 101140876A CN A2007101456384 A CNA2007101456384 A CN A2007101456384A CN 200710145638 A CN200710145638 A CN 200710145638A CN 101140876 A CN101140876 A CN 101140876A
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张郑烈
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DB HiTek Co Ltd
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Abstract

本发明涉及闪速存储器件以及制造闪速存储器件的方法，其通过在曝光工艺中获得焦点深度(DOF)提高了工艺可靠性。在实施方式中，该方法包括在半导体衬底上顺序层叠氧化物膜、浮置栅极多晶硅膜、氧化物－氮化物－氧化物膜、控制栅极多晶硅膜和BARC(底部抗反射涂层)，在底部抗反射涂层上形成用于叠层栅极的光刻胶图案，和通过使用光刻胶图案一次蚀刻BARC、控制栅极多晶硅膜、氧化物－氮化物－氧化物膜和浮置栅极多晶硅膜直到暴露出氧化物膜。

Description

闪速存储器件
本申请要求2006年9月6日提出的韩国专利申请No.10-2006-0085485的优先权，在此将其结合进来作为参考。
技术领域
本发明涉及闪速存储器件的制造方法，尤其涉及一种通过在曝光工序中获得焦点深度(DOF)提高工艺可靠性的闪速存储器件的制造方法。
背景技术
栅极耦合系数是确定闪速存储器件中存储单元效率的一个重要因素。栅极耦合系数对浮置栅的电势有重要影响。在具有较高栅极耦合系数的闪速存储器件中浮置栅的电势与存储单元中控制栅的给定电势相近。因此，能提高闪速存储单元的性能，包括编程和擦除效率以及快速读取速度。
高的栅极耦合率能简化芯片设计，并且能将闪速存储单元的工作电压降低至较低的电源电压。也就是，确定栅极耦合系数的重要因素是各多晶硅之间的电容与隧道氧化物电容的比，即，浮置栅极多晶硅和控制栅极多晶硅之间的电容。随着各多晶硅之间的电容增加和隧道氧化物电容降低，栅极耦合系数会增加。
图1A至1C是示出具有叠层栅极结构的闪速存储器件的相关技术制造方法的截面图。相关技术闪速存储器件包括半导体衬底10、氧化物膜11、浮置栅极多晶膜12(floating gate poly film)、ONO膜13、控制栅极多晶膜14、底部抗反射涂层(BARC)15和光刻胶图案16。
在相关技术蚀刻方法中，可首先使用光刻胶图案16来蚀刻BARC 15(如图1B中所示)。顺序地蚀刻浮置栅极多晶膜12、ONO膜13和控制栅极多晶膜14(如图1C中所示)。
关于具有叠层栅极结构的相关技术闪速存储器件的叠层栅极的厚度，如果对于降低的设计规则不改变离子注入条件，则可用作离子注入掩模的控制栅极多晶膜14厚度不会减小。由此，由于将被蚀刻的膜厚度不会降低，因此不可能会降低在蚀刻工艺中用作掩模的光刻胶图案16的厚度。
这种情况下，必须保持光刻胶至少为6000的厚度。然而，根据已降低的设计规则，也降低形成叠层栅极的间距，即间隔的线和临界尺寸(CD)的总值。因此，对于相同的光刻胶厚度，在曝光工艺中难以获得焦点深度(DOF)余量。
当构图叠层栅极的光刻胶时，光刻胶图案16会脱落或变形。而且，即使可以形成光刻胶图案，但是也会降低其实现性且使闪速存储器件的效率变差。
发明内容
本发明涉及闪速存储器件以及闪速存储器件的制造方法。本发明涉及通过获得曝光工艺中的焦点深度(DOF)提高了工艺的可靠性的制造闪速存储器件的方法。
本发明涉及闪速存储器件的制造方法，其通过获得曝光工艺中的焦点深度(DOF)提高了工艺的可靠性。
根据实施方式，制造闪速存储器件的方法包括在半导体衬底上顺序层叠氧化物膜、浮置栅极多晶硅膜、ONO膜、控制栅极多晶硅膜和BARC(底部抗反射涂层)，在BARC上形成用于叠层栅极的光刻胶图案，和通过使用光刻胶图案蚀刻BARC、控制栅极多晶硅膜、ONO膜和浮置栅极多晶硅膜直到暴露出氧化物膜。
附图说明
图1A至1C是示出根据相关技术具有叠层栅极结构的闪速存储器件制造方法的截面图；
图2A和2B是示出根据实施方式的闪速存储器件以及制造闪速存储器件的方法的截面图；以及
图3是根据实施方式在蚀刻叠层栅极之后的扫描电子显微镜(SEM)截面图。
具体实施方式
参考图2A，在半导体衬底100上顺序叠置氧化物膜110、浮置栅极多晶硅膜120、氧化物一氮化物一氧化物(ONO)膜130、控制栅极多晶硅膜140和底部抗反射涂层(BARC)150。为了形成叠层栅极，涂覆厚度在接近4000和5000之间的用于KrF的光刻胶。
构图用于KrF的光刻胶以形成用于KrF的光刻胶图案160。在于曝光工艺中获得焦点深度(DOF)余量之后，一起蚀刻BARC 150和叠层栅极膜，其中叠层栅极膜包括浮置栅极多晶硅膜120、ONO膜130和控制栅极多晶硅膜140。根据实施方式，蚀刻方法与相关技术蚀刻方法不同，相关技术蚀刻方法首先使用光刻胶图案16蚀刻BARC 15(如图1B中所示)，然后蚀刻浮置栅极多晶硅膜12、ONO膜13和控制栅极多晶硅膜14(如图1C中所示)。
为了使用用于KrF 160的光刻胶图案作为掩模实施蚀刻工艺，可进行蚀刻工艺直到很多共同副产物作为终点被用尽。该工艺条件包括10～30mT的大气压力、400～700W的电源和40～150W的偏置功率。蚀刻工艺可使用80～200sccm的CF4，100～200sccm的Ar以及10～20sccm的HeO2。
参考图2B，氧化物膜110可被蚀刻以暴露出。这形成了叠层栅极170，其包括浮置栅极多晶硅膜120、ONO膜130和控制栅极多晶硅膜140。
在实施方式中，在这样的条件下进行蚀刻工艺之后，剩余的光刻胶部分“A”具有接近1000的厚度。在实施方式中，以下工艺余量要求光刻胶中A厚度为约200和300。因此，厚度为1000的剩余光刻胶可确保足够的工艺余量。而且，控制栅极形状也保持为具有足够工艺余量的预定厚度。
在实施方式中，在闪速存储器件、尤其是具有130nm或更小半间距的闪速存储器件中形成控制栅极的工艺可使用原位方法(in-site method)，该方法中，BARC 150和包括浮置栅极多晶硅膜120、ONO膜130和控制栅极多晶硅膜140在内的叠层栅极膜可在单个蚀刻工艺中被一次蚀刻。因此，可形成叠层栅极170，而不需要其他工艺和装置来蚀刻BARC 150。
根据实施方式，可以前述工艺中形成叠层栅极170。由此，可以降低用作蚀刻工艺掩模的光刻胶的厚度。这获得改善DOF余量的制造条件的结果。
根据实施方式，闪速存储器件及该闪速存储器件的制造方法具有一定优点。
例如，如果使用原位方法在具有130nm或更小半间距的闪速存储器件中形成叠层栅极，则可提高制造产量并通过降低光刻胶厚度提高DOF余量。
对于本领域技术人员来说，显然可以对实施方式作出各种修改和变型。由此，上述实施方式覆盖落入附属权利要求书范围内的修改和变型。还应明白，当称为层在另一层或衬底“上”或“上方”时，其可直接形成于另一层或衬底上，或者可存在中间层。

Claims (18)

1.一种方法，包括：
在半导体衬底上方顺序层叠氧化物膜、浮置栅极多晶硅膜、氧化物-氮化物-氧化物膜、控制栅极多晶硅膜和底部抗反射涂层；
在底部抗反射涂层上方形成用于叠层栅极的光刻胶图案；和
使用光刻胶图案作为掩模在单个蚀刻工艺中蚀刻底部抗反射涂层、控制栅极多晶硅膜、氧化物-氮化物-氧化物膜和浮置栅极多晶硅膜。
2.根据权利要求1所述的方法，其特征在于，所述蚀刻工艺进行到暴露出氧化物膜。
3.根据权利要求2所述的方法，其特征在于，所述形成光刻胶图案的步骤包括：
在底部抗反射涂层上方涂覆厚度在4000和5000之间的光刻胶；和
通过构图光刻胶在用于叠层栅极的区域中形成光刻胶图案。
4.根据权利要求3所述的方法，其特征在于，光刻胶图案包括KrF的光刻胶。
5.根据权利要求2所述的方法，其特征在于，光刻胶图案包括KrF的光刻胶。
6.根据权利要求2所述的方法，其特征在于，所述蚀刻工艺是使用下述条件执行的：80～200sccm的CF4，100～200sccm的Ar以及10～20sccm的HeO2在10～30mT的大气压力、400～700W的电源和40～150W的偏置功率。
7.根据权利要求2所述的方法，其特征在于，所述蚀刻工艺是通过原位方式执行到半导体衬底上方的氧化物膜。
8.根据权利要求2所述的方法，其特征在于，还包括在形成光刻胶图案之后的曝光工艺中获得焦点深度余量，其中所述蚀刻工艺在获得焦点深度余量之后进行的。
9.根据权利要求1所述的方法，其特征在于，所述蚀刻工艺进行到耗尽大量共同副产物。
10.一种方法，包括：
在底部抗反射涂层和叠层栅极膜上方形成用于KrF图形的光刻胶，该光刻胶图案具有接近4000-5000的厚度；和
使用光刻胶图案作为掩模在单个蚀刻工艺中蚀刻底部抗反射涂层和叠层栅极膜。
11.根据权利要求10所述的方法，其特征在于，所述叠层栅极膜包括浮置栅极多晶硅膜、氧化物-氮化物-氧化物膜和控制栅极多晶硅膜，且其中底部抗反射涂层形成于叠层栅极膜上方。
12.根据权利要求11所述的方法，其特征在于，在10～30mT的大气压力、400～700W的电源和40～150W的偏置功率下，其中使用80～200sccm的CF4、100～200sccm的Ar以及10～20sccm的HeO2进行蚀刻。
13.根据权利要求12所述的方法，其特征在于，所述叠层栅极膜形成于半导体衬底的氧化层上方，且其中所述蚀刻工艺进行到直到暴露出氧化物层。
14.根据权利要求12所述的方法，其特征在于，所述蚀刻工艺进行到直到消耗掉大量共同副产物。
15.根据权利要求12所述的方法，其特征在于，在进行所述蚀刻之后，剩余光刻胶图案具有接近1000的厚度。
16.根据权利要求12所述的方法，其特征在于，还包括在形成光刻胶图案之后在曝光工艺中获得焦点深度余量，其中在获得DOF余量之后进行所述蚀刻。
17.一种器件，包括
半导体衬底；
在半导体衬底上方的氧化物层；和
在氧化物层上方的至少一叠层栅极，其中所述叠层栅极包括浮置栅极多晶硅膜、氧化物-氮化物-氧化物膜和控制栅极多晶硅膜，且其中所述至少一叠层栅极是通过使用光刻胶在单个蚀刻工艺中蚀刻叠层栅极膜和形成于叠层栅极膜上方的底部抗反射涂层而形成的。
18.根据权利要求17所述的器件，其特征在于，光刻胶包括具有接近4000-5000的厚度用于KrF的光刻胶。
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