TW584945B - Method of manufacturing flash memory - Google Patents

Abstract

A method of fabricating a flash memory device is provided. First, a substrate partitioned into a memory cell region and a peripheral circuit region is provided. A tunnel dielectric layer is formed over the memory cell region and a liner layer is formed over the peripheral circuit region. Thereafter, a patterned gate conductive layer is formed over the substrate. An inter-gate dielectric layer and a passivation layer are sequentially formed over the substrate. The passivation layer, the inter-gate dielectric layer, the gate conductive layer and the liner layer over the peripheral circuit region are removed. A gate dielectric layer is formed over the peripheral circuit region while the passivation layer over the memory cell region is converted into an oxide layer. Another conductive layer is formed over the substrate. The conductive layer, the oxide layer, the inter-gate dielectric layer and the gate conductive layer over the memory cell region are patterned to form a memory gate. The second conductive layer over the peripheral circuit region is similarly patterned to form a gate.

Description

584945 V. Description of the invention (1) The invention belongs to the technical field M. The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a flash memory (F 1 ash M em ry) device. . The prior art flash memory (F 1 ash Mem ry) element has the advantages that data can be stored, read, and erased multiple times, and the stored data will not disappear even after power is turned off. Therefore, it has become a non-volatile memory element widely used in personal computers and electronic devices. A typical flash memory device is made of doped polycrystalline silicon to make a floating gate and a control gate. Moreover, the control gate is directly arranged on the floating gate, the floating gate and the control gate are separated by a dielectric layer, and the floating gate and the substrate are penetrated by an oxide layer (T u η ne 1 ing 0 X ide) (also known as stacked gate flash memory). The flash memory device controls the injection and discharge of charges in the floating gate (F 1 0 a t i n g g a t e) by controlling the positive or negative voltage applied to the gate to achieve the memory function. Figures 1A to 1D are sectional views showing part of the manufacturing process of a conventional flash memory device. In FIGS. 1A to 1D, the substrate 100 can be divided into a cell region 102 and a peripheral circuit region 104. First, referring to FIG. 1A, a tunnel dielectric layer 106 is formed on the substrate 100 of the memory cell region 102, and a liner layer 108 is formed on the substrate 100 of the peripheral circuit region 104. Next, a conductor layer 110 is formed on the entire substrate 100, and the conductor layer 11 0 on the memory cell region 102 is patterned to form a stripe layout.

10620twf.ptd Page 6 584945 V. Description of the invention (2) Forming a conductor layer 1 1 0 a. After that, an inter-gate dielectric layer 1 12 is formed on the substrate 100. The material of the inter-gate dielectric layer 1 12 is silicon oxide / silicon nitride / silicon nitride. Next, referring to FIG. 1B, a patterned photoresist layer 1 14 is formed on the substrate 100. The patterned photoresist layer 1 4 covers the memory cell region 102 and exposes the peripheral circuit region 104. The patterned photoresist layer 114 is then used as a mask to remove the inter-gate dielectric layer 1 2, the conductor layer 1 10 and the sacrificial layer 108 from the peripheral circuit area 104. Then, a gate dielectric layer 1 16 is formed on the peripheral circuit area 104. Next, referring to FIG. 1C, the conductive layer 118 is formed on the entire substrate 100 after the patterned photoresist layer 1 1 4 is removed. Next, referring to FIG. 1D, a patterned conductor layer 11 8 is formed on the memory cell region 102 to form a control gate conductor layer 1 1 8 a, and then an inter-gate dielectric layer 1 1 2 and a conductor layer 1 are formed. 10 a and the tunneling dielectric layer 106 are formed to form a stacked gate structure formed by the control gate conductor layer 118a, the inter-gate dielectric layer 112a, the conductor layer 110b, and the tunneling dielectric layer 106a. At the same time, the conductor layer 1 1 8 on the peripheral circuit area 104 is patterned to form a gate structure composed of a gate oxide layer 1 16 a and a conductor layer 1 1 8 b. In the above process, since the inter-gate dielectric layer 1 12 is very thin and fragile, it is easy to suffer in the manufacturing process, for example, in the ashing process and cleaning process of the patterned photoresist layer 1 1 4 damage. As a result, the characteristics of the inter-gate dielectric layer 1 12 are deteriorated, and the problem of data retention characteristics of the flash memory is deteriorated. On the other hand, in order to avoid damaging the top oxide layer in the inter-gate dielectric layer 1 12, a stronger cleaning agent cannot be used in the photoresist stripping process, so that the photoresist cannot be completely removed and a polymer is generated. the remains,

10620twf.ptd Page 7 584945 V. Description of the invention (3) This leads to metal pollution and poor gate quality. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for manufacturing a flash memory, so that the gate dielectric layer is not easily damaged during the manufacturing process, and the device performance can be improved. Another object of the present invention is to provide a method for manufacturing a flash memory, which can avoid the generation of polymer residues in the manufacturing process, thereby avoiding pollution and improving the quality of the gate. The invention provides a method for manufacturing a flash memory. This method provides a substrate having a memory cell region and a peripheral circuit region, and then a tunneling dielectric layer is formed on the substrate of the memory cell region, and the substrate on the peripheral circuit region is formed. A 榇 ^ layer is formed. Next, a first conductor layer is formed on the substrate, and the first conductor layer on the memory cell region is patterned to form a gate conductor layer. Then, an inter-gate dielectric layer is formed on the substrate, and a protective layer is formed on the inter-gate dielectric layer. After that, the protective layer, the inter-gate dielectric layer, the first conductor layer, and the sacrificial layer of the peripheral circuit area are removed, and then a gate dielectric layer is formed on the substrate of the peripheral circuit area, and the protective layer of the memory cell area is transformed Is an oxide layer. After that, a second conductor layer is formed on the substrate, and then the second conductor layer, the oxide layer, the inter-gate dielectric layer, and the gate conductor layer of the memory cell region are patterned to form a plurality of memory gates, and the periphery is patterned. The second conductor layer of the circuit area forms a plurality of gates. As mentioned above, since the protective layer is formed on the inter-gate dielectric layer to cover the inter-gate dielectric layer on the memory cell region, the inter-gate dielectric layer can be prevented from being damaged during the manufacturing process, and the gate can be maintained. Characteristics of the dielectric layer. Moreover, since the present invention forms a protective layer on the inter-gate dielectric layer,

10620twf. Pt.d Page 8 584945 V. Description of the invention (4) This can use stronger chemical agents to perform the steps of photoresist removal and cleaning in the process, thus avoiding the generation of polymer residues. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below and described in detail with the accompanying drawings as follows: Embodiments: Formula, which details a method for manufacturing a flash memory according to a preferred embodiment of the present invention. In FIGS. 2A to 2F, the substrate 200 can be divided into a memory cell region 202 and a peripheral circuit region 204. First, referring to FIG. 2A, a tunneling dielectric layer 206 is formed on the substrate 200 of the memory cell region 202, and a substrate 208 is formed on the substrate 200 of the peripheral circuit region 204. The material of the tunneling oxide layer 206 and the liner layer 208 is, for example, silicon oxide, and the formation method is, for example, a thermal oxidation method. Next, a conductor layer 210 is formed on the entire substrate 200. The material of the conductor layer 2 10 is, for example, doped polycrystalline silicon. The formation method of the conductor layer 2 10 is, for example, a chemical vapor deposition method to form an undoped polycrystalline silicon layer. Then, an ion implantation step is performed to form it. Next, the conductor layer 2 10 on the memory cell area 202 is patterned to form a stripe layout to form a conductor layer 2 10 a (gate conductor layer). Thereafter, an inter-gate dielectric layer 2 1 2 is formed on the substrate 2000. The material of the inter-gate dielectric layer 2 1 2 is, for example, silicon oxide / silicon nitride / silicon nitride, and the inter-gate dielectric layer 2 1 The formation method of 2 is, for example, firstly forming a bottom silicon oxide layer 2 1 4 by a thermal oxidation method, and then using a chemical vapor deposition method to form a silicon nitride layer 2 1 6 as a charge trapping layer, and then A top silicon oxide layer 2 1 8 is formed on the silicon nitride layer 2 1 6.

10620twf.ptd Page 9 584945 V. Description of the invention (5) Next, please refer to FIG. 2B to form a protective layer on the substrate 2 0 2 2 0, wherein the material of the protective layer 2 2 0 is, for example, nitrogen Silicon is formed, and the method for forming the protective layer 220 is, for example, forming a thin layer of nitrided nitride by chemical vapor deposition. Next, referring to FIG. 2C, a patterned photoresist layer 222 is formed on the substrate 200. The patterned photoresist layer 222 covers the memory cell region 202 and exposes the peripheral circuit region 204. Then, using the patterned photoresist layer 222 as a mask, the protective layer 220, the inter-gate dielectric layer 212, the conductor layer 210, and the hafnium layer 208 on the peripheral circuit area 204 are removed. Next, referring to FIG. 2D, remove the patterned photoresist layer 2 2 2 and perform a cleaning process on the substrate 2 0 as necessary, and then form a gate 4 pole dielectric layer 2 2 4 in the peripheral circuit area 2 4 , And make the protective layer 2 2 0 of the memory cell array area 2 2 into an oxide layer 2 2 6. Among them, a method of forming the gate dielectric layer 2 2 4 and converting the protective layer 2 2 0 to the oxide layer 2 2 6 is, for example, a thermal oxidation method. In the above steps of removing the patterned photoresist layer 2 2 2 or cleaning, since a protective layer 2 2 0 is formed on the inter-gate dielectric layer 2 1 2, a stronger chemical agent (such as hydrogen) can be used. Fluoric acid or SC-1 cleaning solution (also known as APM, ammonia-hydrogen peroxide mixed solution) for removing the photoresist layer 2 2 0 and cleaning the substrate 2 0 0, without affecting the gate dielectric layer 2 1 2 causes damage, and the purpose of completely removing the photoresist layer 2 2 2 can be achieved. Next, referring to FIG. 2E, a conductive layer 2 2 8 is formed on the substrate 2000. The material of the conductive layer 2 2 8 is, for example, doped polycrystalline silicon. The method for forming the conductive layer 2 2 8 is, for example, chemical gas. After an undoped polycrystalline silicon layer is formed by the phase deposition method, an ion implantation step is performed to form it.

10620t.wf.ptd Page 10 584945 V. Description of the invention (6) Next, please refer to Figure 2 F, pattern the conductor layer 2 2 8 to form the control. Gate conductor layer 2 2 8 a, then pattern the gate Dielectric layer 2 1 2, conductor layer 2 1 0 a and tunneling dielectric layer 2 0 6 to form a controlled gate conductor layer 2 2 8 a, inter-gate dielectric layer 2 1 2 a, and conductor layer 2 1 A stacked gate structure (that is, a memory gate) formed by stacking 0 b and the tunneling dielectric layer 2 0 6 a. At the same time, the conductor layer 228 on the peripheral circuit region 204 is patterned to form a gate structure 2 3 2 formed by stacking the gate oxide layer 224a and the conductor layer 2 2 8 b. The subsequent process of completing the flash memory is well known to those skilled in the art and will not be repeated here. According to the above embodiment, after the inter-gate dielectric layer 2 1 2 is formed in the present invention, a protective layer 2 2 0 is formed on the inter-gate dielectric layer 2 12 to cover the inter-gate dielectric on the memory cell area. Layer 2 1 2, so the gate dielectric layer 2 1 2 can be prevented from being damaged during the manufacturing process, and the characteristics of the gate dielectric layer 2 1 2 can be maintained. In addition, since the present invention is to form a protective layer 2 2 0 on the inter-gate dielectric layer 2 1 2, a stronger chemical agent can be used to perform the photoresist removal and cleaning steps, and the photoresist layer 2 2 2 can be further processed. Completely removed to avoid polymer residues. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various changes and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. ^

10620twf.ptd Page 11 584945 Brief Description of Drawings Figures 1A to 1D show the manufacturing of a conventional flash memory. Method flow sectional view. FIG. 2A to FIG. 2F are cross-sectional views illustrating a method for manufacturing a flash memory according to a preferred embodiment of the present invention. Description of icons: 100, 2 0 0: substrate 1 0 2, 2 0 2: memory cell area 104, 204: peripheral circuit area 106, 206: tunnel dielectric layer 1 0, 2 0 8: liner 110 , 110a, 110b, 118, 118b, 210, 210a, 210b, Ιβ 228, 228b · Conductor layer 1 1 2, 2 1 2: Inter-gate dielectric layer 114, 222: Patterned photoresist layer 1 1 6, 2 2 4: Gate dielectric layer 1 1 8 a, 2 2 8 a: Control gate conductor layer 2 1 4 ·· Bottom oxide layer 2 1 6: Silicon nitride layer 2 1 8: Top oxide layer 2 2 0: Protective layer 2 2 6: oxide layer

10620twf.ptd Page 12

Claims (1)

584945 VI. Patent application scope A flash memory manufacturing method, the method includes the following steps: providing the peripheral circuit to the patterned conductor layer; removing a conductor layer from the memory cell area at the pattern gate; Dielectric patterning the 2. As the law, of which 3. As the law, of which 4. · As the law, the substrate with a memory cell region is on the substrate, the recording medium on the substrate and the periphery of the gate are electrically connected to the substrate. To ensure that the recording layer and the peripheral electrical application are applied to the gate application, the gate application is applied to the memory cell area and a peripheral circuit area; a tunnel dielectric layer is formed on the substrate on the area, And forming a first layer on the substrate; forming a first conductor layer; forming the first conductor layer on the memory cell area to form a gate to form a gate dielectric layer; forming a protective layer on the electrical layer; a circuit The protective layer, the inter-gate dielectric layer, and the first layer; the substrate forms a gate dielectric layer into an oxide layer; forms a second conductor layer; and the second conductor layer in the memory cell area The Of the layer, the gate conductor layer to form a plurality of memory gate, the second conductive layer and the channel region to form a plurality of gates. The manufacturing method of the flash memory described in the first item of the scope of interest is that the dielectric layer includes a silicon oxide / silicon nitride / silicon oxide layer. The manufacturing method of the flash memory described in Item 1 of the scope of interest The material of the conductive layer includes polycrystalline silicon. The material of the manufacturing method of the flash memory described in item 1 of the scope of interest includes nitride nitride. And change the cover of the road area 10620twf.ptd Page 13 584945 6. Scope of Patent Application 5 · If applied, the method of oxidizing the memory cells. 6 · As claimed, in which the manufacturer of the flash memory described in item 1 of the patent scope, the base of the peripheral circuit area forms the gate dielectric layer, and the protective layer of the area is converted into the oxide The method of the layer includes heat. 7. The material of the second conductive layer of the flash memory manufacturer described in item 1 of the patent scope includes polycrystalline silicon. A method for manufacturing a flash memory, the method includes the following steps: providing a patterned conductor layer having a peripheral circuit area on the base; and removing the capture layer on the top and the top based on the bottom and the top. A pattern of a memory cell region and a peripheral circuit region is patterned on the base of the peripheral memory cell region; a tunneling dielectric layer is formed on the substrate of the memory cell region, and a chirped layer is formed on the substrate. A first conductor layer is formed on the bottom; the first conductor layer on the memory cell region is formed to form a bottom oxide layer on the gate bottom; a charge trap layer is formed on the oxide layer; a charge trap layer is formed on the A top oxide layer; a protective layer is formed on the oxide layer; the protective layer, the top oxide layer, the charge bottom oxide layer, the first conductor layer and the plutonium layer of the peripheral circuit area; the base of the side circuit area forms a gate A dielectric layer, and the protective layer is transformed into an oxide layer; a second conductor layer is formed on the bottom; and the second conductor layer, the oxide layer, the 10620twf.ptd Page 14 584945 VI. Patent application scope The top oxide layer, the charge trap layer, the bottom oxide layer and the gate conductor layer form a plurality of memory gates, and pattern the peripheral circuit area. A second conductor layer to form a plurality of gates. 8. The method for manufacturing a flash memory as described in item 7 of the scope of the patent application, wherein the material of the charge trapping layer includes nitride. 9. The method for manufacturing a flash memory as described in item 7 of the scope of patent application, wherein the material of the gate conductor layer includes polycrystalline silicon. 10. The method for manufacturing a flash memory as described in item 7 of the scope of patent application, wherein the material of the protective layer includes silicon nitride. 1 1 · The flash memory manufacturing method as described in item 7 of the scope of patent application, wherein the gate dielectric layer is formed on the base of the peripheral circuit area, and 0 changes the protection layer of the memory cell area The method for the oxide layer includes a thermal oxidation method. 12. The method for manufacturing a flash memory as described in item 7 of the scope of patent application, wherein the material of the second conductor layer includes polycrystalline silicon. 10620t.wf. Ptd Page 15