1270182 14736twf/y 九、發明說明： 【發明所屬之技術領域】 本發明是有關-種非揮發性記憶體及其 =是有關於-種可改善元件電性特性及提高可 的非揮發性記憶體及其製造方法。 罪又 【先前技術】 目前非揮發性記憶體中常見的是—_為「1270182 14736twf/y IX. Description of the Invention: [Technical Field] The present invention relates to a non-volatile memory and a non-volatile memory thereof which can improve the electrical characteristics of an element and improve the usability. And its manufacturing method. Sin again [Prior Art] Currently common in non-volatile memory is -_"
體」的可電抹除可程式唯讀記##〇 * 貝口C 體（Electricaliy Erasable rogrammable Read Only Memory，EEPR〇M)，复且 行多次資料之存人、讀取、抹除等動作，且存;^資料在 斷電後也不會消失之優點’所以已成為個人電腦和電子設 備所廣泛採用的一種記憶體元件。 典型的快閃記憶體係以摻雜的摻雜多晶矽作為浮置閘 極(Floating Gate)與控制閘極(c〇咖丨仏⑹。當記憶體進行 寫入程式(Program)時，注入浮置閘極的電子會均勻分布於 整個摻雜多晶料置閘極層之中。錢，當雜多晶石夕浮 置閘極層下方的穿隨氧化層有缺陷存在時，就容易造成元 件的漏電流，影響元件的可靠度。 因此’為了解決快閃記憶體漏電流之問題，目前改採 一種用電荷陷入層取代摻雜多晶矽浮置閘極的非揮發性記 ί*思體’其係稱為「石夕_氧化物_氮化物_氧化物_半導體 (silicon-oxide_nitride，oxide-semiconductor，SONOS)」記慎 體。因為石夕-氧化物-氮化物-氧化物-半導體記憶體具有一氧 化物-氮化物-氧化物(oxide-nitride-oxide，簡稱ΟΝΟ)介電 1270182 14736twf/y 結構’其中氣化物層係作為電荷陷入層（electr〇de trapping layer)使用。一般可藉由氧化物-氮化物-氧化物介電結構之 底氧化層的通道熱電子(channel hot electron，簡稱CHE)注 入而被寫入。另方面，藉由氧化物-It化物-氧化物介電 結構之底氧化層約牙隧加強熱電洞(tunneiing enhanced hot hole，簡稱TEHH)注入而被抹除。所以，氧化物氮化物_ 氧化物-半導體記憶體能克服漏電流的問題。但是，隨著元 件尺寸不斷縮小，上述矽-氧化物-氮化物—氧化物-半導體記 憶體中的電荷陷入層内容易發生電荷遷移失誤的問題。 因此，近來出現一種電荷陷入發生在閘極兩側的氧化 物-氮化物-氧化物介電結構(如圖丨所示）中，有效解決了這 個問題。 請參照圖1，其係繪示習知一種非揮發性記憶體的剖 面圖。此石夕氧化物-氮化物_氧化物·半導體(s〇N〇s)非揮發 性圮憶體的字元線120係形成在基底1〇〇上的閘氧化層 110上，而控制閘170係形成在字元線12〇的側壁上，其 形狀呈間隙壁狀。字元線120與控制閘17〇之間以及控制 閘170與基底100之間則以底介電層14〇、電荷陷入層15〇 與頂介電層160所形成的氧化物_氮化物_氧化物(〇N〇)結 構相隔開；而源極180與汲極19〇則形成於字元線12〇兩 側之控制閘極間隙壁170外的基底100中。。 此種元件在進行程式化時，由於電荷是陷入於字元線 120兩側的電荷陷入層15〇中，因此可以避免因元件縮小 造成之電荷遷移問題。然而，當電荷陷入於矽-氧化物_氮 6 1270182 14736twf/y 物·半導體_發性記憶體中字⑽侧壁的氧化 構時，因為此處的電荷不易移二 何累積的、、、。果將產生轉可靠度的問題。 弧二::二t於控制閘極呈間隙壁狀，其表面為-圓 扣、’ ^ ，在後續形成接觸窗的製程中，在接觸 由與控^閘極間隙壁之_電性連接並不容易進行。 此外’在形成控制閘極間隙壁時，於回钱 會對氧化物-氮化物·氧化物(ΟΝΟ)結構造成破壞，後 元線與控制閘極間隙壁上艰士 、、、、；子 造成短路。H场成魏金屬⑼脇e)時，容易 【發明内容】 本U的目4就是在提供重 升記憶體元件的可靠度。 ’叫 目的疋提供—種非揮發性記憶體的製 k方法，以改善記憶體元件的電性。 =明，出-種非揮發性記憶體的製造方法，首先提 由下基底上形成多數個堆疊結構’各堆疊結構 由下而上⑽為底介電層、電荷陷 閘層及頂蓋層。接著，在埯晶，士棋—7 电層控制 階辟/Γ 構之側壁上形成多數個間 堆ί心之Η 乂 Ϊ上形成閘介電層。之後’在相鄰兩個 日/成字7^線。再來，移除各堆疊結構中的頂 f層。^、’在各字元線兩側之各堆疊結構外的基底中形 成源極區及及極區。 一 7 1270182 14736twf/y 伙脫不赞明的丨 憶體的製造方法中形成間二非揮發性記 間隙壁材料層並覆蓋堆疊結構^ ’係先在基底上形成 層，以在堆疊結構之側壁上形成^壁回餘刻間隙壁材料 依照本發明的一較佳實 憶體的製造方法中形成閘介電層的方^处之非揮發性記 依照本發明的一較佳:述二=法。 方法’首先在基底上形成導體層，子元線的 相鄰兩個堆疊結構之間 覆现堆豐蛣構並填滿 :暴露出各堆叠結構中的;;層。：後移:體層， 的頂蓋層裸構：;二^ 層幕和除各恤射的_。再來，移== 億趙轉發性記 的頂蓋層的方味等體層以暴路出各堆疊結構_ 止層進行-化學频 結射_蓋層為研磨終 憶體’上述之非揮發性記 的頂蓋層Sit 層以暴露出各堆疊結構中 止層進行—回韻刻;ΐ以各堆疊結構中的頂蓋層為敍刻終 依照本發明的-較佳實施例所述，上述之非揮發性記 8 Ϊ270182 14736twf/y =的製造方法中移除各堆疊結 濕式蝕刻法。 只现層的方法包括 二：一較佳實施例所述，上述之非揮㈣己 ^的衣U方法中形成源極區及汲極區的方法包括離子植己 本發明提出-種非揮發性記憶體，包括 d豐結構、多數個字元線、多數個間隙壁、—;介ς 夕數個源極區與多數個汲極區。其中，多 ^丨，層、 酉，基底上，各堆疊結構包括底介電層、電荷二籌係 二c制閘極。在各堆疊結構中，“:置 上、電荷陷人層配置於底氧化層上、頂介電二己ΐ 、電何陷人層上’而控制閘極係配置於魏化 曰 ;= 爾配置於堆疊結構及所對應的各; =線之間。閘介電層配置字元線與基底之間。多 二 外的基底中。 置於各子讀兩側之各堆疊結構 依照本發明的一較佳實施例 憶體中控制間極包括具有一平坦上表面^之非揮發性記 有氧2本發日狀非料性記憶財字元_壁上並沒 H氮终氧化料構，不會有習知之參氧化物- i字-導體非揮發性記憶體結構中，電荷陷入 此，ΐ接二壁之氧化物·氮化物氧化物結構的問題，因 了提升圮憶體元件的可靠度。 9 1270182 I4736twf/y ^者’本發明之非揮發性記憶體的控制閘極具有 ’在後續形成接觸窗的製程中，控制閘極與 囱月b更易於進行電性連接。 觸 、、士 f a方面’依照本發明之非揮發性記憶體的製造方 / - ’字7L線與控制間極之間形成之間隙壁可有效進行 f ’於後續形成魏金屬的製程中較不易發生短路現 象’可有效改善電性特性。 見 為讓本發明之上述和其他目的、特徵和優點能更 ，下文特舉較佳實施例，並配合所附圖式，作詳細說 明如下。 ϋ 【實施方式】 >圖2Α〜圖2C係緣示本發明一較佳實施例之非揮發性 記憶體的製造流程剖面圖。請參關2A，提供—半導體基 底j〇〇,並在基底200上形成多數個堆疊結構212。其中， 堆=構212中的各膜層由下而上依序為底介電層214、 電何陷入層216、頂介電層218、控制閘極22G及頂蓋層 2^10/。上述堆疊結構212的形成方法例如是在基底2〇〇上依 次形成底介電層214、電荷陷入材料層216、頂介電材料層 218/控制閘極2〇8與頂蓋層21〇，再對各膜層進行一圖案 化製程而得之，至於形成上述堆疊結構的詳細方法、材料 與相關的#作係數為熟知此技藝者所周知，於此不在贅述。 然後，請繼續參照圖2A，在每一堆疊結構212之側 壁上形成多數個間隙壁222，其材質例如是氮化矽或氧 1270182 14736twf/y 此外，間隙壁222形成的方法例如是先在半 上形成間隙壁材料層(未繪示)並覆蓋堆疊結構 二壁材料層’以在堆疊、纟⑽2之側壁上形 接下來，請參照圖2B，在轉體基底2 f電層224，其材質例如是氧切，形成方法例如是t"Electricaliy Erasable rogrammable Read Only Memory (EEPR〇M)", which can be used to save, read, erase, etc. And the advantages of the data; ^ data will not disappear after power off' has become a memory component widely used in personal computers and electronic devices. A typical flash memory system uses doped doped polysilicon as a floating gate and a control gate (c). When the memory is programmed, the floating gate is injected. The electrons of the poles are evenly distributed in the gate layer of the doped polycrystalline material. When the porous oxide layer below the floating gate layer is defective, it is easy to cause leakage of components. The current affects the reliability of the component. Therefore, in order to solve the problem of leakage current of the flash memory, a non-volatile recording method using a charge trapping layer instead of a doped polysilicon floating gate is proposed. For the "silicon-oxide_nitride-oxide-semiconductor (SONOS)", it is considered to be oxidized because the Shixi-oxide-nitride-oxide-semiconductor memory has oxidation. -oxide-nitride-oxide (abbreviated as ΟΝΟ) dielectric 1270182 14736 twf / y structure 'where the vapor layer is used as a charge trapping layer (electr〇 de trapping layer). Generally by oxide - Nitride-oxide dielectric The channel hot electron (CHE) of the underlying oxide layer is implanted and written. On the other hand, the thermal oxide layer is reinforced by the bottom oxide layer of the oxide-I-oxide-oxide dielectric structure. The tunneiing enhanced hot hole (TEHH) is implanted and erased. Therefore, the oxide nitride _ oxide-semiconductor memory can overcome the problem of leakage current. However, as the component size shrinks, the above bismuth-oxide-nitride - The charge trapping in the oxide-semiconductor memory is prone to the problem of charge migration errors. Therefore, a recent charge-trapping oxide-nitride-oxide dielectric structure occurs on both sides of the gate (see Figure 丨). In the case shown, this problem is effectively solved. Referring to Figure 1, there is shown a cross-sectional view of a conventional non-volatile memory. This is an oxide-nitride oxide/semiconductor (s〇N〇). s) The word line 120 of the non-volatile memory is formed on the gate oxide layer 110 on the substrate 1 , and the control gate 170 is formed on the sidewall of the word line 12 , and has a shape of a gap wall. Word line 120 Between the control gates 17A and between the control gates 170 and the substrate 100, an oxide-nitride oxide is formed by the bottom dielectric layer 14, the charge trapping layer 15 and the top dielectric layer 160. The structures are spaced apart; and the source 180 and the drain 19 are formed in the substrate 100 outside the control gate spacer 170 on both sides of the word line 12A. When such an element is programmed, the charge is The charge trapped on both sides of the word line 120 is trapped in the layer 15A, so that the problem of charge migration due to the reduction of the element can be avoided. However, when the charge is trapped in the oxidation structure of the side wall of the word (10) in the 矽-oxide_nitrogen 6 1270182 14736 twf/y semiconductor, the charge here is not easily absorbed. If there is a problem with the reliability of the turn. Arc 2:: 2 t is in the control gate with a gap wall shape, the surface of which is - round buckle, ' ^, in the subsequent process of forming the contact window, the contact is electrically connected with the control gate gap Not easy to carry out. In addition, when forming the control gate spacer, the return of the money will cause damage to the oxide-nitride-oxide structure, and the rear-line and the control gate are hard, and Short circuit. When the H field is a Wei metal (9) threat e), it is easy [Explanation] The purpose of this U is to provide reliability for the memory element. The purpose of providing a non-volatile memory method to improve the electrical properties of memory components. = Ming, a non-volatile memory manufacturing method, firstly, a plurality of stacked structures are formed on the lower substrate. The stacked structures are bottom-up (10) as a bottom dielectric layer, a charge trap layer and a cap layer. Then, on the sidewalls of the crystals, the layers of the gates and the layers of the gates are formed into a plurality of layers. After 'on the next two days / word 7^ line. Again, the top f layer in each stacked structure is removed. ^, 'The source region and the polar region are formed in the substrate outside the stacked structures on both sides of each word line. A 7 1270182 14736 twf / y 脱 不 不 不 的 的 的 的 的 的 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成Forming a wall-returning residual spacer material in accordance with a preferred embodiment of the present invention in the method of fabricating a gate dielectric layer in accordance with a preferred embodiment of the present invention: . The method 'firstly forms a conductor layer on the substrate, and the adjacent two stacked structures of the sub-line are overlapped and filled: exposing each layer; : Backward movement: The body layer, the top cover layer bare structure:; 2 ^ layer curtain and _. Then, the body layer of the top cover layer of the shift == billion Zhao forwards is violently discharged from each stack structure _ the stop layer is carried out - the chemical frequency junction _ the cover layer is the grinding final memory body 'the above non-volatile The top layer of the cap layer Sit layer is exposed to expose the stop layer of each stack structure, and the top cover layer in each stack structure is described as a final embodiment according to the preferred embodiment of the present invention. The method of manufacturing the volatiles 8 Ϊ 270182 14736 twf / y = remove each of the stacked junction wet etching methods. The method of forming only the layer includes: in a preferred embodiment, the method for forming the source region and the drain region in the non-volatile (four) method of the coating U includes ion implantation. The memory includes a d-rich structure, a plurality of word lines, a plurality of spacers, and a plurality of source regions and a plurality of bungee regions. Among them, multiple stacks, layers, germanium, and substrates, each stack structure includes a bottom dielectric layer, a charge quadratic system, and a c-gate. In each stack structure, ": set, the charge trapping layer is disposed on the bottom oxide layer, the top dielectric is dipyrene, and the electricity is trapped on the human layer" and the control gate is disposed in Weihuayu; Between the stack structure and the corresponding; = line. The gate dielectric layer is disposed between the word line and the substrate. In the outer substrate, each stacked structure placed on both sides of each sub-read is in accordance with the present invention. In the preferred embodiment, the control inter-electrode includes a non-volatile aerobic 2 having a flat upper surface, and the surface is not H-nitrogen oxidized material. In the conventional reference oxide-i-conductor non-volatile memory structure, the charge is trapped in this, and the problem of the oxide-nitride oxide structure of the two walls is spliced, because the reliability of the memory element is improved. 9 1270182 I4736twf / y ^ 'The control gate of the non-volatile memory of the present invention has 'in the subsequent process of forming a contact window, the control gate is more easily electrically connected with the chimney b. Touch, shi fa Aspect 'Manufacturer of non-volatile memory according to the present invention / - 'Word 7L line and control The spacer formed between the interpoles can effectively perform the short-circuit phenomenon in which the f' is less likely to be formed in the subsequent formation of the Wei metal. The electrical characteristics can be effectively improved. See the above and other objects, features and advantages of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the preferred embodiments are described in detail below with reference to the accompanying drawings. [Embodiment] > Figures 2A to 2C show the non-volatile memory of a preferred embodiment of the present invention. A cross-section of the fabrication process. Referring to FIG. 2A, a semiconductor substrate is provided, and a plurality of stacked structures 212 are formed on the substrate 200. The layers in the stack = 212 are sequentially from bottom to top. The electrical layer 214, the electrical trapping layer 216, the top dielectric layer 218, the control gate 22G, and the cap layer 210/10. The stacking structure 212 is formed by, for example, sequentially forming a bottom dielectric layer on the substrate 2〇〇. 214, the charge trapping material layer 216, the top dielectric material layer 218 / the control gate 2 〇 8 and the cap layer 21 〇, and then a patterning process for each film layer, as a detailed method of forming the above stacked structure , materials and related #作系数 are familiar with this As is well known to the art, it will not be described here. Then, referring to FIG. 2A, a plurality of spacers 222 are formed on the sidewalls of each stacked structure 212, such as tantalum nitride or oxygen 1270182 14736 twf/y. The method of forming the wall 222 is, for example, first forming a layer of a spacer material (not shown) on the half and covering the layer of the two-wall material of the stacked structure to form on the sidewalls of the stack and the raft (10) 2, please refer to FIG. 2B. Body substrate 2 f electrical layer 224, the material of which is, for example, oxygen cutting, the forming method is, for example, t
Hi之後’在半導體基底2。。上形成導體層226，覆ΐ 隹宜結構212亚填滿相鄰兩個堆疊結構2ΐ2 〜 f :導體層226的材質例如是摻雜多晶矽，形：的；：。 如疋化學氣相沉積法。接著，移除 =方法例 露出各堆疊結構212中的頂蓋層21〇，其方法曰:/暴 堆$結構212中的頂蓋層21〇為 =各 械研磨製程。在另-較佳~㈣:止層進仃—化學機 以暴露出各堆疊_12中_蓋體層226， ST疊結ί 212中的頂蓋層210為親終止層進:如是 製f。其後’在基底上形成圖案化之光阻;ΪΓ: 盘於兩個堆疊結構212之間的導_细^ ^如’覆 的頂蓋層210裸露出來。 上，至>、使部分 層210 ^未』’移除各堆叠結構212中的頂蓋 自228所覆蓋的導體声二風 =阻層228為單幕，進行一濕式钱刻“ ^叠結構212之間形成字元線23〇。‘，’；^^兩個 構212的方法。 ”甲，移除各堆疊結 繼之，請繼續參照圖2C，移除光阻層228。。接著， 1270182 14736twf/y Γ兩側之各堆疊結構212夕卜的半導體基底 是離子=區232及-没極區234 ’其形成的方法例如 盘字非揮發性半導體的方法中，在控制閘極220 Γ Π t間所形成的間隙壁222具有較佳的品質， 來於物形成魏金屬（錢示)的製㈣，較不易 ㈣=路的現象。因此，可有效提升非揮發性記憶體的電 ^續完成非揮發性記憶體的製程為周知的製程 +丹賢述。 ^ 配合圖3說明利用上述方法所得之非揮發性記 1 Λ 3 ’此非揮發性記憶體包括半導體基底 330、结構312、間隙壁322、閘介電層324、字元線 係配置、於丰汲極區334。其中，多數個堆疊結構312 mi 底300上，各堆疊結構312包括底介電 S …何陷入層316、頂介電層318與控制閉極32〇。 承上述，底介電層314配置於半導體基底3㈨上，豆 ^例如是非導體材料’如氧化石夕。電荷陷入層316配置 化層314上，其材質例如是非導體材料，如氮化石夕。 S3 318配置㈣荷陷入層316上’其材質例如是非 ^ 如氧化矽。控制閘極320配置於頂氧化層318 二：上ί面例如是一平坦之上表面’而其材質例如是導 體材枓，如摻雜多晶矽。 而且，字元線330配置於半導體基底3〇〇上且係位於 1270182 14736twf/y 相鄰兩個堆叠結構312之間，其材質例如是推雜多晶石夕。 而夕數個間隙壁322配置於堆疊結構312及所對應的各字 儿線330之間，其材質例如是非導體材料，如氮化石夕或氧 ^石夕^介電層324配置字猶33G與半導體基底300之 間、材質例如是氧化石夕。源極區332與沒極區334分別 3〇=。子兀、線330兩側之各堆疊結構312外的半導體基底 ^發明贿丨之非揮舰半導體元件巾，目為在字元 線0側壁上並沒有氧化矽-氮化矽-氧化矽結構，不合蛴 二字ί線側壁之氧化物-氮化物_氧化物結“ 了長1升6己板、體元件的可靠产。萁一 士二, 非揮發性記憶體的控制閘極3心有平;;3面本 •為長方艘，在後續形成接觸窗的 更谷易與接觸窗（未繪示）電性連接。 。 綜上所述，本發明至少具有下列優點： 1. 本發明之非揮發性記憶體可解決 存於字元線側壁之氧化石夕-氮化 =電何儲 提高記憶體元件的可靠度。 乳化矽、、、。構的問題，可 2. 本發明之非揮發性記憶體之控 平坦的上表面，使後續控制閘極與接觸】電::是具有一 更容易進行。 f自電性連接的製程 3. 依照本發明之非揮紐記憶體的 — 線與控制閘極間之間隙壁具有較佳 二法，在字兀 續形成石夕化金屬的製程中不易發此—來於後 岭的現象，能改善記 13 1270182 14736twf/y k、體元件的電性特性。 限定St發圭實施例揭露如上，然其並非用以 和範圍内，去可二二、自此技蟄者，在不脫離本發明之精神 繼視後:之4:==者=本發明之保護 【圖式簡單說明】 Θ係、、、曰示㊂知一種非揮發性記憶體的剖面圖。 圖2Α〜圖2C係繪示本發明一較佳實施例之非 s己i思體的製造流程剖面圖。 圖3係繪示本發明一較佳實施例之非揮發性記憶體的 剖面圖。 【主要元件符號說明】 100、200、300 :半導體基底 110、224、324 :閘氧化層 • 120、230、330 ··字元線 140、214、314 ··底介電層 150、216、316 :電荷陷入層 160、218、318 :頂介電層 170 ··控制閘極間隙壁 180、232、332 :源極區 190、234、334 :汲極區 210 :頂蓋層 14 1270182 14736twf/y 212、312 :堆疊結構 220、320 :控制閘極 222、322 :間隙壁 226 :導體層 228 :光阻層Hi after 'on the semiconductor substrate 2. . The conductor layer 226 is formed thereon, and the cover structure 212 is filled with the adjacent two stacked structures 2ΐ2 to f: the material of the conductor layer 226 is, for example, doped polysilicon, shaped::. Such as bismuth chemical vapor deposition. Next, the method of removing = method exposes the cap layer 21 of each of the stacked structures 212 by the method of 曰: / the top layer 21 of the structure 212 is = mechanical polishing process. In the other - preferably ~ (d): stop layer - chemical machine to expose each stack _12 _ cover layer 226, ST stack ί 212 of the cap layer 210 is pro-terminating layer: if f. Thereafter, a patterned photoresist is formed on the substrate; ΪΓ: a thin-film cap layer 210 between the two stacked structures 212 is exposed. Up, to >, the partial layer 210 is not removed. The top cover in each stack structure 212 is removed from the conductor covered by the 228, and the resistance layer 228 is a single screen, and a wet money engraving is performed. A structure of the word lines 23A is formed between the structures 212. ', '; ^^ Two structures 212. "A, remove each stack and continue, please continue to refer to Figure 2C, remove the photoresist layer 228. . Next, 1270182 14736 twf / y Γ 之 各 的 的 的 的 的 的 的 半导体 离子 离子 离子 离子 离子 离子 离子 离子 离子 离子 离子 离子 离子 离子 离子 离子 离子 离子 离子 离子 离子 离子 离子 离子 离子 离子 离子 离子 离子 离子 离子 离子 离子 离子The spacer 222 formed between 220 Γ Π t has a better quality, and the formation of the Wei metal (Qian) system is relatively difficult (four) = road phenomenon. Therefore, the process of continuously completing the non-volatile memory of the non-volatile memory can be effectively improved by the well-known process + Dan Xianshu. ^ The non-volatile memory obtained by the above method is described with reference to FIG. 3. The non-volatile memory includes a semiconductor substrate 330, a structure 312, a spacer 322, a gate dielectric layer 324, a word line configuration, and Yufeng. Bungee area 334. Wherein, a plurality of stacked structures 312 mi bottom 300, each stacked structure 312 includes a bottom dielectric S, a trapped layer 316, a top dielectric layer 318 and a controlled closed end 32〇. In the above, the bottom dielectric layer 314 is disposed on the semiconductor substrate 3 (9), and the beans are, for example, non-conductive materials such as oxidized stone. The charge trapping layer 316 is disposed on the layer 314 and is made of, for example, a non-conducting material such as nitride. The S3 318 configuration (4) is charged on the layer 316. The material thereof is, for example, non-such as yttrium oxide. The control gate 320 is disposed on the top oxide layer 318. The upper surface is, for example, a flat upper surface, and the material thereof is, for example, a conductor material such as a doped polysilicon. Moreover, the word line 330 is disposed on the semiconductor substrate 3A and is located between the adjacent two stacked structures 312 of 1270182 14736 twf/y, and the material thereof is, for example, a doped polycrystalline stone. The plurality of spacers 322 are disposed between the stacked structure 312 and the corresponding word lines 330, and the material thereof is, for example, a non-conductor material, such as a nitride nitride or an oxygen oxide layer 324. The material between the semiconductor substrates 300 is, for example, oxidized stone. The source region 332 and the gate region 334 are respectively 3〇=. The semiconductor substrate outside the stack structure 312 on both sides of the sub-trailer and the line 330 is invented to be a non-Wheeling semiconductor component towel, which has no yttria-yttria-yttria structure on the sidewall of the word line 0.不 蛴 ί ί 氧化物 氧化物 氧化物 氧化物 氧化物 氧化物 氧化物 氧化物 ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ;; 3 face book • is a rectangular ship, in the subsequent formation of the contact window, more valleys are electrically connected with a contact window (not shown). In summary, the present invention has at least the following advantages: 1. The present invention The non-volatile memory can solve the problem of the reliability of the memory element by the oxidation of the oxidized stone deposited on the sidewall of the word line. The problem of the emulsification of yttrium, y, and y. Control of the flat upper surface of the memory, so that the subsequent control gate and contact] electricity:: is easier to carry out. f self-electrical connection process 3. non-core memory according to the present invention - line and The gap between the control gates has a better two method, and the formation of the stone It is not easy to send this in the process - the phenomenon of coming to the back ridge can improve the electrical characteristics of the body components of 13 1270182 14736 twf / yk. The definition of the St. Philippine embodiment is as disclosed above, but it is not used and scoped. Second, since this technology, without departing from the spirit of the present invention: 4: = = = the protection of the present invention [simple description of the schema] Θ,,, 曰, three senses, a non-volatile memory Figure 2A to Figure 2C are cross-sectional views showing a manufacturing process of a preferred embodiment of the present invention. Figure 3 is a diagram showing a non-volatile memory of a preferred embodiment of the present invention. Cross-sectional view of the body. [Main component symbol description] 100, 200, 300: semiconductor substrate 110, 224, 324: gate oxide layer • 120, 230, 330 · word line 140, 214, 314 · · bottom dielectric layer 150, 216, 316: charge trapping layer 160, 218, 318: top dielectric layer 170 · control gate spacers 180, 232, 332: source regions 190, 234, 334: drain region 210: cap layer 14 1270182 14736twf/y 212, 312: stack structure 220, 320: control gate 222, 322: spacer 226: conductor layer 228: light Floor
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