CN101136005A - Terminal chip pin multiplexing device - Google Patents
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- CN101136005A CN101136005A CNA2007101615836A CN200710161583A CN101136005A CN 101136005 A CN101136005 A CN 101136005A CN A2007101615836 A CNA2007101615836 A CN A2007101615836A CN 200710161583 A CN200710161583 A CN 200710161583A CN 101136005 A CN101136005 A CN 101136005A
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Abstract
The method comprises: a multiplexing control module used for controlling the switching between the functional module and general I/O interface module, and controlling the signal direction of the functional module and general I/O interface module; and a general I/O interface module used for controlling the signal direction of the I/O interface module and outputting CPU configuration level to multiplex pins, and reading the signal of the multiplex pin. Wherein, each multiplexing control combination logic module corresponds to a multiplexing pin.
Description
Technical field
The present invention relates to terminal SOC (SOC (system on a chip)) chip or cellphone multimedia chip design, relate in particular to a kind of pin multiplexing device of ultra-large chip.
Background technology
Along with developing rapidly of microelectronics and mechanics of communication, the integrated scale of chip is increasing.Terminal SOC (SOC (system on a chip)) chip is exactly a typical example.Early stage terminal chip may need a plurality of chips to finish corresponding function, and a present terminal SOC chip integrated the base band all functions, but also have abundant multimedia and application function.These terminal chips comprise mobile phone base band chip, mobile phone application processor, terminal multi-media processor and multimedia player SOC chip etc.
Along with increasing rapidly of application demand, the terminal chip integrated functionality is more and more abundanter, as supports multiple type of memory, support various communication interfaces, multiple multimedia function, multiple outside linkage function or the like.The increase of terminal SOC chip functions must increase chip and draw pin, to connect concrete application function.Shown in figure one is a typical mobile phone SOC chip functions block diagram.Its pin that need draw comprises following a few class:
(1), memory bus interface, comprise DDR SDRAM, FLASH etc.
(2), the application function interface, as baseband interface, WLAN interface and blue tooth interface etc.
(3), the external communication connecting interface, as various serial ports (UART, SPI, I2C, USB, SD/MMC etc.).
(4), multimedia interface, as LCD interface, utilizing camera interface and audio interface etc.
(5), the miscellany interface, comprise test interface, GPIO, clock and power management etc.
Generally, the I/O signal that need draw of the mobile phone SOC chip of integrated application function and multimedia function is nearly more than 400.
So many I/O needs guide pins, can cause following several problem:
(1), increases the chip manufacturing cost.In fact, along with the development of microelectronic process engineering, the silicon area cost of chip has reduced many relatively, and the packaging cost proportion is increasing.I/O quantity is big, must increase packaging cost.
(2), increase the Chip Packaging difficulty.Because the technology live width is more and more littler, silicon area is also corresponding to diminish.But I/O quantity is a lot, has not only increased the package area of chip, and makes the encapsulation of chip complicated.
(3), during the system integration, terminal volume is difficult to reduce.This does not meet terminal and trends towards the miniaturization trend.
At this problem, some chips for cell phone have also adopted the mode of pin multiplexing, but mainly are at module level GPIO (general purpose I/O signal) and some test signals to be carried out multiplexingly, have also reduced a small amount of (more than ten) pin.But how many above-mentioned existing problems be there is no improves.
In addition, along with the mobile phone terminal function designs diversified requirement, to chip for cell phone GPIO (quantitative requirement of general purpose I/O) is more, this again with reduce chip pin and become contradiction.
Therefore, need a kind of solution of terminal chip pin multiplexing, can solve the problem in the above-mentioned correlation technique.
Summary of the invention
The present invention is intended to overcome terminal SOC chip, and to draw pin many, and packaging cost height, the shortcoming that the chip entire area is big solve the GPIO lazy weight that exists in the prior art, use the problem of very flexible.
According to an aspect of the present invention, a kind of terminal chip pin multiplexing device is provided, this device comprises: multiplexing control module, be used for the switching between control function module and general purpose I/O interface module, and the direction of the signal of control function module and general purpose I/O interface module; And general purpose I/O interface module, the sense, output CPU configuration level that is used for determining general purpose I/O interface module is to complexing pin and the signal that reads complexing pin, and wherein, each multiplexing control combination logic module is corresponding to a complexing pin.
This device also comprises: a plurality of multiplexing control combination logic modules, the multiplexing control combination logic module of wherein each all is used for handoff functionality module and general purpose I/O interface module, the direction of the signal of control function module and general purpose I/O interface module, and enable control signal or the output enable control signal is controlled complexing pin macroelement module input signal or output signal by input; And a plurality of complexing pin macroelement modules; each complexing pin macroelement module wherein all is used for making complexing pin input signal or output signal according to input enable signal or output enable signal from one of a plurality of multiplexing control combination logic modules; the signal that comprises complexing pin drives, three-state is controlled and the protection of complexing pin; wherein, each complexing pin macroelement module is corresponding to a complexing pin.
Multiplexing control module also is used for the signal that is input to functional module and I/O interface module is interrupted monitoring and management, and the control complexing pin on draw, drop-down, maintenance and hysteresis characteristic.
The I/O interface module also is used to gather the look-at-me of I/O interface module, and exports look-at-me to the CPU minimum system, and obtains the signal from functional module.
Multiplexing control module comprises a plurality of registers, and CPU switches functional module and the general purpose I/O interface module that is connected to complexing pin by a plurality of registers being configured control, and the direction of the signal of control function module and general purpose I/O interface module.
The maximum I/O quantity of I/O interface module support is 256.
The multiplexer mode of complexing pin comprises: normal mode, general purpose I/O interface output mode, general purpose I/O interface input pattern, general purpose I/O interface detecting pattern, functional module alternating pattern, pin alternating pattern and cascade pattern.
Under normal mode, complexing pin is used for the input and output of functional module.
Under general purpose I/O interface output mode, complexing pin is used to export the signal of general purpose I/O interface module, and selects from the signal of general purpose I/O interface module whether winding is to corresponding functional modules.
Under general purpose I/O interface input pattern, complexing pin is used for to general purpose I/O interface module input signal, and whether general purpose I/O interface module configuration allows general purpose I/O interface module to produce interruption.
Under general purpose I/O interface detecting pattern, complexing pin is used for the input and output of functional module, and the signal of while input functional module and the signal of exporting from functional module all are input to general purpose I/O interface module, and CPU reads signal condition, thereby realizes signal monitoring.
Under the functional module alternating pattern, the input of the signal of first functional module is finished by second functional module, and activates corresponding general purpose I/O interface module monitoring pattern.
Under the pin alternating pattern, the signal of first functional module carries out input and output via the second complexing pin macroelement module.
Under the cascade pattern, signal is inputed in a plurality of functional modules one by a plurality of complexing pin macroelement modules.
Adopt the present invention,, simultaneously, do not influence different functional requirement in the differentiation design in the quantity that can reduce the pin of from terminal SOC chip, drawing.Thereby reduction production cost of chip, and the package area of minimizing mobile phone SOC chip help the terminal miniaturization Design.In addition, because most pins are multiplexing with GPIO, the user can flexible configuration GPIO or practical work GP configuring IO, helps chip user chip exterior function expansion and is connected.The method applied in the present invention, its I/O disposes the test that also helps the system design initial stage and the localization of fault of board level system flexibly.
Other features and advantages of the present invention will be set forth in the following description, and, partly from instructions, become apparent, perhaps understand by implementing the present invention.Purpose of the present invention and other advantages can realize and obtain by specifically noted structure in the instructions of being write, claims and accompanying drawing.
Description of drawings
Accompanying drawing described herein is used to provide further understanding of the present invention, constitutes the application's a part, and illustrative examples of the present invention and explanation thereof are used to explain the present invention, do not constitute improper qualification of the present invention.In the accompanying drawings:
Fig. 1 is the functional block diagram that terminal SOC chip commonly used in the prior art is shown;
Fig. 2 is the functional block diagram that illustrates according to terminal SOC chip of the present invention; And
Fig. 3 is the block diagram that illustrates according to the terminal pin multiplexing device of the embodiment of the invention.
Embodiment
Describe embodiments of the invention in detail below in conjunction with accompanying drawing.
Fig. 2 is the functional block diagram that illustrates according to terminal SOC chip of the present invention.With reference to Fig. 2, terminal pin multiplexing device 200 according to the present invention comprises: multiplexing control module 202, be used for the switching between control function module and general purpose I/O interface module, and the direction of the signal of control function module and general purpose I/O interface module; And general purpose I/O interface module 204, the sense, output CPU configuration level that is used for determining general purpose I/O interface module is to complexing pin and the signal that reads complexing pin, and wherein, each multiplexing control combination logic module is corresponding to a complexing pin.
This device also comprises: a plurality of multiplexing control combination logic modules, the multiplexing control combination logic module of wherein each all is used for handoff functionality module and general purpose I/O interface module, the direction of the signal of control function module and general purpose I/O interface module, and enable control signal or the output enable control signal is controlled complexing pin macroelement module input signal or output signal by input; And a plurality of complexing pin macroelement modules; each complexing pin macroelement module wherein all is used for making complexing pin input signal or output signal according to input enable signal or output enable signal from one of a plurality of multiplexing control combination logic modules; the signal that comprises complexing pin drives, three-state is controlled and the protection of complexing pin; wherein, each complexing pin macroelement module is corresponding to a complexing pin.
Multiplexing control module also is used for the signal that is input to functional module and I/O interface module is interrupted monitoring and management, and the control complexing pin on draw, drop-down, maintenance and hysteresis characteristic.
The I/O interface module also is used to gather the look-at-me of I/O interface module, and exports look-at-me to the CPU minimum system, and obtains the signal from functional module.
Multiplexing control module comprises a plurality of registers, and CPU switches functional module and the general purpose I/O interface module that is connected to complexing pin by a plurality of registers being configured control, and the direction of the signal of control function module and general purpose I/O interface module.
The maximum I/O quantity of I/O interface module support is 256.
The multiplexer mode of complexing pin comprises: normal mode, general purpose I/O interface output mode, general purpose I/O interface input pattern, general purpose I/O interface detecting pattern, functional module alternating pattern, pin alternating pattern and cascade pattern.
Under normal mode, complexing pin is used for the input and output of functional module.
Under general purpose I/O interface output mode, complexing pin is used to export the signal of general purpose I/O interface module, and selects from the signal of general purpose I/O interface module whether winding is to corresponding functional modules.
Under general purpose I/O interface input pattern, complexing pin is used for to general purpose I/O interface module input signal, and whether general purpose I/O interface module configuration allows general purpose I/O interface module to produce interruption.
Under general purpose I/O interface detecting pattern, complexing pin is used for the input and output of functional module, and the signal of while input functional module and the signal of exporting from functional module all are input to general purpose I/O interface module, and CPU reads signal condition, thereby realizes signal monitoring.
Under the functional module alternating pattern, the input of the signal of first functional module is finished by second functional module, and activates corresponding general purpose I/O interface module monitoring pattern.
Under the pin alternating pattern, the signal of first functional module carries out input and output via the second complexing pin macroelement module.
Under the cascade pattern, signal is inputed in a plurality of functional modules one by a plurality of complexing pin macroelement modules.
Still one embodiment of the present of invention are described with reference to Fig. 2.
Common pin multiplexing is to carry out at module level, and promptly just GPIO module and partial test and function pin carry out multiplexing.The number of pin of this multiplexing minimizing is very limited.In fact, because the cell-phone function differentiation is bigger, the function of terminal SOC chip is not all can all comprise in each design, and present embodiment utilizes these characteristics to realize that most of pin is system-level multiplexing.
Embodiment carries out multiplexingly at terminal SOC chip system-level, almost most of pin all has configuration and multiplexing function.
Terminal pin multiplexing device in the present embodiment comprises:
The pin multiplexing controller 202 of chip system grade, this controller is the multiplex controller of entire chip, and inside modules has register, and CPU can be configured, and produces different multiplexing functions.Mainly comprise the control of three aspects: the control of each pin multiplexing control combination logic comprises signal source, direction etc.; The Interrupt Process function comprises that the interruption of pin enables, interrupt monitoring and interrupt functions such as multiplexing; The configuration of the specific function of pin is as above drawn, drop-down, magnetic hysteresis and maintenance etc.;
The GPIO module 204 of chip, usually the GPIO module number is few, as 32 etc.System-level multiplexing function can make most of pins have the GPIO function, for example, can reach 128, even 256.The GPIO module has internal register, the configurable register of CPU, and read-write register is with operation GPIO module.
Each complexing pin all has corresponding multiplexing control combination logic 206, and this partial logic is controlled by multiplexing the finish selection of input and output direction, input and output switching etc.;
Chip need be drawn the IP module of I/O signal, as various communication serial port module, multimedia input/output module;
Each draws the PAD macroelement of pin correspondence;
The cpu subsystem that is used for configuration pin in the chip;
Interconnection in the sheet, CPU by interconnection to corresponding module be configured, operation such as read-write;
System-level pin multiplexing in the present embodiment has following principal character:
(1), a system-level multiplex controller is arranged in terminal SOC chip, can finish the functions such as the attached characteristic switching of I/O switching, source, pin of complexing pin;
(2), except that dedicated pin, other pins in the chip are all received the control of reset controller, can be configured according to application need;
(3), chip internal has a GPIO module.All multiplexing pins can both be configured to general purpose I/O (GPIO), and the maximum GPIO that supports can reach 256;
(4), all multiplexing pins can be supported interrupt function by the CPU configuration;
(5), the reset controller module has one-level interrupt management function, can select whether to shield respective interrupt, and finish the interruption monitoring function as required;
(6), each complexing pin can be by to register configuration, select whether to have draw, drop-down, maintenance and hysteresis function; And
(7), pin multiplexing not only can be accomplished the multiplexing of functional module I/O and GPIO signal, can also be the triple multiplexing of two functional module I/O and GPIO signal.
This pin multiplexing also has following characteristics:
(1), the multiplex controller module has corresponding registers, CPU is by realizing multiplexing to register configuration;
(2), this scheme has pin signal capture function, promptly pin is finished the normal function module, can also be with the pin signal map to GPIO; And
(3), this scheme is supported the daisy chain connected mode of pin signal.Be that the pin signal can cascade up by multiplexing control combination logic.
Describe an alternative embodiment of the invention in detail below with reference to Fig. 2～Fig. 3.In this embodiment, terminal SOC chip system-level carries out chip, and to draw signal pin multiplexing, thus increase GPIO quantity, increase draw external interrupt signal in, reduces total output pin, thereby reaches minimizing Chip Packaging number of pin.
The common pin multiplexing device (as shown in Figure 1) of terminal pin multiplexing device shown in Figure 2 and industry is compared, and what increased chip system grade draws signal multiplexing controller module and GPIO module.To might be multiplexing the signal of drawing all passed through multiplexing control combination logic, thereby finish various multiplexer modes.
202 circuit modules among Fig. 2 are the system-level signal reset controllers of drawing.This controller is the multiplex controller of entire chip, and inside modules has register, and CPU can be configured, and produces different multiplexing functions.
Wherein finish corresponding IP module and draw the switching controls of signal and GPIO signal, the control of sense, the interruption monitoring and the management of drawing signal also have this controller management.In addition, the special characteristics of pin is as above drawn, drop-down, maintenance and the also register output signal of module control thus of hysteresis characteristic.
204 circuit modules among Fig. 2 are system-level GPIO circuit modules.The GPIO inside modules has the register of CPU by interconnection configuration and read-write.The GPIO module can be determined the direction of GPIO module by signal according to configuration, can finish the output of CPU configuration level, can read the signal of corresponding complexing pin or the signal of corresponding introducing IP module.In addition, the GPIO module also has the interrupt management function, can gather the look-at-me of each GPIO, and to CPU minimum system output look-at-me.As required, the maximum I/O quantity that can support of GPIO module can reach 256.
206 circuit among Fig. 2 are all multiplexing control combination logics that need multiplexing signal all will pass through.These combinational logics are specifically finished the switching of output signal, the switching of input signal.And the output needed output enable control signal of I/O macroelement and input enable control signal.
Fig. 3 is the synoptic diagram that the specific implementation of present embodiment is shown.
With reference to Fig. 3, the 302nd, need the multiplexing IP module n that draws signal, these IP modules generally comprise communication commonly used such as various serial ports (UART, SPI, I2C, USB, SD/MMC etc.); Multimedia interface is as LCD interface, utilizing camera interface and audio interface etc.; The application function interface is as baseband interface, WLAN interface and blue tooth interface etc.; Memory interface etc.
The 304th, circuit module is system-level GPIO circuit module.This module is finished the output of CPU configuration level, can read the signal of corresponding complexing pin or the signal of corresponding introducing IP module.
The 306th, the system-level signal multiplexing controller circuitry of drawing.This controller is the multiplex controller of entire chip, and inside modules has register, and CPU can be configured, and produces different multiplexing functions.Wherein finish corresponding IP module and draw the switching controls of signal and GPIO signal, the control of sense, the interruption monitoring and the management of drawing signal also have this controller management.In addition, the special characteristics of pin is as above drawn, drop-down, maintenance and the also register output signal of module control thus of hysteresis characteristic.
The 308th, the multiplexing control combination logic n circuit of chip.These combinational logics are specifically finished the switching of output signal, the switching of input signal.And the output needed output enable control signal of I/O macroelement and input enable control signal.Corresponding multiplexing control combination logic of each pin wherein.
The 310th, multiplexing control combination logic m circuit is the multiplexing control combination logic of another one pin, and implementation is identical with multiplexing control combination logic n with function.
The 312nd, PAD (pin) I/O macroelement n.The PAD macroelement is that chip is connected to the outer last circuit of sheet.Comprise output driving, output level conversion, ternary control, incoming level conversion and corresponding protection circuit.
The 314th, another one PAD (pin) I/O macroelement m.
Fig. 3 has represented the realization schematic block circuit diagram of a complexing pin.The chip total system has a multiplex controller and a GPIO module, and each complexing pin all has corresponding multiplexing control combination logic (308 among Fig. 3 and 310) and corresponding PAD macroelement.(312 among Fig. 3 and 314).
Corresponding interactive mode of each circuit module and signal flow are to being described below among Fig. 3:
The signal of the outside that need draw comprises the outer input/output signal of the sheet of all IP modules, GPIO input/output signal.These signals all are connected in the multiplexing control combination logic module.And the concrete input/output signal of multiplexing control combination logic is selected and direction is the signal controlling exported by the multiplex controller module.Multiplex controller has the register of software arrangements, can select corresponding signal and sense flexibly.In addition, there is the register of each complexing pin attribute multiplex controller inside, by CPU configuration, draws on can being with pin configuration, multiple functions such as drop-down, magnetic hysteresis and maintenance.The signal that multiplexing control combination logical and PAD macroelement connects comprises that input enables, output enable, input signal and output signal.The PAD macroelement is finished final pin signal driving, ternary control and defencive function.When being configured to the GPIO input signal, GPIO module monitors and management come from the interruption of GPIO pin.In addition, external input signal also allows to interrupt, and its monitoring and management are finished by the multiplex controller module.Among Fig. 3, multiplexing control combination logic n also has the signal of connection with multiplexing control combination logic m, and the purpose of this signal is that the daisy chain of finishing signal connects and internal loop.
In the present embodiment, according to system requirements, multiplexing dispose following several mode:
1. normal mode, under this pattern, the function of the IP module that pin is finished, for example, UART receiving and transmitting signal etc.
2.GPIO output mode, under this pattern, pin uses as the GPIO output signal.Under this pattern, the GPIO output signal can also select whether loopback is to corresponding IP module.
3.GPIO input pattern, under this pattern, pin uses as the GPIO input signal.Under this pattern, configurable this module that whether allows of GPIO module produces interruption.
4.GPIO monitoring pattern, under this pattern, pin normally uses as the IP module by signal.But this signal is incorporated into the GPIO module simultaneously, and CPU can read this signal condition, thereby reaches the monitoring purpose.
5. the functional module alternating pattern under the normal mode, is finished the signal input of IP module n, under alternating pattern, finishes the function of IP module m, and simultaneously, corresponding GPIO monitoring pattern also can activate.
6. pin alternating pattern, under normal mode, the signal of IP module n is by the PADn input and output.Under the pin alternating pattern, the signal of IP module n is by the PADm input and output.
7. cascade pattern, under this pattern, the input signal of some IP modules can be by a plurality of PAD macroelement inputs.Cascade by multiplexing control combination logic realizes this mode.
By present embodiment, the user can flexible configuration GPIO or practical work GP configuring IO, helps chip user chip exterior function expansion and is connected, and I/O disposes the test that also helps the system design initial stage and the localization of fault of board level system flexibly.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (14)
1. a terminal chip pin multiplexing device is characterized in that, comprising:
Multiplexing control module is used for the switching between control function module and general purpose I/O interface module, and the direction of controlling the signal of described functional module and described general purpose I/O interface module; And
General purpose I/O interface module, the sense, output CPU configuration level that is used for determining described general purpose I/O interface module be to described complexing pin and the signal that reads described complexing pin,
Wherein, each described multiplexing control combination logic module is corresponding to a described complexing pin.
2. device according to claim 1 is characterized in that, also comprises:
A plurality of described multiplexing control combination logic modules, the described multiplexing control combination logic module of wherein each all is used to switch described functional module and described general purpose I/O interface module, control the direction of the signal of described functional module and described general purpose I/O interface module, and enable control signal or the output enable control signal is controlled complexing pin macroelement module input signal or output signal by input; And
A plurality of described complexing pin macroelement modules; the described complexing pin macroelement of wherein each module all is used for making described complexing pin input signal or output signal according to described input enable signal or described output enable signal from one of a plurality of described multiplexing control combination logic modules; the signal that comprises described complexing pin drives, three-state is controlled and the protection of described complexing pin
Wherein, each described complexing pin macroelement module is corresponding to a described complexing pin.
3. device according to claim 1, it is characterized in that, described multiplexing control module also is used for the signal that is input to described functional module and described I/O interface module is interrupted monitoring and management, and control described complexing pin on draw, drop-down, maintenance and hysteresis characteristic.
4. device according to claim 3 is characterized in that described I/O interface module also is used to gather the look-at-me of described I/O interface module, and exports described look-at-me to the CPU minimum system, and obtains the signal from described functional module.
5. device according to claim 3, it is characterized in that, described multiplexing control module comprises a plurality of registers, CPU switches functional module and the general purpose I/O interface module that is connected to described complexing pin by described a plurality of registers being configured control, and the direction of controlling the signal of described functional module and described general purpose I/O interface module.
6. device according to claim 4 is characterized in that, the maximum I/O quantity of described I/O interface module support is 256.
7. device according to claim 2, it is characterized in that the multiplexer mode of described complexing pin comprises: normal mode, general purpose I/O interface output mode, general purpose I/O interface input pattern, general purpose I/O interface detecting pattern, functional module alternating pattern, pin alternating pattern and cascade pattern.
8. device according to claim 7 is characterized in that, under described normal mode, described complexing pin is used for the input and output of described functional module.
9. device according to claim 7, it is characterized in that, under described general purpose I/O interface output mode, described complexing pin is used to export the signal of described general purpose I/O interface module, and selects from the signal of described general purpose I/O interface module whether winding is to corresponding described functional module.
10. device according to claim 7, it is characterized in that, under described general purpose I/O interface input pattern, described complexing pin is used for to described general purpose I/O interface module input signal, and whether described general purpose I/O interface module configuration allows described general purpose I/O interface module to produce interruption.
11. device according to claim 7, it is characterized in that, under described general purpose I/O interface detecting pattern, described complexing pin is used for the input and output of described functional module, the signal of importing the signal of described functional module simultaneously and exporting from described functional module all is input to described general purpose I/O interface module, CPU reads described signal condition, thereby realizes signal monitoring.
12. device according to claim 7 is characterized in that, under described functional module alternating pattern, the input of the signal of first functional module is finished by second functional module, and activates corresponding general purpose I/O interface module monitoring pattern.
13. device according to claim 7 is characterized in that, under described pin alternating pattern, the signal of described first functional module carries out input and output via the second described complexing pin macroelement module.
14. device according to claim 7 is characterized in that, under described cascade pattern, by a plurality of described complexing pin macroelement modules signal is inputed in described a plurality of functional module one.
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