CN216721302U

CN216721302U - Reusable pin circuit for chip

Info

Publication number: CN216721302U
Application number: CN202123239354.6U
Authority: CN
Inventors: 陆网锁; 徐建华
Original assignee: Suzhou Hongxin Integrated Circuit Co ltd
Current assignee: Suzhou Hongxin Integrated Circuit Co ltd
Priority date: 2021-12-22
Filing date: 2021-12-22
Publication date: 2022-06-10
Anticipated expiration: 2031-12-22

Abstract

The utility model discloses a chip reusable pin circuit, which comprises a functional module A, a functional module B, a system configuration module, a multiplexing module, a bare chip pin module and a packaging pin module, wherein the bare chip pin module comprises a pin module A, a pin module B _1 and a pin module B _2, the pin module B _1 and the pin module B _2 are electrically connected with the multiplexing module, the packaging pin module comprises a reusable pin module A/A _ B and a pin module B, the pin module A is electrically connected with the reusable pin module A/A _ B, the pin module B _1 is selectively and electrically connected with the pin module A/A _ B, and the pin module B _2 is selectively and electrically connected with the pin module B. According to the utility model, through fixing the structure of the pin part circuit in the chip serialization development, the connection mode of the corresponding circuit is selected according to the actual packaging size, the manufacture of the mask is simplified, the manufacturing cost of the chip is reduced, and the marketing process of the chip is accelerated.

Description

Reusable pin circuit for chip

Technical Field

The utility model relates to a reusable pin circuit of a chip, belonging to the technical field of chip packaging.

Background

In the current market, the cost of mask plate manufacturing in chip manufacturing accounts for a large proportion of the total cost, and in chip development, a problem that a product needs to be serialized is often faced. Serialization is often represented by the pruning and multiplexing of chip pins. In a conventional circuit design, the circuit structure of the pin part of the serialized chip is changed to adapt to the pin requirement of the chip. Specifically, as shown in fig. 1 and 2, fig. 1 and 2 are schematic pin circuits of a full-size packaged chip and a small-size packaged chip in the prior art, respectively, in the full-size chip package in fig. 1, a pin module B in a bare-chip pin module is connected to a pin module B in a packaged pin module, and in the small-size chip package in fig. 2, the pin module B is connected to a reusable pin module a/a _ B in the packaged pin module, so that the pin module B in the two packages is different in position, and therefore two masks are required, thus, each serialized chip has a specific pin circuit structure, and different masks are required in chip manufacturing, and each mask takes a long time to manufacture, which affects the marketing progress of the chip.

Disclosure of Invention

The utility model aims to provide a reusable chip pin circuit, which aims to solve the problems of deletion and reuse of chip pins in the chip serialization process and accelerate the on-chip marketing process.

In order to achieve the purpose, the utility model provides the following technical scheme: a chip reusable pin circuit comprises a bare chip module and a package pin module, wherein the bare chip module comprises a functional module A, a functional module B, a system configuration module, a multiplexing module and a bare chip pin module, the bare chip pin module comprises a pin module A, a pin module B _1 and a pin module B _2, the functional module A and the system configuration module are electrically connected with the pin module A, the functional module B and the system configuration module are electrically connected with the multiplexing module, the system configuration module is electrically connected with the pin module B _1, the pin module B _1 and the pin module B _2 are electrically connected with the multiplexing module, the package pin module comprises a reusable pin module A/A _ B and a reusable pin module B, the pin module A is electrically connected with the reusable pin module A/A _ B, the pin module B _1 can be selectively and electrically connected with the reusable pin module A/A _ B, and the pin module B _2 can be selectively and electrically connected with the pin module B.

Further, the chip can multiplex a pin circuit, wherein: when the chip is packaged in a full size, the system configuration module controls the multiplexing module to select the pin module B _2, and the pin module B _2 is connected with the pin module B of the packaged pin module, so that the circuits of the functional module B, the pin module B _2 and the pin module B are conducted.

Further, the chip can multiplex a pin circuit, wherein: when the chip is packaged in a small size, the system configuration module controls the multiplexing module to select the pin module B _1, the pin module B _1 is connected with the multiplexing pin module A/A _ B of the packaged pin module, so that the lines of the functional module B, the pin module B _1 and the multiplexing pin module A/A _ B are conducted, and the pin module B is vacant.

Further, the chip can multiplex a pin circuit, wherein: and other pin modules are arranged in the bare chip pin module and the packaging pin module, and the other pin modules of the bare chip pin module are correspondingly and electrically connected with the other pin modules in the packaging pin module.

Further, the chip can multiplex a pin circuit, wherein: and an inverter is connected between the system configuration module and the pin module B _ 1.

The utility model has the beneficial effects that: the utility model sets two groups of pin modules in the bare chip pin module, sets the system configuration module and the multiplexing module in the bare chip module, can select the needed pin module through the system configuration module, and selects the corresponding pin module and the corresponding circuit connection mode thereof according to the actual packaging size through fixing the structure of the partial circuit of the pin part in the serial development of the chip, thereby simplifying the manufacture of the mask plate, reducing the manufacturing cost of the chip and accelerating the marketing process of the chip.

Drawings

FIG. 1 is a prior art pin electronics schematic of a full-scale packaged chip;

FIG. 2 is a circuit diagram of a small-sized chip pin in the prior art

FIG. 3 is a diagram of a reusable pin circuit of a chip according to the present invention;

FIG. 4 is a schematic diagram of a full-scale package circuit of the chip of the present invention;

FIG. 5 is a circuit diagram of a small-sized chip package according to the present invention.

Detailed Description

In order to further understand the contents, features and effects of the present invention, the following embodiments are illustrated and described in detail with reference to the accompanying drawings.

Referring to fig. 1 to fig. 5, a reusable pin circuit of a chip according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

As shown in fig. 3 to 5, a chip reusable pin circuit according to the present invention includes a bare chip module and a package pin module, the bare chip module includes a functional module a, a functional module B, a system configuration module, a multiplexing module (i.e. MUX in the figure), and the bare chip pin module includes a pin module a, a pin module B _1, and a pin module B _2, the functional module a and the system configuration module are electrically connected to the pin module a, the functional module B and the system configuration module are electrically connected to the multiplexing module, the system configuration module is electrically connected to the pin module B _1, the pin module B _1 and the pin module B _2 are electrically connected to the multiplexing module, the package pin module includes a reusable pin module a/a _ B and a pin module B, the pin module a is electrically connected to the reusable pin module a/a _ B, the pin module B _1 can be selectively and electrically connected with the reusable pin module A/A _ B, and the pin module B _2 can be selectively and electrically connected with the pin module B, wherein one circuit is selected from the two to be electrically connected.

It should be noted that the dashed line connecting pin module B and pin module B _2 in fig. 3 indicates that this lead line is only possible in a full-scale package. The dashed line connecting the reusable pin module A/A _ B with the pin module B _1 indicates that this lead is only possible with small-scale packages. The pin module B _1 and the pin module B _2 are 2 candidate pins for realizing the functional module B, and exist on the die. The reusable pin module A/A _ B indicates that under different packaging, the pin module can be used for the individual pin module A or in a multiplexed mode for the pin module A and the pin module B _ 1. The alternative multiplexing module MUX in the figure is controlled by the system configuration module.

Example 1

As shown in fig. 4, when the chip needs a full-scale package, the pin module a is turned on and the pin module B _1 is turned off by the system configuration module. And the system configuration module controls the multiplexing module MUX to select the pin module B _2 as the communication PAD of the module B, electrically connects the pin module B _2 with the pin module B of the packaging pin module, and then the functional module B, the pin module B _2 and the pin module B are conducted.

Example 2

As shown in fig. 5, when the chip needs a small-sized package, the system configuration module turns on the pin module a and turns off the pin module B _1, or turns on the pin module B _1 and turns off the pin module a according to the user setting. And the system configuration module controls the multiplexing module to select to start the pin module B _1, at the moment, the pin module B _1 is used as the communication PAD of the module B, and the pin module B _2 cannot be packaged on a pin. The pin module B _1 is electrically connected with the reusable pin module A/A _ B of the packaging pin module, the circuits of the functional module B, the pin module B _1 and the reusable pin module A/A _ B are conducted, at the moment, the pin module B _1 is not connected with the pin module B of the packaging pin module, and the pin module B _1 and the pin module B of the packaging pin module are vacant.

Preferably, other pin modules are arranged in the bare chip pin module and the packaging pin module, and the other pin modules of the bare chip pin module are correspondingly and electrically connected with the other pin modules in the packaging pin module. And a line between the system configuration module and the pin module B _1 is connected with an inverter, and the inverter has the function of ensuring that only one of the pin module A and the pin module B _1 is started at the same time.

It can be seen from the above description that the present invention has two sets of pin modules, i.e. a pin module B _1 and a pin module B _2, and the system configuration module is added to control the multiplexing module MUX to select the pin module B _1 or the pin module B _2, and at the same time, the system configuration module also controls whether the pin module B _1 is turned on, so that only one mask is needed, and by fixing the structure of the pin part circuit in the chip serialization development, the connection mode of the corresponding circuit is selected according to the actual package size, thereby simplifying the manufacture of the mask, reducing the chip manufacturing cost, and accelerating the marketing process of the chip.

The above are only typical examples of the present invention, and besides, the present invention may have other embodiments, and all the technical solutions formed by equivalent substitutions or equivalent changes are within the scope of the present invention as claimed.

Claims

1. A chip reusable pin circuit is characterized by comprising a bare chip module and a package pin module, wherein the bare chip module comprises a functional module A, a functional module B, a system configuration module, a multiplexing module and a bare chip pin module, the bare chip pin module comprises a pin module A, a pin module B _1 and a pin module B _2, the functional module A and the system configuration module are electrically connected with the pin module A, the functional module B and the system configuration module are electrically connected with the multiplexing module, the system configuration module is electrically connected with the pin module B _1, the pin module B _1 and the pin module B _2 are electrically connected with the multiplexing module, the package pin module comprises a reusable pin module A/A _ B and a reusable pin module B, the pin module A is electrically connected with the reusable pin module A/A _ B, the pin module B _1 can be selectively and electrically connected with the reusable pin module A/A _ B, and the pin module B _2 can be selectively and electrically connected with the pin module B.

2. The chip multiplexing pin circuit according to claim 1, wherein when the chip is packaged in a full size, the system configuration module controls the multiplexing module to select the pin module B _2, and the pin module B _2 is connected to the pin module B of the packaged pin module, so that the functional module B, the pin module B _2, and the pin module B are electrically connected.

3. The chip reusable pin circuit according to claim 2, wherein when the chip is a small-sized package, the system configuration module controls the multiplexing module to select the pin module B _1, and the pin module B _1 is connected to the reusable pin module a/a _ B of the package pin module, so that the functional module B, the pin module B _1, and the reusable pin module a/a _ B are connected, and the pin module B is idle.

4. The chip reusable pin circuit according to claim 1, wherein other pin modules are provided in the bare chip pin module and the package pin module, and the other pin modules of the bare chip pin module are electrically connected to the other pin modules in the package pin module correspondingly.

5. The chip multiplexing pin circuit according to claim 1, wherein an inverter is connected between the system configuration module and the pin module B _ 1.