CN201290199Y - Circuit board - Google Patents
Circuit board Download PDFInfo
- Publication number
- CN201290199Y CN201290199Y CNU2008201230566U CN200820123056U CN201290199Y CN 201290199 Y CN201290199 Y CN 201290199Y CN U2008201230566 U CNU2008201230566 U CN U2008201230566U CN 200820123056 U CN200820123056 U CN 200820123056U CN 201290199 Y CN201290199 Y CN 201290199Y
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- integrated circuit
- circuit board
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Abstract
The utility model discloses a circuit board. The circuit board is fixed with two groups of double-row straight-line type integrated circuit chips with same width, space length of adjacent pins in same row of each integrated circuit chip is one in a distance set, the distance set is composed of values that of 1 to N times of a fixation value, wherein N is a random natural number more than 1; each group of integrated circuit chips have at least one chip; the solder pad position of any group of integrated circuit chips on the circuit board is fixed corresponding to that of other groups of integrated circuit chips on the circuit board, and at least part pins are connected coincidently. The circuit board of the utility model makes uses have more qualitative choice conveniently in case for farthest decreasing usable floor area of the circuit board.
Description
Technical field
The utility model belongs to the board design technical field, particularly a kind of circuit board.
Background technology
Present stage, the design of circuit board has become particularly important in the various electronic products.On the circuit board, usually contain power interface, signal input interface and signal output interface, and can be connected with various electronic devices, for example be connected with resistance, electric capacity, inductance coil, power supply chip, chip for driving, input control chip, output control chip, logic control chip or the like is to realize the different function of circuit board.At present, how more to optimize the line of chip chamber, and how to save the area of circuit board more, when board design, need emphasis to consider.
At present, usually according to the needs of determining element and function, consider to reserve the position of pad in the process of board design, after the ifs circuit plate completes, want to realize that other functions or chip connect, can only change circuit board again.Will cause the huge waste of cost like this.Therefore, there is defective in prior art, needs further improvement and develops.
The utility model content
The utility model is in order to solve the deficiency on the prior art, particularly a kind of circuit board.
A kind of circuit board comprises the biserial orthoscopic integrated circuit (IC) chip that at least two group width are identical, and wherein, each is organized integrated circuit (IC) chip and all contains at least one chip;
The adjacent pin of the same row of each integrated circuit (IC) chip, its spacing are wherein of a distance set, and described distance set is 1 times of set of doubly being formed to N of a fixed value, and N is the arbitrary natural number greater than 1;
The pad locations of arbitrary group of integrated circuit (IC) chip on described circuit board is with the corresponding setting of other group pad locations of integrated circuit (IC) chip on described circuit board, to small part pin coincidence connection.
Circuit board described in the utility model, also comprise power module, signal input interface module and signal output interface module, each organize integrated circuit (IC) chip in the serial or parallel connection mode after, be connected with power module, signal input interface module, signal output interface module respectively.
Circuit board described in the utility model, it only comprises two groups of biserial orthoscopic integrated circuit (IC) chip that width is identical,
First group of integrated circuit (IC) chip be the pad locations on described circuit board in the pad locations on the described circuit board and second group of integrated circuit (IC) chip, all overlap setting, and, the pin of first group of integrated circuit (IC) chip, with the pin of second group of integrated circuit (IC) chip, all overlap connection;
Or first group of integrated circuit (IC) chip be the pad locations on described circuit board in the pad locations on the described circuit board and second group of integrated circuit (IC) chip, and setting partially overlaps, and, the pin of first group of integrated circuit (IC) chip, with the pin of second group of integrated circuit (IC) chip, connection partially overlaps.
Among the utility model embodiment, the same tubulation pin of same integrated circuit (IC) chip, the spacing between the adjacent pin equates.
Among the utility model embodiment, described biserial orthoscopic integrated circuit (IC) chip adopts DIP dual in-line package, the little external form encapsulation of SOP, the encapsulation of SSOP scaled-down version or the thin little outline packages of TSOP.
Among the utility model embodiment, in each integrated circuit (IC) chip group, the standard soldering board spacing that is spaced apart at least 1 pin of each chip.
The beneficial effects of the utility model, adopt method for designing of the present utility model and circuit board, under the situation of the usable floor area that can reduce circuit board to greatest extent, make things convenient for the user to have more quality to select, so that under the situation of not changing circuit board, can obtain more function, thereby on the basis that reduces risk and production cost, realize product diversification production to greatest extent.
Description of drawings
Fig. 1 is the schematic diagram of the utility model embodiment 1 and 2;
Fig. 2 is the schematic diagram of the utility model embodiment 3;
Fig. 3 is the schematic diagram of the utility model embodiment 4;
Fig. 4 is the schematic diagram of the utility model embodiment 5;
Fig. 5 is the schematic diagram of the utility model embodiment 6.
Embodiment
Below in conjunction with accompanying drawing and preferred embodiment the utility model is done further to elaborate, embodiment also is not understood to restriction of the present utility model.
With reference to accompanying drawing Fig. 1, the utility model provides a kind of circuit board, wherein, each is organized integrated circuit (IC) chip and all contains at least one chip, with the pad locations of arbitrary group of integrated circuit (IC) chip on described circuit board, with the corresponding setting of other group pad locations of integrated circuit (IC) chip on described circuit board, to small part pin coincidence connection.
Be preferably, the same tubulation pin for same chip is made as the spacing between the adjacent pin equal.Perhaps, for each chip of same group of integrated circuit (IC) chip, be made as the spacing between its adjacent pin equal.
In the present embodiment, two groups of biserial orthoscopic integrated circuit (IC) chip that width is identical are set;
With first group of integrated circuit (IC) chip in the pad locations on the described circuit board and second group of integrated circuit (IC) chip the pad locations on described circuit board, all overlap and be provided with, and,, all overlap and connect with the pin of second group of integrated circuit (IC) chip with the pin of first group of integrated circuit (IC) chip; The identical circuit board line of promptly shared correspondingly definition.
In addition, adopt the thin little outline packages mode of DIP dual in-line package mode, the little external form packaged type of SOP, SSOP scaled-down version packaged type or TSOP in this circuit board, described biserial orthoscopic integrated circuit (IC) chip is encapsulated.
Adopt circuit board described in the utility model, can save the space of circuit board to greatest extent, thereby provide cost savings, wherein, by the recycling pad, different chip in the connection can also be realized different functions, has promptly realized the variation of product.
Embodiment 2
With reference to accompanying drawing Fig. 1, the utility model also provides a kind of circuit board, and it comprises the biserial orthoscopic integrated circuit (IC) chip that at least two group width are identical, and wherein, each is organized integrated circuit (IC) chip and all contains at least one chip; The adjacent pin of the same row of each integrated circuit (IC) chip, its spacing are wherein of a distance set, and described distance set is 1 times of set of doubly being formed to N of a fixed value, and N is the arbitrary natural number greater than 1; The pad locations of arbitrary group of integrated circuit (IC) chip on described circuit board is with the corresponding setting of other group pad locations of integrated circuit (IC) chip on described circuit board, to small part pin coincidence connection.
For example, the same tubulation pin of same integrated circuit (IC) chip, the spacing between the adjacent pin equates.And for example, in each integrated circuit (IC) chip group, the standard soldering board spacing that is spaced apart at least 1 pin of each chip.
With reference to accompanying drawing Fig. 1, this example is a kind of circuit board 100, has only explained the part of this circuit board among the figure, wherein, circuit board shown in the figure contains power module 101, signal input interface module 102 and signal output interface module 103, and power module 101 links to each other with signal input interface module 102.Power module, signal input interface module and signal output interface module, each organize integrated circuit (IC) chip in the serial or parallel connection mode after, be connected with power module, signal input interface module, signal output interface module respectively.In the present embodiment, integrated circuit (IC) chip 107,109 and 110 all adopts DIP dual in-line package mode.
Need to prove that the circuit board 100 that contains above-mentioned module should not be construed as restriction of the present utility model, in the available circuit technology, all the other various circuit connect and do not exceed restriction of the present utility model.
Reserved 2 pad locations 108 that wait width on the circuit board 100, and pad locations adopts and arrange up and down, need to prove herein, arrange about also can adopting or oblique certain angle is arranged, as long as 2 pad locations 108 are provided with point-blank.
Wherein, the distance between pad and the pad is the standard soldering board spacing of 1 pin, and in the practical application, distance also can be other spacings; And 2 pad locations all contain the tie point of 2 input pins and the tie point of 2 output pins, the input pin tie point 106 of each pad is connected with described signal input interface module 102 respectively, and its output pin tie point 105 is connected with described signal output interface module 103 respectively., need explanation herein, the distance between pad and the pad can also be the integral multiple of standard soldering board spacing arbitrarily, the spacing of 2 pins for example, and the spacing of 5 pins etc., this is a general knowledge as well known to those skilled in the art, does not repeat them here.
In described pad locations 108, can also weld second chipset, it contains an integrated circuit (IC) chip 107, and this integrated circuit (IC) chip 107 contains 4 inputs, output pin, also overlaps with pad locations 108 fully.
By present embodiment as can be seen, on the pad locations 108 of circuit board 100, an integrated circuit (IC) chip 110 and an integrated circuit (IC) chip 109 both can have been welded respectively, also can weld an integrated circuit (IC) chip 107, promptly can connect by the identical circuit board of shared correspondingly definition, realize identical functions.Thereby can not change circuit board, just different chips can be installed, realize difference in functionality.And pass through the multiplexing of pad locations 108, and also saved the space of circuit board 100 greatly, provide cost savings.
Embodiment 3
With reference to accompanying drawing Fig. 2, the utility model embodiment difference from Example 2 is, be reserved with 2 pad locations on the circuit board 100, one of them pad locations contains 4 incoming junctions, 4 output connections, and another pad locations contains 2 incoming junctions, 2 output connections.
In addition, in this enforcement, first chipset is that integrated circuit (IC) chip 109 and 110, the second chipsets are integrated circuit (IC) chip 107, and they all adopt the little external form packaged type of SOP.
All the other are identical with embodiment 2, do not repeat them here.
By present embodiment, can customize different circuit boards according to client's individual demand, so that integrated circuit (IC) chip not of the same race to be installed, realize function not of the same race, provide cost savings.
Embodiment 4
With reference to accompanying drawing Fig. 3, the utility model embodiment difference from Example 2 is, 3 pad locations have been reserved on the circuit board 100, wherein first pad locations respectively contains 4 incoming junctions, 4 output connections, and second pad locations and the 3rd pad locations all respectively contain 2 incoming junctions, 2 output connections.
First chipset is integrated circuit (IC) chip 109, chip 110 and chip 120, and they all adopt SSOP scaled-down version packaged type, and reserves pad locations and overlaps fully.
Second chipset is an integrated circuit (IC) chip 111, also adopts SSOP scaled-down version packaged type, and contains 8 input pins and 8 output pins respectively, also overlaps fully with the reservation pad locations.
All the other are identical with embodiment 2, do not repeat them here.
By present embodiment, as can be seen, adopt this mode, can save circuit board space more.
Embodiment 5
With reference to accompanying drawing Fig. 4, the present embodiment difference from Example 2 is, 3 pad locations have been reserved on the circuit board 100, wherein first pad locations respectively contains 4 incoming junctions, 4 output connections, and second pad locations and the 3rd pad locations all respectively contain 2 incoming junctions, 2 output connections.
First chipset contains 3 integrated circuit (IC) chip, is respectively integrated circuit (IC) chip 109, integrated circuit (IC) chip 110 and integrated circuit (IC) chip 120, and they all adopt SSOP scaled-down version packaged type, and with reserve pad locations and overlap fully.
Second chipset contains 2 integrated circuit (IC) chip 112 and integrated circuit (IC) chip 113, and wherein, integrated circuit (IC) chip 112 contains 5 input pins and 5 output pins respectively, and integrated circuit (IC) chip 113 contains 3 input pins and 3 output pins respectively.
By present embodiment as can be seen, when being reserved with a plurality of pad locations, can there be multiple integrated circuit (IC) chip to connect, under the situation of not changing circuit board, realizes more kinds of functions in pad locations.
Embodiment 6
With reference to accompanying drawing Fig. 5, the present embodiment difference from Example 2 is, 3 pad locations have been reserved on the circuit board 100, wherein first pad locations respectively contains 4 incoming junctions, 4 output connections, and second pad locations and the 3rd pad locations all respectively contain 2 incoming junctions, 2 output connections.
First chipset contains 3 integrated circuit (IC) chip, is respectively integrated circuit (IC) chip 109, integrated circuit (IC) chip 110 and integrated circuit (IC) chip 120, and they all adopt SSOP scaled-down version packaged type, and with reserve pad locations and overlap fully.
Second chipset contains an integrated circuit (IC) chip 114, also adopts SSOP scaled-down version packaged type, and wherein integrated circuit (IC) chip 114 not exclusively covers 3 pad locations reserving, and only with wherein part tie point welding.
By present embodiment as can be seen, when being reserved with a plurality of pad, can be in the integrated circuit (IC) chip that pad locations is welded and pad locations overlaps fully, also can weld, the incomplete chip that overlaps, the utilance of the circuit board that improves, and under the situation of not changing circuit board, realize more function.
By above embodiment the utility model has been carried out further announcement, but scope of the present utility model is not limited thereto, do not departing under the condition of the utility model design, more than each module can replace with the similar or equivalent module that affiliated technical field personnel understand.
Claims (6)
1, a kind of circuit board is characterized in that, comprises the biserial orthoscopic integrated circuit (IC) chip that at least two group width are identical,
Wherein, each is organized integrated circuit (IC) chip and all contains at least one chip;
The adjacent pin of the same row of each integrated circuit (IC) chip, its spacing are wherein of a distance set, and described distance set is 1 times of set of doubly being formed to N of a fixed value, and N is the arbitrary natural number greater than 1;
The pad locations of arbitrary group of integrated circuit (IC) chip on described circuit board is with the corresponding setting of other group pad locations of integrated circuit (IC) chip on described circuit board, to small part pin coincidence connection.
2, circuit board according to claim 1, it is characterized in that, also comprise power module, signal input interface module and signal output interface module, each organize integrated circuit (IC) chip in the serial or parallel connection mode after, be connected with power module, signal input interface module, signal output interface module respectively.
3, circuit board according to claim 1 and 2 is characterized in that, it only comprises two groups of biserial orthoscopic integrated circuit (IC) chip that width is identical,
First group of integrated circuit (IC) chip be the pad locations on described circuit board in the pad locations on the described circuit board and second group of integrated circuit (IC) chip, all overlap setting, and, the pin of first group of integrated circuit (IC) chip, with the pin of second group of integrated circuit (IC) chip, all overlap connection;
Or first group of integrated circuit (IC) chip be the pad locations on described circuit board in the pad locations on the described circuit board and second group of integrated circuit (IC) chip, and setting partially overlaps, and, the pin of first group of integrated circuit (IC) chip, with the pin of second group of integrated circuit (IC) chip, connection partially overlaps.
4, circuit board according to claim 1 and 2 is characterized in that, the same tubulation pin of same integrated circuit (IC) chip, and the spacing between the adjacent pin equates.
5, circuit board according to claim 1 and 2 is characterized in that, described biserial orthoscopic integrated circuit (IC) chip adopts DIP dual in-line package, the little external form encapsulation of SOP, the encapsulation of SSOP scaled-down version or the thin little outline packages of TSOP.
6, circuit board according to claim 1 and 2 is characterized in that, in each integrated circuit (IC) chip group, and the standard soldering board spacing that is spaced apart at least 1 pin of each chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008201230566U CN201290199Y (en) | 2008-10-20 | 2008-10-20 | Circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008201230566U CN201290199Y (en) | 2008-10-20 | 2008-10-20 | Circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201290199Y true CN201290199Y (en) | 2009-08-12 |
Family
ID=40981878
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNU2008201230566U Expired - Fee Related CN201290199Y (en) | 2008-10-20 | 2008-10-20 | Circuit board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201290199Y (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101394708B (en) * | 2008-10-20 | 2012-11-28 | 李鑫 | Circuit board and design method therefor |
| CN105188255A (en) * | 2015-08-03 | 2015-12-23 | 浪潮集团有限公司 | Non-divergence compatibility circuit design method in PCB |
-
2008
- 2008-10-20 CN CNU2008201230566U patent/CN201290199Y/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101394708B (en) * | 2008-10-20 | 2012-11-28 | 李鑫 | Circuit board and design method therefor |
| CN105188255A (en) * | 2015-08-03 | 2015-12-23 | 浪潮集团有限公司 | Non-divergence compatibility circuit design method in PCB |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: SHENZHEN ZHONGQINGWEI TECHNOLOGY DEVELOPMENT CO., Free format text: FORMER OWNER: BEIJING JUSHU DIGITAL TECHNOLOGY DEVELOPMENT CO., LTD. Effective date: 20110720 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 100085 ROOM 402B, TOWER E, YINGCHUANG POWER PARK, NO. 1, SHANGDI EAST ROAD, HAIDIAN DISTRICT, BEIJING TO: 518040 706, TAIRAN FACTORY BUILDING 211, CHEGONGMIAO INDUSTRIAL ZONE, FUTIAN DISTRICT, SHENZHEN CITY, GUANGDONG PROVINCE |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20110720 Address after: Futian District Che Kung Temple Tairan Industrial Zone in Shenzhen city of Guangdong province 518040 211 industrial buildings 706 Patentee after: Shenzhen Zhongqingwei Technology Development Co., Ltd. Address before: 100085 Beijing city Haidian District East Road No. 1 building E room 402B power Creative Park Patentee before: Beijing Jushu Digital Technology Development Co., Ltd. |
|
| DD01 | Delivery of document by public notice |
Addressee: Shenzhen Zhongqingwei Technology Development Co., Ltd. Document name: Notification to Pay the Fees |
|
| DD01 | Delivery of document by public notice | ||
| DD01 | Delivery of document by public notice |
Addressee: Shenzhen Zhongqingwei Technology Development Co., Ltd. Document name: Notification of Termination of Patent Right |
|
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090812 Termination date: 20131020 |