CN108986853B - Storage control chip, storage device and self-adaptive interface method - Google Patents
Storage control chip, storage device and self-adaptive interface method Download PDFInfo
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- CN108986853B CN108986853B CN201810595357.7A CN201810595357A CN108986853B CN 108986853 B CN108986853 B CN 108986853B CN 201810595357 A CN201810595357 A CN 201810595357A CN 108986853 B CN108986853 B CN 108986853B
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- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
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Abstract
The invention relates to the technical field of chips and discloses a storage control chip, storage equipment and a self-adaptive interface method. The storage control chip is connected with the first memory and the second memory, and comprises: the interface circuit is used for being connected with the first memory and the second memory; the function selection circuit is connected with the interface circuit and is used for selecting the interface function of the interface circuit; and the controller is respectively connected with the interface circuit and the function selection circuit and is used for configuring the state of the interface circuit and controlling the function selection circuit to select the interface function. In this way, the embodiment of the invention can simplify the connection line of the storage device.
Description
Technical Field
The present invention relates to the field of chip technologies, and in particular, to a memory control chip, a memory device, and an adaptive interface method.
Background
The storage device includes a USB flash disk (USB flash disk), an SSD, an emmc, an EMCP, a ufs, an SD card, and the like, and is widely applied to various products, such as electronic products, such as computers and mobile phones. As the functions of electronic products become more and more abundant and the volume thereof is developing towards lightness, thinness and miniaturization, it puts higher demands on the structure of the internal circuit board of the storage device.
In the design of the circuit board, when the two sides of the circuit board need to be subjected to the chip mounting operation, the problem of pin definition sequence can be encountered. As shown in fig. 1 and 2, the memory device 1 includes a first memory 01, a second memory 02 and a controller 03, the first memory 01 and the second memory 02 are respectively connected with the controller 03, and the pins I/O0-I/O7 on the first memory 01 are in reverse order to the pins I/O0-I/O7 on the second memory 02 due to the opposite placement positions, so that the connection lines between the second memory 02 and the controller 03 are crossed, thereby increasing the difficulty of the layout of the printed circuit board, and the long-length wiring affects the timing and the interference resistance of high-speed signals.
In the process of implementing the embodiment of the invention, the inventor finds that the connection circuit of the memory device in the prior art is complex, and further influences the performance of the memory device.
Disclosure of Invention
The technical problem mainly solved by the embodiments of the present invention is to provide a method and an apparatus for chip adaptive connection, and an electronic device, which can simplify the connection line of a storage device.
In order to solve the above technical problems, embodiments of the present invention provide the following technical solutions:
in a first aspect, an embodiment of the present invention provides a memory control chip, which is connected to a first memory and a second memory, where the memory control chip includes: the interface circuit is used for being connected with the first memory and the second memory; the function selection circuit is connected with the interface circuit and is used for selecting the interface function of the interface circuit; and the controller is respectively connected with the interface circuit and the function selection circuit and is used for configuring the state of the interface circuit and controlling the function selection circuit to select the interface function.
Optionally, the interface circuit comprises: a pad and a data bus; the bonding pads are respectively connected with the first memory and the second memory; the function selection circuit is respectively connected with the pad and the data bus, the controller is respectively connected with the pad and the data bus, and the controller is specifically used for configuring the state of the pad and controlling the function selection circuit to select the interface function of the pad.
Optionally, the first memory and the second memory respectively include pins to be inverted, and the number of the pins to be inverted of the first memory and the second memory corresponds to the number of the welding points of the pad; pins to be inverted of the first memory and the second memory are connected with the controller through welding points of the welding pads.
Optionally, the controller comprises a state configuration module and a reverse control module; the state configuration module is connected with the bonding pad and used for configuring the state of the bonding pad; the reverse control module is connected with the function selection circuit and is used for controlling the function selection circuit to select the interface function.
Optionally, the function selection circuit includes a first switch tube and a second switch tube; one end of the first switch tube and one end of the second switch tube are respectively connected with the welding disc, and the other end of the first switch tube and the other end of the second switch tube are respectively connected with the data bus; the inversion control module is respectively connected with the first switch tube and the second switch tube, and is specifically used for controlling selective conduction of the first switch tube or the second switch tube.
Optionally, the memory control chip further includes: and the reverse function identification module is respectively connected with the interface circuit and the controller and used for acquiring the state of the interface circuit and determining whether the controller triggers a reverse function instruction according to the state of the interface circuit.
Optionally, the inverse function identification module is specifically configured to: and the controller is connected with a pad welding point of the interface circuit and determines whether to trigger an inverse function instruction according to a response signal generated by an input signal of the welding point in a preset state.
Optionally, the inverse function identification module is further configured to: and acquiring the return state of the first memory or the second memory for the specific instruction, and determining whether the controller triggers a reverse function instruction according to the return state.
Optionally, the state of the interface circuit includes one or more of a push-pull output, an open-drain output, a multiplexed push-pull output, a pull-up input, a pull-down input, a floating input, and an analog input.
In a second aspect, an embodiment of the present invention provides a storage device, which is characterized by including a first memory, a second memory, and the storage control chip.
Optionally, the first memory, the second memory and the memory control chip are disposed on a same printed circuit board, and the first memory and the second memory are disposed on two opposite surfaces of the same printed circuit board, respectively.
In a third aspect, an embodiment of the present invention provides an adaptive interface method, which is applied to the foregoing storage control chip, and the method includes: configuring the state of an interface circuit of the storage control chip; judging whether the inversion is needed, if so, sending an inversion function instruction; and controlling a function selection circuit of the storage control chip to select the interface function of the interface circuit according to the inverted function instruction.
In a fourth aspect, an embodiment of the present invention provides an adaptive interface apparatus, which is applied to the foregoing memory control chip, where the apparatus includes: the state configuration unit is used for configuring the state of an interface circuit of the storage control chip; the instruction sending unit is used for judging whether the inversion is needed or not, and sending an inversion function instruction if the inversion is needed; and the reverse unit is used for controlling the function selection circuit of the storage control chip to select the interface function of the interface circuit according to the reverse function instruction.
In a fifth aspect, embodiments of the present invention provide a non-transitory computer-readable storage medium storing computer-executable instructions for an electronic device to perform a method in any of the above method embodiments.
In a sixth aspect, embodiments of the present invention provide a computer program product comprising a computer program stored on a non-volatile computer-readable storage medium, the computer program comprising program instructions which, when executed by a computer, cause the computer to perform the method described above.
According to the memory control chip provided by the embodiment of the invention, the interface circuit and the function selection circuit are arranged, the controller configures the state of the interface circuit and controls the function selection circuit to select the interface function of the interface circuit, so that the pin state of the second memory connected with the interface circuit can be matched with the pin state of the first memory connected with the interface circuit, and the connecting line between the second memory and the interface circuit is simplified.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.
FIG. 1 is a schematic diagram of a prior art memory device;
fig. 2 is a schematic structural diagram of functional modules of a computer system according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a memory device of the computer system of FIG. 2;
fig. 4 is a schematic structural diagram of a memory control chip according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a connection structure of the storage device of FIG. 3;
FIG. 6 is a schematic diagram of the memory controller chip of FIG. 4;
FIG. 7 is a schematic diagram of a portion of the memory controller chip of FIG. 4;
fig. 8 is a flowchart illustrating an adaptive interface method according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram of an adaptive interface device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The invention includes a memory control chip, a memory device and a self-adaptive interface method, wherein, the memory control chip is connected with a first memory and a second memory, the memory control chip includes: the interface circuit is respectively connected with the first memory and the second memory, and the function selection circuit is connected with the interface circuit and is used for selecting the interface function of the interface circuit; and the controller is connected with the interface circuit and the function selection circuit through the interface circuit and is used for configuring the state of the interface circuit and controlling the function selection circuit to select the interface function.
The memory control chip, the memory device and the adaptive interface method provided by the embodiment of the invention can obtain various beneficial effects, such as: the connection lines of the memory device are simplified, again for example: the routing is shortened, the transmission speed of signals is improved, and the anti-interference performance of the storage device is enhanced.
Fig. 2 is a schematic structural diagram of functional modules of a computer system according to an embodiment of the present invention. As shown in FIG. 2, computer system 100 includes a host 10 and a storage device 20 communicatively coupled to host 10. For example, storage device 20 may be communicatively coupled to host 10 through interface 30.
The storage device 20 may be a USB flash disk (USB flash disk), an SSD, an emmc, an EMCP, a ufs, an SD card, or the like.
The interface 30 may be a Serial Advanced Technology Attachment (SATA), a peripheral component interconnect express (PCIe), or a Universal Serial Bus (USB), among other connectors and interfaces. In general, the interface 30 may provide an interface for passing control, address, data, and other signals between the storage device 20 and the host 10.
It should be noted that the storage device 20 may be used in several different computing systems, either in conjunction with or instead of a hard disk drive. The computer system 100 illustrated in FIG. 1 is one example of such a system; however, embodiments of the present invention are not limited to the structure shown in FIG. 1.
Fig. 3 is a schematic structural diagram of a storage device of the computer system of fig. 2. As shown in fig. 3, the storage device 20 includes a first memory 21, a second memory 22, and a storage control chip 23.
The functions of the first memory 21 and the second memory 22 may be implemented by a memory chip, for example, a flash chip, and the flash type chip may be a NAND flash chip. The function of the storage control chip 23 may be implemented by a control chip, such as a single chip.
The first memory 21, the second memory 22 and the memory control chip 23 are disposed on the same printed circuit board, the first memory 21 and the second memory 22 are disposed on two opposite surfaces of the same printed circuit board, and the first memory 21 and the second memory 22 are connected to the memory control chip 23. The memory control chip 23 is used to perform function switching according to the connection manner of the first memory 21 and the second memory 22, thereby simplifying the connection line of the memory device 20.
The number of pins of the first memory 21 and the number of pins of the second memory 22 may be several, and may be set according to practical application requirements. In FIG. 3, the pins of the first memory 21 and the pins of the second memory 22 are illustrated as I/O0-I/O7.
Wherein in some other embodiments the memory control chip 23 may be an application specific integrated circuit coupled to the printed circuit board.
In some other embodiments, the storage device 20 may further include more than two memories, so as to expand the memory of the storage device 20.
In the prior art, when the first memory and the second memory are respectively located at two sides of the printed circuit board, the pin sequence of the first memory and the pin sequence of the second memory are opposite, and in order to match the pin numbers, the connection line between the memory control chip and the second memory is necessarily crossed, so that the connection line between the memory control chip and the second memory becomes complicated, the design of the printed circuit board becomes complicated, and the performance of the memory device is affected.
Based on this, the present embodiment provides a memory control chip capable of simplifying a connection line of a memory device.
Fig. 4 is a schematic structural diagram of a memory control chip according to an embodiment of the present invention. As shown in fig. 4, the memory control chip 23 includes an interface circuit 231, a function selection circuit 232, and a controller 233.
The interface circuit 231 is used for connecting with the first memory 21 and the second memory 22, the function selection circuit 232 is connected with the interface circuit 231, and the controller 233 is connected with the interface circuit 231 and the function selection circuit 232, respectively. The function selection circuit 232 is used for selecting an interface function of the interface circuit 231; the controller 233 is used to configure the state of the interface circuit 231 and to control the function selection circuit 232 to select the interface function. By providing the interface circuit 231, the function selection circuit 232, and the controller 233 in the memory control chip 23, function switching can be performed according to the connection mode of the first memory 21 and the second memory 22, so that the first memory 21 and the second memory 22 can be directly connected to the memory control chip 23, and the crossing of connection lines is avoided, thereby simplifying the connection lines of the memory device 20.
The interface circuit 231 includes a data bus 2311 and a pad 2313. Referring to fig. 5, fig. 5 is a schematic diagram illustrating a connection structure of the memory device of fig. 3, wherein a pad 2313 is connected to the first memory 21 and the second memory 22 respectively,
the function selection circuit 232 is connected to the pad 2313 and the data bus 2311, and the controller 233 is connected to the pad 2313 and the data bus 2311.
The controller 233 is connected to the function selection circuit 232 through the data bus 2311, and the controller 233 is specifically configured to configure the state of the pad 2313 and control the function selection circuit 232 to select the interface function of the pad 2313.
Referring to fig. 6, fig. 6 is a schematic structural diagram of the memory controller chip of fig. 4, as shown in fig. 6, the interface circuit 231 further includes a control bus 2312, and the controller 233 is connected to the pad 2313 through the control bus 2312, so as to configure the state of the pad 2313.
In this embodiment, the number of the pins to be inverted of the first memory and the second memory corresponds to the number of the pins to be inverted of the pad, respectively, the number of the pins to be inverted of the first memory and the second memory is equal to the number of the pins to be inverted of the first memory 21 and the number of the pins to be inverted (hereinafter referred to as "pins"), for example, the number of the pins of the first memory 21 is I/O0-I/O7, the number of the pins of the first memory 21 is 8, the number of the pins of the second memory 22 is I/O0-I/O7, the number of the pins of the second memory 22 is 8, the number of the pads 2313 is 8. The pins of the first memory 21 are connected to the control bus 2312 through the bonding pads of the pad 2313, and the pins of the second memory 22 are connected to the control bus 2312 through the bonding pads of the pad 2313. Referring to fig. 5, in the present embodiment, the pins of the first memory 21 and the bonding pads 2313 are respectively and sequentially connected, the pins of the second memory 22 and the bonding pads 2313 are respectively and sequentially connected, and the redefinition of the I/O pins is performed by the memory control chip 23, so that the pins of the first memory 21 are matched one-to-one from the I/O0 to the I/O7 and the pins of the second memory 22 are matched one-to-one from the I/O0 to the I/O7, thereby simplifying the connection lines of the memory device 20.
Of course, in some other embodiments, the pin order of the first memory 21 does not have to be from the I/O0 to the I/O7, and the pin order of the second memory 22 does not have to be from the I/O0 to the I/O7, and may be selected according to the actual situation, as long as the redefinition of the I/O pins by the memory control chip 23 is possible, so that the connection lines are simplified.
Of course, in some other embodiments, the number of pins of the first memory 21 and the number of pins of the second memory 22 may be more than 8, and may be freely set according to actual requirements. For example, the pins of the first memory 21, the pins of the second memory 22 may further include a chip select signal pin CE, a write enable signal pin WE, a read enable signal pin RE, a data latch pin ALE, a code latch pin CLE, and the like.
In the present embodiment, the controller 233 configures the state of the pad 2313 and controls the function selection circuit 232 to select the interface function of the pad 2313, thereby enabling the pin state of the second memory 22 connected to the pad 2313 to match the pin state of the first memory 21 connected to the pad 2313, and simplifying the connection line between the second memory 22 and the pad 2313.
Referring to fig. 4, the function selection circuit 232 includes a first switch tube and a second switch tube. The first switch tube and the second switch tube may be mos tubes, other triacs, or other switch circuits, and in this embodiment, both the first switch tube and the second switch tube are mos tubes, such as mos10, mos20, … … mos17, and mos27 in fig. 4. The first and second switching tubes are connected to the pads 2313, respectively. Optionally, the first switch tube is sequentially connected to the pad 2313, and the second switch tube is sequentially connected to the pad 2313, specifically, as shown in fig. 7, if the first switch tubes such as mos10, mos11, mos12 … mos17 are sequentially connected to the first bonding point, the second bonding point, and the seventh bonding point … …, respectively, the first switch tube and the second switch tube are sequentially connected; the second switch tubes of mos20, mos21, mos22 … mos27 are connected to the eighth pad, the seventh pad, the sixth pad, and the first pad of … … in sequence, respectively, which is the reverse sequence. When the memory control chip 23 is sequentially connected to the first memory 21 and the second memory 22, respectively, if the first switch tube is gated, i.e. mos10, mos11, mos12, mos13 … mos17, the first pin of the first memory 21 is communicated with the first pin of the second memory 22, the second pin of the first memory 21 is communicated with the second pin of the second memory 22, the third pin of the first memory 21 is communicated … … with the third pin of the second memory 22, the eighth pin of the first memory 21 is communicated with the eighth pin of the second memory 22, if the second switch tube is gated, i.e. mos20, mos21, mos22, mos23 … mos27, the first pin of the first memory 21 is communicated with the eighth pin of the second memory 22, the second pin of the first memory 21 is communicated with the seventh pin of the second memory 22, and the third pin of the first memory 21 is communicated with the sixth pin … … of the first memory 21 The pin communicates with a first pin of the second memory 22.
It will be appreciated that in some other embodiments, the first switch tube is connected to the pad 2313 in sequence, and the second switch tube is not connected to the pad 2313 in reverse sequence, for example: the eighth pin of the second switching tube 2313 is connected to the first welding point, and the first to seven pins are sequentially connected to the second to eight welding points.
In this embodiment, the function selection circuit 232 gates the first switch tube or the second switch tube under the control of the controller 233, so as to select the interface function of the pad 2313.
Referring to fig. 4, the controller 233 may be a control processing circuit, and the controller 233 is connected to the data bus 2311, the control bus 2312 and the function selection circuit 232 respectively. By providing the controller 233 to control the interface circuit 231 and the function selection circuit 232, one embodiment of the present embodiment may be as follows: the state of the interface circuit 231 is configured and the control function selection circuit 232 selects the interface function.
The state of the interface circuit 231 may include one or more of a push-pull output, an open-drain output, a multiplexed push-pull output, a pull-up input, a pull-down input, a floating input, and an analog input. The configuration state of the interface circuit 231 may be implemented as follows: the controller 233 configures the state of the pad 2313, so as to configure the states of the pins of the first memory 21 and the pins of the second memory 22, for example, when the memory device 20 needs to read data, the controller 233 configures the state of the pull-down input to the pad 2313, so that the read enable signal pin RE of the first memory 21 and the read enable signal pin RE of the second memory 22 configure the state of the pull-down input, and the memory device 20 can read data.
Specifically, controller 233 includes a status configuration module 2331 and a reverse control module 2332. The status configuration module 2331 is coupled to the interface circuit 231, specifically, the status configuration module 2331 is coupled to the pad 2313 via the control bus 2312, and the status configuration module 2331 is configured to configure the pad 2313. The flip control module 2332 is connected to the function selection circuit 232, and the flip control module 2332 is used to control the function selection circuit 232 to select an interface function.
The control function selection circuit 232 selects an interface function, and the specific implementation may be: the inverse control module 2332 receives the inverse function command and selectively turns on the first switch tube or the second switch tube according to the inverse function command. The inverted function command is a command that can trigger the inverted control module 2332 to select an interface function. For example, the inverted function instruction may be a level signal or the like. For example, the following steps are carried out: if the first switch tube is connected to the pad 2313 in sequence and the second switch tube is connected to the pad 2313 in reverse sequence, after the inversion control module 2332 receives the inversion function command, the second switch tube is selectively turned on according to the inversion function command, so that the pin function of the second memory 22 is inverted; when the disable control module 2332 does not receive the disable function command, the first switch is turned on, so that the pin function of the second memory 22 is not disabled.
In some embodiments, referring back to fig. 6, the memory controller chip 23 further includes a flip function identification module 234. The reverse function identification module 234 is connected to the interface circuit 231 and the controller 233, respectively, and the reverse function identification module 234 is configured to obtain a state of the interface circuit 231 and determine whether the controller 233 triggers a reverse function instruction according to the state of the interface circuit 231.
Specifically, in some embodiments, the flip function identification module 234 may be connected to one of the bonding pads 2313. The inverse function identifying module 234 is further configured to, according to a pin function corresponding to a connected solder point, pull up, pull down, or suspend the pin, and then input a signal to the second memory 22, and if a valid signal can be received, determine that the controller 233 does not trigger an inverse function instruction. For example, if the pin function corresponding to the welding point connected to the inverse function identifying module 234 is CE, and CE is active at low level, the pin is pulled down to input a signal to the welding point, and if the active signal is received, the controller 233 does not trigger the inverse function command.
In this embodiment of the present invention, the inverse function identification module 234 is further configured to: and acquiring the return state of the first memory or the second memory for the specific instruction, and determining whether the controller triggers a reverse function instruction according to the return state. The specific implementation mode can be as follows: a specific instruction is sent to the second memory 22, and if the second memory 22 returns to a correct state, the controller 233 does not trigger the flip function instruction; if the second memory 22 fails to return to the correct state, the controller 233 triggers a flip function command. The specific instruction may be: a reset instruction, a read address instruction, etc. For example: a reset instruction is sent to the second memory 22, and if the second memory 22 is reset, the controller 233 does not trigger the reverse function instruction; if the second memory 22 is not reset, the controller 233 triggers a flip function command.
In the embodiment of the present invention, the inverse position identification module 234 may identify the specific data returned from the memory, for example, the data of 0x01 is fixed in the memory, i.e. 1 is returned on D0 of the memory, and 0 is returned on other Dx, so that when the inverse position is not performed, if the data read on the data bus is 0x01, that indicates that the memory does not need to be inverse position, and if the data read on the data bus is 0x80 (the highest bit is 1), that indicates that the memory needs to be inverse position.
In the present embodiment, the memory control chip 23 configures the state of the interface circuit 231 by providing the interface circuit 231 and the function selection circuit 232, and controls the function selection circuit to select the interface function of the interface circuit 232, so that the pin state of the second memory 22 connected to the interface circuit 231 can be matched with the pin state of the first memory 21 connected to the interface circuit 231, thereby simplifying the connection line between the second memory 22 and the interface circuit 231.
Fig. 8 is a flowchart illustrating an adaptive interface method according to an embodiment of the present invention. The method is applied to the memory control chip in the above embodiment, and as shown in fig. 8, the method includes:
310. configuring the state of an interface circuit of the storage control chip;
the controller 233 configures the pad 2313 of the interface circuit 231 according to the pin of the first memory 21 to which the memory control chip 23 is connected.
320. Judging whether the inversion is needed, if so, sending an inversion function instruction;
the controller 233 determines whether the second memory 22 needs to be inverted, and if so, sends an inverted function command to the function selection circuit 232; if not, the reverse function instruction is not sent.
330. And controlling a function selection circuit of the storage control chip to select the interface function of the interface circuit according to the inverted function instruction.
The controller 233 controls the function selection circuit 232 to select the interface function of the interface circuit 231 according to the inverted function instruction, and specifically, the control function selection circuit 232 controls to selectively turn on the first switch tube or the second switch tube.
It should be noted that, for the technical details not described in detail in the steps 310, 320, and 330 in the embodiments of the present invention, reference may be made to the detailed description of the above embodiments.
In this embodiment, the adaptive interface method controls the function selection circuit of the memory control chip to select the interface function of the interface circuit by sending the inverted function command, and can redefine the pin so that the pin state of the second memory 22 connected to the interface circuit 231 can be matched with the pin state of the first memory 21 connected to the interface circuit 231, thereby simplifying the connection line between the second memory 22 and the interface circuit 231.
Fig. 9 is a schematic structural diagram of an adaptive interface device according to an embodiment of the present invention. The apparatus is applied to the memory control chip in the above embodiment, and as shown in fig. 9, the adaptive apparatus 400 includes a state configuration unit 410, an instruction sending unit 420, and a resetting unit 430.
The state configuration unit 410 is connected to the instruction sending unit 420, and the instruction sending unit 420 is connected to the inverse unit 430. The state configuration unit 410 is used for configuring the state of the interface circuit of the storage control chip; the instruction sending unit 420 is configured to determine whether a reverse setting is required, and if so, send a reverse setting function instruction; the inverse unit 430 is configured to control the function selection circuit of the storage control chip to select the interface function of the interface circuit according to the inverse function instruction.
It should be noted that, because the contents of information interaction, execution process, and the like between the modules in the adaptive interface device in the embodiment of the present invention are based on the same concept as the method embodiment of the present invention, the specific contents are also applicable to the storage device in the embodiment. The respective modules in the embodiments of the present invention can be implemented as separate hardware or software, and the combination of the functions of the respective units can be implemented using separate hardware or software as necessary. For technical details which are not elaborated in the embodiment of the adaptive interface device 400, reference is made to the above-described embodiment.
In this embodiment, the adaptive interface device 400 configures the state of the interface circuit of the memory control chip through the state configuration unit 410, the instruction sending unit 420 determines whether the inversion is required, and if so, sends the inversion function instruction, and then the inversion unit 430 controls the function selection circuit of the memory control chip to select the interface function of the interface circuit according to the inversion function instruction, so that the pin state of the second memory 22 connected to the interface circuit 231 can be matched with the pin state of the first memory 21 connected to the interface circuit 231, thereby simplifying the connection line of the memory device 20.
Embodiments of the present invention provide a computer program product comprising a computer program stored on a non-volatile computer-readable storage medium, the computer program comprising program instructions which, when executed by an electronic device, cause the electronic device to perform the adaptive interface method as described above. For example, the above-described method steps 310 to 330 in fig. 8 are executed to implement the functions of the 410-430 module in fig. 9.
An embodiment of the present invention provides a non-volatile computer-readable storage medium, which stores computer-executable instructions for causing an electronic device to execute the method for controlling a storage device as described above. For example, the above-described method steps 310 to 330 in fig. 8 are executed to implement the functions of the 410-430 module in fig. 9.
The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.
Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a general hardware platform, and certainly can also be implemented by hardware. It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware related to instructions of a computer program, which can be stored in a computer readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; within the idea of the invention, also technical features in the above embodiments or in different embodiments may be combined, steps may be implemented in any order, and there are many other variations of the different aspects of the invention as described above, which are not provided in detail for the sake of brevity; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (9)
1. A memory control chip is connected with a first memory and a second memory, and is characterized in that the first memory and the second memory respectively comprise pins to be inverted, and the memory control chip comprises:
the interface circuit comprises a bonding pad and a data bus, wherein the bonding pad is respectively connected with the first memory and the second memory, and the number of the bonding pad welding points respectively corresponds to the number of pins to be inverted of the first memory and the second memory;
the function selection circuit is respectively connected with the bonding pad and the data bus and is used for selecting the interface function of the bonding pad;
the controller is respectively connected with the bonding pad, the data bus and the function selection circuit, the controller is connected with pins to be inverted of the first memory and the second memory through the bonding pad welding point, and the controller is further used for configuring the state of the bonding pad and controlling the function selection circuit to select the interface function;
the inverted function identification module is respectively connected with the welding point of the bonding pad and the controller and used for acquiring the state of the bonding pad and determining whether the controller triggers an inverted function instruction according to the state of the bonding pad, and when the controller triggers the inverted function instruction, the function selection circuit is controlled to select the bonding pad and the connection sequence of the data bus so as to enable the pin to be inverted of the first memory or the pin to be inverted of the first memory to be inverted.
2. The memory control chip of claim 1, wherein the controller comprises a state configuration module and a flip control module;
the state configuration module is connected with the bonding pad and used for configuring the state of the bonding pad;
the reverse control module is connected with the function selection circuit and is used for controlling the function selection circuit to select the interface function.
3. The memory control chip of claim 2, wherein the function selection circuit comprises a first switch tube and a second switch tube;
one end of the first switch tube and one end of the second switch tube are respectively connected with the welding disc, and the other end of the first switch tube and the other end of the second switch tube are respectively connected with the data bus;
the inversion control module is respectively connected with the first switch tube and the second switch tube, and is specifically used for controlling selective conduction of the first switch tube or the second switch tube.
4. The memory control chip of claim 1, wherein the flip function identification module is specifically configured to:
and the controller is connected with a pad welding point of the interface circuit and determines whether to trigger an inverse function instruction according to a response signal generated by an input signal of the welding point in a preset state.
5. The memory control chip of claim 4, wherein the flip function identification module is further configured to:
and acquiring the return state of the first memory or the second memory for the specific instruction, and determining whether the controller triggers a reverse function instruction according to the return state.
6. The memory control chip of claim 1, the state of the pad comprising one or more of a push-pull output, an open-drain output, a multiplexed push-pull output, a pull-up input, a pull-down input, a float input, an analog input.
7. A memory device comprising a first memory, a second memory, and a memory control chip according to any one of claims 1 to 6.
8. The memory device according to claim 7, wherein the first memory, the second memory and the memory control chip are disposed on a same printed circuit board, and the first memory and the second memory are disposed on two opposite surfaces of the same printed circuit board, respectively.
9. An adaptive interface method applied to the memory control chip according to any one of claims 1 to 6, wherein the method comprises:
configuring the state of a bonding pad of the storage control chip;
judging whether the inversion is needed, if so, sending an inversion function instruction;
and controlling a function selection circuit of the storage control chip to select the connection sequence of the bonding pad and the data bus according to the inverted function instruction so as to invert the pin to be inverted of the first storage or the pin to be inverted of the first storage.
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| CN201810595357.7A CN108986853B (en) | 2018-06-11 | 2018-06-11 | Storage control chip, storage device and self-adaptive interface method |
| PCT/CN2018/105398 WO2019237535A1 (en) | 2018-06-11 | 2018-09-13 | Memory control chip, memory device, and adaptive interface method |
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| CN201810595357.7A CN108986853B (en) | 2018-06-11 | 2018-06-11 | Storage control chip, storage device and self-adaptive interface method |
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| WO2019237535A1 (en) | 2019-12-19 |
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