WO2015196578A1

WO2015196578A1 - Method and apparatus for pin multiplexing

Info

Publication number: WO2015196578A1
Application number: PCT/CN2014/086529
Authority: WO
Inventors: 王大鹏
Original assignee: 深圳市中兴微电子技术有限公司
Priority date: 2014-06-25
Filing date: 2014-09-15
Publication date: 2015-12-30
Also published as: CN105279051A

Abstract

A method and apparatus for pin multiplexing. The method comprises: configuring different pin multiplexing information, and mapping a source pin (21) to a target pin (22), so as to output different signals.

Description

Method and device for realizing pin multiplexing

Technical field

The present invention relates to pin technology in the field of chips, and more particularly to a method and apparatus for implementing pin multiplexing.

Background technique

With the development of chip technologies such as system-on-chip (SoC), advances in semiconductor device packaging technology, and the demand for miniaturization of electronic devices, printed circuit boards (PCBs) in electronic products Design and processing have become more complicated. Specifically, the size of the leads and vias in the PCB is reduced, and the PCB level is increased. On the one hand, the design and debugging of the PCB face a high probability of logic errors, and on the other hand, the signal integrity environment is deteriorated and the positioning fault is difficult. .

With the rapid changes in the market for electronic products, especially consumer electronics, people have put forward more demanding requirements for the development and debugging cycle of prototype products. The well-known integrated circuit chip is designed such that the function of the chip's lead-out pin and the chip's internal function is single and fixed, and the corresponding relationship cannot be changed during the use of the chip. Therefore, when the designer encounters the wrong logic design of the printed circuit board during debugging, since the pin cannot be moved and redefined, the method of cutting the printed circuit board and the flying line is usually modified, such as encountering In some cases, if the cutting trace or flying line cannot be implemented, the logic design can only be modified, and the debugging work can be continued after the printed circuit board is reworked, which causes debugging difficulties and even delays the development cycle; and at the same time, due to the shrinking of the chip package, The line spacing and via aperture of printed circuit boards are getting smaller and smaller. For example, BGA package chips with a pad diameter of 0.2 mm and a pitch of 0.4 mm have appeared in the products currently being sold, and the chip pins are also coming. The more, even if you plan ahead when designing a printed circuit board, but because the chip has too many pins, the printed circuit board is too small, and the chip tube The reason why the foot can't move does not guarantee that the signal on all the pins of the chip can be easily measured when analyzing and locating the printed circuit board. This makes the search signal and measurement signal become faulty when searching and locating the printed circuit board. It is getting more and more difficult.

Summary of the invention

In view of this, the embodiments of the present invention are intended to provide a method and apparatus for implementing pin multiplexing, which can change the single and fixed functional relationship between the chip lead-out pins and the chip, and provide a guarantee for promoting the development and debugging of the printed circuit board.

In order to achieve the above object, the technical solution of the present invention is achieved as follows:

The embodiment of the invention provides a method for implementing pin multiplexing. The method includes: mapping different source pin multiplexing information to map source pins to destination pins to implement output of different signals.

Preferably, the pin multiplexing information includes a pin multiplexed code value; and the configuring different pin multiplexing information includes: configuring a different pin complex by configuring a jumper, and/or a register manner The code value used.

Preferably, the mapping the source pin to the destination pin comprises: reading a code value in the pin multiplexing information; converting the code value into a mapping relationship between the source pin and the destination pin According to the mapping relationship, the source pin is mapped to the destination pin.

Preferably, the method further includes: configuring an output mode of the destination pin.

Preferably, the output mode of the configuration destination pin includes: configuring an output mode of the destination pin by configuring a jumper, and/or a register; the output mode of the destination pin is: a listening mode, or Parallel mode, or alternate mode.

Preferably, the implementing the output of the different signals comprises: outputting different signals according to the mapping relationship and the output mode.

The embodiment of the invention further provides a device for implementing pin multiplexing, the device comprising: a source pin, a pin multiplexing configuration interface, a control logic circuit, and a destination pin; wherein the source pin implements a signal Input; the pin multiplexing configuration interface, configuring different pin multiplexing information; The control logic circuit maps the source pin to the destination pin according to the pin multiplexing information configured by the pin multiplexing configuration interface; the destination pin implements output of different signals.

Preferably, the pin multiplexing information includes a code value of the pin multiplexing; the pin multiplexing configuration interface, and configuring different pin multiplexing codes by configuring a jumper and/or a register manner. value.

Preferably, the device further includes: a control logic circuit switch, the control logic circuit switch, turning on or off the control logic circuit; the control logic circuit, specifically, the control logic circuit switch is turned on When the logic circuit is controlled, the code value in the pin multiplexing information is read, the code value is converted into a mapping relationship between the source pin and the destination pin, and the source pin mapping is performed according to the mapping relationship. Go to the destination pin.

Preferably, the pin multiplexing configuration interface further configures an output mode of the destination pin.

Preferably, the pin multiplexing configuration interface, specifically configuring the output mode of the destination pin by configuring a jumper, and/or a register; the output mode of the destination pin is: a listening mode, or a parallel mode Or alternative mode.

Preferably, the destination pin performs output of different signals according to the mapping relationship and the output mode.

The method and device for implementing pin multiplexing provided by the embodiment of the present invention, by configuring different pin multiplexing information, mapping the source pin to the destination pin to realize output of different signals; thus, in the actual application process, Different pin multiplexing information can be configured according to requirements. Different pin multiplexing information can correspond to different mapping relationships between source pins and destination pins, and the source pins can be mapped to different purposes according to different mapping relationships. The pin is used to realize the output of different signals; thus, the functional relationship between the chip lead-out pin and the chip can be changed according to the actual situation, and the effect of monitoring the signals on all the pins of the chip on a specific pin is realized, thereby saving the printed circuit board. The fault location time and modification period during the development process improve the efficiency of electronic product design using complex chips.

DRAWINGS

1 is a schematic flowchart of an implementation manner of an embodiment of a method for implementing pin multiplexing according to the present invention;

2 is a schematic structural diagram of a first embodiment of a device for implementing pin multiplexing according to the present invention;

3 is a schematic structural diagram of a second embodiment of a device for implementing pin multiplexing according to the present invention;

4 is a schematic structural diagram of a third embodiment of a device for implementing pin multiplexing according to the present invention;

FIG. 5 is a schematic structural diagram of a circuit for implementing pin multiplexing according to the present invention.

detailed description

In the embodiment of the present invention, by configuring different pin multiplexing information, the source pin is mapped to the destination pin to implement output of different signals.

The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

An embodiment of the present invention provides a method for implementing pin multiplexing. As shown in FIG. 1 , FIG. 1 is a schematic flowchart of an implementation manner of a method for implementing pin multiplexing according to the present disclosure. The method includes the following steps:

Step 101: Configure different pin multiplexing information.

In this step, the configured pin multiplexing information includes the code value of the pin multiplexing, and the different pin multiplexing information is configured, that is, the code value of the different pin multiplexing is configured; By configuring the jumpers, and/or the registers, the code values of the different pin multiplexes can be configured. It should be noted that, in the embodiment of the present invention, the manner in which the configuration pins multiplex information is not limited. As mentioned above, in practical applications, the pin multiplexing information may be configured by physical or software, etc. according to application requirements and application scenarios.

Optionally, the manner of configuring the jumper may be implemented by a jumper external to the chip, and the manner of configuring the register may be implemented by a processor inside the chip through software.

Step 102: According to the pin multiplexing information, mapping source pins to destination pins to implement output of different signals;

In this step, since the pin multiplexing information includes the code value of the pin multiplexing, the first First, the code value in the pin multiplexing information needs to be read by the control logic circuit, and the code value is converted into a mapping relationship between the source pin and the destination pin, and then the source pipe is determined according to the mapping relationship. The foot is mapped to the destination pin.

Optionally, the method of the embodiment of the present invention may further configure an output mode of the destination pin. It should be noted that the output mode of the configuration destination pin may be performed before the method according to the embodiment of the present invention is performed. It can also be carried out during the execution of the method of the embodiment of the invention.

Optionally, the output mode of the destination pin can be configured by configuring a jumper, and/or a register. The method for configuring the destination pin output mode is not limited in the embodiment of the present invention. As described above, in actual applications, the pin multiplexing information may be configured by physical or software, etc., according to application requirements and application scenarios.

Optionally, the output mode of the destination pin may include: but is not limited to: a listening mode, or a parallel mode, or an alternate mode; therefore, according to a mapping relationship between the source pin and the destination pin The output mode of the target pin can realize the output of different signals; thus, by pin multiplexing, one pin (source pin) of the chip can be mapped to another pin (destination pin), thereby The functional relationship between the chip's lead-out pin and the chip's single fixed function is changed, which improves the efficiency of finding faults and locating faults during the design and debugging of the printed circuit board, and reduces the time spent in modifying the logic design error of the printed circuit board.

Optionally, in the listening mode, the destination pin is an output of the source pin, and the signal change on the destination pin is consistent with the source pin, but in this case, the destination pin is the source. The output of the pin, therefore, the excitation signal applied to the destination pin cannot be conducted to the source pin;

In the parallel mode, the destination pin and the source pin are in a parallel relationship, that is, the signals on the destination pin and the source pin change synchronously;

In the alternate mode, the source pin and the internal connection of the chip are bypassed by the destination pin, and the destination pin completely replaces the function of the source pin.

It should be noted that for any source pin, by configuring different code values, it can be made The source pin corresponds to different destination pins. For the same destination pin, a plurality of different source pins may be corresponding, that is, the mapping relationship between the source pin and the destination pin may be multiple; For the same code value, the mapping relationship between the source pin and the destination pin is unique. In this case, the output mode of the destination pin is also unique.

The embodiment of the present invention further provides a device for implementing pin multiplexing. As shown in FIG. 2, FIG. 2 is a schematic structural diagram of a first embodiment of a device for implementing pin multiplexing according to the present invention. The device includes: a source pin. 21. A pin multiplexing configuration interface 22, a control logic circuit 23, and a destination pin 24; wherein

The source pin 21 realizes input of a signal;

The pin multiplexing configuration interface 22 configures different pin multiplexing information;

Optionally, the pin multiplexing information includes a code value of the pin multiplexing; the pin multiplexing configuration interface 22, configured by using a jumper, and/or a register, to configure different pin multiplexing. The code value.

The control logic circuit 23 maps the source pin to the destination pin according to the pin multiplexing information configured by the pin multiplexing configuration interface;

Optionally, the device may further include: a control logic circuit switch 25, as shown in FIG. 3, FIG. 3 is a schematic structural diagram of a second embodiment of the device for implementing pin multiplexing, and the control logic circuit switch 25 Turning on or off the control logic circuit;

The control logic circuit 23, when the control logic circuit switch 25 turns on the control logic circuit, reads a code value in the pin multiplexing information, and converts the code value into a source pin and The mapping relationship between the destination pins and the source pins are mapped to the destination pins according to the mapping relationship.

Optionally, the pin multiplexing configuration interface 22 further configures an output mode of the destination pin.

The pin multiplexing configuration interface 22, specifically configuring the output mode of the destination pin by configuring a jumper and/or a register; the output mode of the destination pin may include but is not limited to: Monitor mode, or parallel mode, or alternate mode.

The destination pin 24 realizes output of different signals;

Optionally, the destination pin 24 implements output of different signals according to the mapping relationship and the output mode.

Optionally, the device may further include: a kernel interface 26, as shown in FIG. 4, FIG. 4 is a schematic structural diagram of a third embodiment of the apparatus for implementing pin multiplexing according to the present invention, where the kernel interface 26 implements the The connection between the pin multiplexing device and the chip core.

FIG. 5 is a schematic structural diagram of a circuit for implementing pin multiplexing according to the present invention. As shown in FIG. 5, A is a source pin, B is a destination pin, C is a pin multiplexing configuration interface, and D is a control logic circuit, E To control the logic circuit switch, F is the kernel interface;

Optionally, in the actual application, the source pin A may be a default function pin of the chip, the destination pin B may be an output pin, and the source pin A and the destination pin B may be respectively One or more; input pin multiplexing information through the pin multiplexing configuration interface C, the pin multiplexing information including a pin multiplexed code value; when the control logic circuit switch E is to the control logic circuit When turned on, the code value at the pin multiplexing configuration interface C is read by the control logic circuit D, and the code value is converted into a mapping relationship between the source pin A and the destination pin B; the kernel interface F can be connected to the internal processor of the chip. By configuring the jumper and/or register, the mapping relationship between the destination pin B and the kernel interface F can also be changed, so that the chip can be monitored through the destination pin B. The mapping between the source pin A and the destination pin B may be many-to-many, and the mapping relationship between the destination pin B and the interface F of the chip core may also be It is many to many.

It should be noted that the source pin and the destination pin described in the embodiments of the present invention are only used for distinguishing, and do not constitute a limitation of the present invention.

The method for implementing pin multiplexing described in the embodiment of the present invention can also be stored in a computer readable if it is implemented in the form of a software function module and sold or used as an independent product. In the storage medium. Based on such understanding, those skilled in the art will appreciate that embodiments of the present application can be provided as a method, system, or computer program product. Thus, the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment in combination of software and hardware. Moreover, the application can take the form of a computer program product embodied on one or more computer-usable storage media containing computer usable program code, including but not limited to a USB flash drive, a mobile hard drive, a read only memory ( ROM, Read-Only Memory), disk storage, CD-ROM, optical storage, etc.

The present application is described in terms of flowcharts and/or block diagrams of methods, apparatuses, and computer program products according to embodiments of the present application. It will be understood that each flow and/or block of the flowchart illustrations and/or FIG. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing device to produce a machine for the execution of instructions for execution by a processor of a computer or other programmable data processing device. Means for implementing the functions specified in one or more of the flow or in a block or blocks of the flow chart.

The computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device. The apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.

These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device. The instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

Correspondingly, an embodiment of the present invention further provides a computer storage medium, where a calculation is stored A computer program for performing the method of implementing pin multiplexing as described in the method embodiments of the present invention.

The above is only the preferred embodiment of the present invention and is not intended to limit the scope of the present invention.

Claims

A method for implementing pin multiplexing, wherein the method includes:

By configuring different pin multiplexing information, the source pin is mapped to the destination pin to implement different signal outputs.
The method of claim 1, wherein the pin multiplexing information comprises a pin multiplexed code value;

The configuration of different pin multiplexing information includes:

Configure the code values for different pin multiplexes by configuring jumpers, and/or registers.
The method of claim 2 wherein said mapping source pins to destination pins comprises:

Reading a code value in the pin multiplexing information;

Converting the code value into a mapping relationship between a source pin and a destination pin;

According to the mapping relationship, the source pin is mapped to the destination pin.
The method of any of claims 1 to 3, wherein the method further comprises: configuring an output mode of the destination pin.
The method of claim 4, wherein the output mode of the configuration destination pin comprises:

The output mode of the destination pin is configured by configuring a jumper, and/or a register; the output mode of the destination pin is: a listening mode, or a parallel mode, or an alternate mode.
The method of claim 5 wherein said implementing the output of the different signals comprises:

Outputs of different signals are implemented according to the mapping relationship and the output mode.
A device for implementing pin multiplexing, wherein the device includes: a source pin, a pin multiplexing configuration interface, a control logic circuit, and a destination pin; wherein

The source pin realizes input of a signal;

The pin multiplexing configuration interface configures different pin multiplexing information;

The control logic circuit maps the source pin to the destination pin according to the pin multiplexing information configured by the pin multiplexing configuration interface;

The destination pin realizes output of different signals.
The apparatus of claim 7, wherein the pin multiplexing information comprises a pin multiplexed code value;

The pin multiplexes the configuration interface, and configures the code values of different pin multiplexes by configuring jumpers and/or registers.
The device according to claim 8, wherein

The device further includes: a control logic circuit switch, the control logic circuit switch, turning on or off the control logic circuit;

The control logic circuit, when the control logic circuit switch turns on the control logic circuit, reads a code value in the pin multiplexing information, and converts the code value into a source pin and a destination tube The mapping relationship between the pins maps the source pin to the destination pin according to the mapping relationship.
The apparatus according to any one of claims 7 to 9, wherein

The pin multiplexing configuration interface also configures an output mode of the destination pin.
The device according to claim 10, wherein

The pin multiplexing configuration interface, specifically configuring the output mode of the destination pin by configuring a jumper, and/or a register; the output mode of the destination pin is: a listening mode, or a parallel mode, or an alternative mode.
The apparatus according to claim 11, wherein said destination pin, in accordance with said mapping relationship and said output mode, achieve output of different signals.