WO2013091516A1

WO2013091516A1 - Earphone interface and gpio interface multiplexing circuit structure

Info

Publication number: WO2013091516A1
Application number: PCT/CN2012/086745
Authority: WO
Inventors: 奚剑雄; 陈锋
Original assignee: 杭州硅星科技有限公司
Priority date: 2011-12-20
Filing date: 2012-12-17
Publication date: 2013-06-27
Also published as: CN102427569A

Abstract

The present invention provides an earphone interface and GPIO interface multiplexing circuit structure. A host baseband or a host audio codec comprises a low-dropout linear voltage stabilizer, a programmable gain amplifier, a first power amplifier, a second power amplifier, and a grounding terminal. An output end of the low-dropout linear voltage stabilizer, an input end of the programmable gain amplifier, and a first universal input/output interface are connected in parallel and then connected to a microphone interface. The grounding terminal of the host baseband is connected to a grounding interface. An output end of the first power amplifier and a second universal input/output interface are connected in parallel and then connected to a left-channel earphone interface. An output end of the second power amplifier and a third universal input/output interface are connected in parallel and then connected to a right-channel earphone interface. The earphone interface and GPIO interface multiplexing circuit structure of the present invention can implement the connection between a host and an earphone device, and further implement the connection between the host and a data interface device, thereby extending the functions of the earphone interface.

Description

Headset interface and GPIO interface multiplexing circuit structure

Technical field

The invention relates to a muzzle interface and a GPIO interface multiplexing circuit structure.

Background technique

Headsets are extremely versatile, so there are headsets on many devices. The prior art earphone interface only serves as a bridge between the headset device and the audio codec, baseband or processor, etc. Therefore, the prior art headset interface can only implement the connection between the host and the headset device.

Summary of the invention

It is an object of the present invention to provide a multiplexed circuit structure of a headset interface and a GPIO interface, which can be configured as either a headset interface or a GPIO interface.

In order to achieve the above object, the present invention provides a headset circuit and a universal input/output interface multiplexing circuit structure, including: a host baseband or host audio codec, a first universal input/output interface, a second universal input/output interface, and a third Universal input/output interface, microphone interface, left channel headphone jack, right channel headphone jack and grounding port, the host baseband or host audio codec includes a low dropout linear regulator, a programmable gain amplifier, a first power amplifier a second power amplifier and a ground terminal; the output end of the low-dropout linear regulator is connected to the microphone interface after being connected to the first resistor, and the microphone interface is connected to the first capacitor and the input of the programmable gain amplifier End connection, the first universal input/output interface is connected to the microphone interface; the ground end of the host baseband or the host audio codec is connected to the grounding port; the output end of the first power amplifier and the a left channel headphone interface connection, the second universal input/output interface and the Interface channel headphones; the output of the second power amplifier is connected to the headphone jack right channel, the third general-purpose input-output interface with the earphone interface of the right channel.

The above-mentioned headset interface and the universal input/output interface multiplexing circuit structure, wherein the control end of the low dropout linear regulator is connected to the host register, and the working state of the low voltage difference linear regulator is controlled by the host register The input terminal is connected to a voltage transmitted from the host, and the voltage transmitted from the host is regulated by the low-dropout linear regulator to output a microphone bias voltage.

The above-mentioned headset interface and the universal input/output interface multiplexing circuit structure, wherein the control end of the programmable gain amplifier is connected to the host register, and the working state is controlled by the host register, The output of the programmable gain amplifier is coupled to an analog to digital converter of the host.

The above-mentioned headset interface and the universal input/output interface multiplexing circuit structure, wherein the control end of the first power amplifier is connected to the host register, and the working state is controlled by the host register, and the input end of the first power amplifier and the host Digital to analog converter connection.

The above-mentioned headset interface and the universal input/output interface multiplexing circuit structure, wherein the control end of the second power amplifier is connected to the host register, and the working state is controlled by the host register, and the input end of the second power amplifier and the host Digital to analog converter connection.

The above-mentioned headset interface and the universal input/output interface multiplexing circuit structure, wherein the first universal input/output interface, the second universal input/output interface, and the third universal input/output interface are respectively connected to the host register, and the host register is Control whether it is either an input state or an output state.

The above-mentioned headset interface and the universal input/output interface multiplexing circuit structure, wherein the input state is a floating input, a weak pull-up input or a weak pull-down input.

The above-mentioned headset interface and the universal input/output interface multiplexing circuit structure, wherein the output end of the first power amplifier is connected to the left channel headphone interface after being connected to a capacitor, and the output end of the second power amplifier is connected to a capacitor And connected to the right channel earphone interface, the microphone is connected between the microphone interface and the grounding port, the left earphone is connected between the left channel earphone interface and the grounding port, and the right earphone is connected to the right channel. Between the earphone interface and the grounding port, the low dropout linear regulator, the programmable gain amplifier, the first power amplifier and the second power amplifier are both turned on, the first universal input/output interface, the second universal input/output interface, and The third general purpose input and output interface is configured as a floating input.

The above-mentioned headset interface and the universal input/output interface multiplexing circuit structure, wherein the output end of the first power amplifier is connected to the left channel headphone interface after being connected to a capacitor, and the output end of the second power amplifier is connected to a capacitor After being connected to the right channel earphone interface, the low dropout linear regulator, the programmable gain amplifier, the first power amplifier and the second power amplifier are both disconnected, by the first universal input/output interface, The configuration of the two general purpose input and output interfaces and the third general purpose input and output interface form a bus.

The above-mentioned headset interface and the universal input/output interface multiplexing circuit structure, wherein the output end of the first power amplifier is connected to the left channel headphone interface after being connected to a capacitor, and the output end of the second power amplifier is connected to a capacitor Connecting to the right channel earphone interface, at the microphone interface a resistor is connected to the left channel earphone interface, and a resistor is connected between the left channel earphone interface and the right channel earphone interface; the low dropout linear regulator, a programmable gain amplifier, Disconnecting the first power input amplifier and the second power amplifier; configuring the first universal input/output interface as a data line of an I2C interface, and configuring the second universal input/output interface as a power line of an I2C interface, The third general-purpose input/output interface is configured as a clock line of the I2C interface.

The above-mentioned headset interface and the universal input/output interface multiplexing circuit structure, wherein the output end of the first power amplifier is connected to the left channel headphone interface after being connected to a capacitor, and the output end of the second power amplifier is connected to a capacitor Connecting to the right channel earphone interface, connecting a resistor between the microphone interface and the left channel earphone interface, and connecting a connection between the left channel earphone interface and the right channel earphone interface a low-dropout linear regulator, a programmable gain amplifier, a first power amplifier, and a second power amplifier are both disconnected; configuring the first general-purpose input/output interface as a data line of a two-wire interface, The second universal input/output interface is configured as a power line of the two-wire interface, and the third universal input/output interface is configured as a clock line of the two-wire interface.

The above-mentioned headset interface and the universal input/output interface multiplexing circuit structure, wherein the output end of the first power amplifier is connected to the left channel headphone interface after being connected to a capacitor, and the output end of the second power amplifier is connected to a capacitor Connecting to the right channel earphone interface, connecting a resistor between the microphone interface and the left channel earphone interface, and connecting a connection between the left channel earphone interface and the right channel earphone interface a low-dropout linear regulator, a programmable gain amplifier, a first power amplifier, and a second power amplifier are both disconnected; configuring the first general-purpose input/output interface as a USB interface positive differential data line (D+) Configuring the second universal input/output interface as a power line of the USB interface, and configuring the third universal input/output interface as a negative differential data line of the USB interface (D-1)

The headset interface and the GPIO interface multiplexing circuit structure of the present invention can be configured as a headset interface or a GPIO interface, which expands the functions of the headset interface.

DRAWINGS

The headset interface and GPIO interface multiplexing circuit structure of the present invention are given by the following embodiments and the accompanying drawings.

1 is a schematic diagram showing the structure of a multiplexer circuit of a headset interface and a GPIO interface of the present invention.

2 is a schematic diagram of a structure of a multiplexing circuit of the present invention configured as a conventional headset interface. 3 is a schematic diagram of a multiplexing circuit structure of the present invention configured as a GPIO general data interface.

4 is a schematic diagram of the structure of the multiplexing circuit of the present invention configured as an I2C interface.

FIG. 5 is a schematic diagram of the structure of the multiplexing circuit of the present invention configured as a two-wire interface.

detailed description

The headset interface and GPIO interface multiplexing circuit structure of the present invention will be further described in detail below with reference to Figs.

Referring to FIG. 1, the multiplex interface structure of the headset interface and the GPIO interface of the present invention includes a host baseband, a first general input/output (GPIO) interface GPIO1, a second universal input/output interface GPI02, and a third universal input/output interface. GPI03, microphone interface MIC, left channel headphone interface HPL, right channel headphone interface HPR and grounding port GND, the host baseband includes a low dropout linear regulator LDO, a programmable gain amplifier PGA, a first power amplifier PA1, Two power amplifiers PA2 and ground GND1;

The host baseband may also be a host audio codec, and the structure of the host audio codec is the same as that of the host baseband;

The output end 11 of the low-dropout linear regulator LDO is connected to the microphone interface MIC after being connected to the first resistor R1, and the microphone interface MIC is connected to the first capacitor C1 and the input end 21 of the programmable gain amplifier PGA. Connecting, the first universal input/output interface GPI01 is connected to the microphone interface MIC;

The grounding terminal GND1 of the baseband of the host is connected to the grounding port GND;

The output end 31 of the first power amplifier PA1 is connected to the left channel headphone interface HPL, and the second universal input/output interface GPI02 is connected to the left channel headphone interface HPL;

An output 41 of the second power amplifier PA2 is connected to the right channel headphone interface HPR, and the third universal input/output interface GPI03 is connected to the right channel headphone interface HPR.

The control terminal 12 of the low dropout linear regulator LDO is connected to a host register (not shown in FIG. 1), and the first control signal SHD_BIAS sent by the host register controls the low dropout linear regulator LDO For the convenience of description, the low-dropout linear regulator LDO is turned off when the first control signal SHD_BIAS is at a high level, and the output terminal 11 of the low-dropout linear regulator LDO is simultaneously When the first control signal SHD_BIAS is at a low level, the low dropout linear regulator LDO is turned on, from the low dropout linear regulator The voltage VDD input to the input terminal 13 of the LDO is regulated by the low-dropout linear regulator LDO, and output through the output terminal 11 of the low-dropout linear regulator LDO to obtain a microphone bias voltage MIC BIASo.

The control terminal 22 of the programmable gain amplifier PGA is connected to the host register, and the second control signal SHD_MIC sent by the host register controls an operating state of the programmable gain amplifier PGA, the programmable gain The output terminal 23 of the amplifier PGA is connected to an analog-to-digital converter (not shown in FIG. 1) of the host. For convenience of explanation, the programmable gain amplifier PGA is turned off assuming that the second control signal SHD_MIC is at a high level. When the second control signal SHD_MIC is at a low level, the programmable gain amplifier PGA is turned on, and the microphone information MICN input from the microphone interface MIC is amplified by the programmable gain amplifier PGA, The output 23 of the programmable gain amplifier PGA is output, and the signal MIC-ADC output from the programmable gain amplifier PGA is input to an analog-to-digital converter of the host.

The control terminal 32 of the first power amplifier PA1 is connected to the host register, and the third control signal SHD_HPL sent by the host register controls an operating state of the first power amplifier PA1, the first power The input terminal 33 of the amplifier PA1 is connected to a digital-to-analog converter (not shown in FIG. 1) of the host. For convenience of explanation, the first power amplifier PA1 is turned off when the third control signal SHD_HPL is at a high level. At the same time, the output terminal 31 of the first power amplifier PA1 is placed in a high impedance state, and when the third control signal SHD_HPL is at a low level, the first power amplifier PA1 is turned on, and the digital-to-analog conversion of the host is performed. The left channel headphone drive signal HPL_DAC transmitted by the device is output through the output terminal 31 of the first power amplifier PA1.

The control terminal 42 of the second power amplifier PA2 is connected to the host register, and the fourth control signal SHD_HPR sent by the host register controls the operating state of the second power amplifier PA2, the second power The input terminal 43 of the amplifier PA2 is connected to the digital-to-analog converter of the host. For convenience of explanation, the second power amplifier PA2 is turned off when the fourth control signal SHD_HPR is at a high level, and the The output terminal 41 of the second power amplifier PA2 is placed in a high impedance state, when the fourth control signal SHD_HPR is at a low level, the second power amplifier PA2 is turned on, and the right sound of the digital-to-analog converter sent by the host The channel headphone drive signal HPR_DAC is output through the output terminal 41 of the second power amplifier PA2.

The first universal input/output interface GPI01, the second universal input/output interface GPI02, and the first The three general-purpose input/output interfaces GPI03 are respectively connected to the host register, and the host register controls whether it is an input state or an output state, and the input state may be a floating input, a weak pull-up input, or a weak pull-down input. The output state can be an NMOS open-drain output, a PMOS open-drain output, and a push-pull output. That is, the host register controls the working state of the corresponding headset interface and the GPIO interface of the baseband/audio codec, and different functions can be obtained through different combinations.

Since the output terminal 11 of the low-dropout linear regulator LDO and the input terminal 21 of the programmable gain amplifier PGA are connected in parallel with the first general-purpose input/output interface GPI01, the microphone interface MIC becomes a microphone interface and a universal input/output interface. The multiplexing interface of the first power amplifier PA1 is connected in parallel with the second universal input/output interface GPI02, so that the left channel headphone interface HPL becomes a left channel headphone interface and a universal input/output interface. The multiplexing interface; the output terminal 41 of the second power amplifier PA2 is connected in parallel with the third universal input/output interface GPI03, so that the right channel headphone interface HPR becomes a complex of the right channel headphone interface and the universal input/output interface. Use the interface.

When the headset interface and the GPIO interface multiplexing circuit structure are configured as a traditional headset interface, the host and the headset can be realized through the microphone interface MIC, the left channel headphone interface HPL, the right channel headphone interface HPR, and the grounding port GND. The connection between the devices, when the headset interface and the GPIO interface multiplexing circuit structure are configured as a universal input/output interface, through the microphone interface MIC, the left channel headphone interface HPL, the right channel headphone interface HPR, and the grounding port GND enables the connection between the host and the data interface device, extending the functionality of the headset interface.

The use of the multiplexed circuit structure of the headset interface and the GPIO interface of the present invention will now be described in detail by way of an embodiment:

Embodiment 1

Referring to FIG. 2, this embodiment configures the headset interface and the GPIO interface multiplexing circuit structure into a conventional headset interface. The output end 31 of the first power amplifier PA1 is connected to the left channel headphone interface HPL after being connected to the second capacitor C2, and the second universal input/output interface GPI02 is connected to the left channel headphone interface HPL; The output terminal 41 of the second power amplifier PA2 is connected to the right channel headphone interface HPR after being connected to the third capacitor C3, and the third universal input/output interface GPI03 is connected to the right channel headphone interface HPR; Between the microphone interface MIC and the grounding port GND, the left earphone 52 is connected to the left channel earphone interface HPL and the grounding port GND The right earphone 53 is connected between the right channel headphone interface HPR and the ground port GND. The first control signal SHD_BIAS, the second control signal SHD_MIC, the third control signal SHD-HPL, and the fourth control signal SHD-HPR sent by the host register are all low level, and correspondingly, the low voltage The differential linear regulator LDO, the programmable gain amplifier PGA, the first power amplifier PA1, and the second power amplifier PA2 are both turned on, the first general-purpose input/output interface GPI01, the second universal input/output interface GPI02, and the third general-purpose input and output. The interface GPI03 is generally configured as a floating input, and is externally embodied as a high impedance state. The first general-purpose input/output interface GPI01 can also be configured as an NMOS open-drain output.

Embodiment 2

Referring to FIG. 3, this embodiment configures the headset interface and the GPIO interface multiplexing circuit structure into a GPIO general data interface. The output end 31 of the first power amplifier PA1 is connected to the left channel headphone interface HPL after being connected to the fourth capacitor C4, and the second universal input/output interface GPI02 is connected to the left channel headphone interface HPL; The output terminal 41 of the second power amplifier PA2 is connected to the right channel headphone interface HPR after being connected to the fifth capacitor C5, and the third universal input/output interface GPI03 is connected to the right channel headphone interface HPR. The first control signal SHD_BIAS, the second control signal SHD_MIC, the third control signal SHD-HPL, and the fourth control signal SHD-HPR sent by the host register are all at a high level, and correspondingly, the low voltage The differential linear regulator LDO, the programmable gain amplifier PGA, the first power amplifier PA1 and the second power amplifier PA2 are both turned off, and externally embodied as a high impedance state, through the first general-purpose input/output interface GPI01, the second universal The configuration of the input/output interface GPI02 and the third general-purpose input/output interface GPI03 form a bus to implement data communication between the host and the data interface device.

Embodiment 3

Referring to FIG. 4, this embodiment configures the headset interface and the GPIO interface multiplexing circuit structure as an I2C interface. The first control signal SHD_BIAS, the second control signal SHD_MIC, the third control signal SHD-HPL, and the fourth control signal SHD-HPR sent by the host register are all at a high level, and correspondingly, the low voltage The differential linear regulator LDO, the programmable gain amplifier PGA, the first power amplifier PA1, and the second power amplifier PA2 are both turned off, and externally embodied as a high-impedance state, and the first general-purpose input/output interface GPIO 1 and the second universal The input and output interface GPI02 and the third general-purpose input/output interface GPI03 form an I2C interface through proper configuration, and the three general-purpose input and output interfaces are configured. When it is possible to rotate, Figure 4 shows only one of the possible configurations. As shown in FIG. 4, the first general-purpose input/output interface GPI01 is configured as a data line SDA of an I2C interface, and the second general-purpose input/output interface GPI02 is configured as a power line VDD of an I2C interface, and the third universal The input/output interface GPI03 is configured as a clock line SCL of the I2C interface; the output end 31 of the first power amplifier PA1 is connected to the left-channel headphone interface HPL after being connected to the sixth capacitor C6, and the second universal input/output interface GPI02 Connected to the left channel headphone interface HPL, the output end 41 of the second power amplifier PA2 is connected to the right channel headphone interface HPR after being connected to the seventh capacitor C7, and the third universal input/output interface GPI03 and the a right channel headphone interface HPR connection, a third resistor R3 is connected between the microphone interface MIC and the left channel headphone interface HPL, and the left channel headphone interface HPL and the right channel headphone interface HPR A second resistor R2 is connected between the first general-purpose input/output interface GPI01 and an NMOS open-drain output according to the I2C protocol, and the second universal input/output interface GPI02 is configured to output a constant "1" to provide power. Three universal input-output interface is configured to GPI03 NMOS open drain output, the data bus can be linked to multiple I2C interface devices 61, the I2C interface device 61 is, for example a gyroscope, an accelerometer, a thermometer, a pressure gauge.

Embodiment 4

Referring to FIG. 5, the embodiment configures the headset interface and the GPIO interface multiplexing circuit structure into a two-wire interface. The first control signal SHD_BIAS, the second control signal SHD_MIC, the third control signal SHD-HPL, and the fourth control signal SHD-HPR sent by the host register are all at a high level, and correspondingly, the low voltage The differential linear regulator LDO, the programmable gain amplifier PGA, the first power amplifier PA1, and the second power amplifier PA2 are both turned off, and externally embodied as a high-impedance state, and the first general-purpose input/output interface GPIO 1 and the second universal The input/output interface GPI02 and the third general-purpose input/output interface GPI03 form a two-wire interface through a suitable configuration. As shown in FIG. 5, the first general-purpose input/output interface GPI01 is configured as a data line SDIN of a two-wire interface, and the The second general-purpose input/output interface GPI02 is configured as a power line VDD of the two-wire interface, and the third general-purpose input/output interface GPI03 is configured as a clock line SCLK of the two-wire interface; the output end 31 of the first power amplifier PA1 is connected to The eight-capacitor C8 is connected to the left-channel headphone interface HPL, and the second universal input-output interface GPI02 is connected to the left-channel headphone interface HPL, the second power amplifier The output terminal 41 of the PA2 is connected to the right channel headphone interface HPR after being connected to the ninth capacitor C9, and the third universal input/output interface GPI03 is connected to the right channel headphone interface HPR, and is connected to the microphone. A fourth resistor R4 is connected between the port MIC and the left channel headphone jack HPL, and a fifth resistor R5 is connected between the left channel headphone jack HPL and the right channel headphone jack HPR according to the two-wire interface protocol. The first general-purpose input/output interface GPI01 is configured as an NMOS open-drain output, the second general-purpose input/output interface GPI02 is configured to be a constant "1" output to provide power, and the third general-purpose input/output interface GPI03 is configured to be an NMOS-on With the leakage output, a plurality of two-wire interface devices 71 can be hung on the data bus.

Embodiment 5

In this embodiment, the headset interface and the GPIO interface multiplexing circuit structure are configured as a USB interface. The output of the first power amplifier is connected to the left channel earphone interface, and the output end of the second power amplifier is connected to the right channel earphone interface, and the microphone is connected to the right channel earphone. A resistor is connected between the interface and the left channel earphone interface, and a resistor is connected between the left channel earphone interface and the right channel earphone interface; the first control signal SHD sent by the host register is The BIAS, the second control signal SHD_MIC, the third control signal SHD-HPL, and the fourth control signal SHD-HPR are all at a high level, and accordingly, the low-dropout linear regulator LDO, the programmable gain amplifier PGA, The first power amplifier PA1 and the second power amplifier PA2 are both turned off and externally embodied as a high impedance state; the first general-purpose input/output interface is configured as a positive differential data line (D+) of the USB interface, and the second universal The input/output interface is configured as a power cable of the USB interface, and the third universal input/output interface is configured as a negative differential data line of the USB interface (D_λ

It will be apparent that those skilled in the art can make various modifications and variations to the invention without departing from the spirit and scope of the invention. Thus, it is intended that the present invention cover the modifications and modifications of the invention

Claims

Rights request

A multiplexer circuit structure for a headset interface and a universal input/output interface, comprising: a host baseband or a host audio codec, a first universal input/output interface, a second universal input/output interface, and a third universal input/output An interface, a microphone interface, a left channel headphone jack, a right channel headphone jack, and a ground port, the host baseband or host audio codec including a low dropout linear regulator, a programmable gain amplifier, a first power amplifier, a second Power amplifier and ground terminal;

The output end of the low-dropout linear regulator is connected to the microphone interface after being connected to the first resistor, and the microphone interface is connected to the first capacitor and connected to the input end of the programmable gain amplifier, the first universal input An output interface is connected to the microphone interface;

a ground end of the host baseband or the host audio codec is connected to the grounding port; an output end of the first power amplifier is connected to the left channel earphone interface, the second universal input/output interface is Left channel headphone jack connection;

An output end of the second power amplifier is connected to the right channel earphone interface, and the third universal input/output interface is connected to the right channel earphone interface.

2. The headset interface and the universal input/output interface multiplexing circuit structure according to claim 1, wherein a control end of the low dropout linear regulator is connected to a host register, and the working state is controlled by the host register. The input end of the low-dropout linear regulator is connected to a voltage transmitted from a host, and the voltage transmitted from the host is regulated by the low-dropout linear regulator to output a microphone bias voltage.

3. The headset interface and the universal input/output interface multiplexing circuit structure according to claim 1, wherein a control end of the programmable gain amplifier is connected to a host register, and the host register controls the working state thereof. The output of the programmable gain amplifier is coupled to an analog to digital converter of the host.

The multiplexer circuit structure of the headset interface and the universal input/output interface according to claim 1, wherein the control end of the first power amplifier is connected to a host register, and the working state of the host is controlled by the host register. The input of the first power amplifier is connected to the digital-to-analog converter of the host.

5. The headset interface and universal input/output interface multiplexing circuit structure according to claim 1, The control terminal of the second power amplifier is connected to a host register, and the working state is controlled by the host register, and the input end of the second power amplifier is connected to a digital-to-analog converter of the host.

The multiplexer circuit structure of the headset interface and the universal input/output interface according to claim 1, wherein the first universal input/output interface, the second universal input/output interface, and the third universal input/output interface are respectively The host register is connected, and the host register controls whether it is an input state or an output state.

The multiplexer circuit structure of the headset interface and the universal input/output interface according to claim 1, wherein the output end of the first power amplifier is connected to the left channel earphone interface after being connected to a capacitor, The output of the second power amplifier is connected to the right channel headphone interface, the microphone is connected between the microphone interface and the ground port, and the left earphone is connected between the left channel headphone interface and the grounding port. The right earphone is connected between the right channel earphone interface and the grounding port, and the low dropout linear regulator, the programmable gain amplifier, the first power amplifier and the second power amplifier are both turned on, the first universal input The output interface, the second general purpose input and output interface, and the third general purpose input and output interface are all configured as floating inputs.

The multiplexer circuit structure of the headset interface and the universal input/output interface according to claim 1, wherein the output end of the first power amplifier is connected to the left channel earphone interface after being connected to a capacitor, The output of the second power amplifier is connected to the right channel headphone and connected to the right channel headphone. The low dropout linear regulator, the programmable gain amplifier, the first power amplifier and the second power amplifier are all disconnected. The configuration of the first general purpose input output interface, the second universal input output interface, and the third general purpose input and output interface form a bus.

The multiplexer circuit structure of the headset interface and the universal input/output interface according to claim 1, wherein the output end of the first power amplifier is connected to the left channel earphone interface after being connected to a capacitor, The output of the second power amplifier is connected to the right channel earphone interface, and a resistor is connected between the microphone interface and the left channel earphone interface, and the left channel earphone interface Connecting a resistor between the right channel headphone interface; the low dropout linear regulator, the programmable gain amplifier, the first power amplifier and the second power amplifier are both disconnected; configuring the first universal input/output interface to a data line of the I2C interface, the second universal input/output interface is configured as a power line of the I2C interface, and the third universal input/output interface is configured as an I2C interface. The clock line of the mouth.

The multiplexer circuit structure of the headset interface and the universal input/output interface according to claim 1, wherein the output end of the first power amplifier is connected to the left channel earphone interface after being connected to a capacitor, The output of the second power amplifier is connected to the right channel earphone interface, and a resistor is connected between the microphone interface and the left channel earphone interface, and the left channel earphone interface Connecting a resistor between the right channel headphone interface; the low dropout linear regulator, the programmable gain amplifier, the first power amplifier and the second power amplifier are both disconnected; configuring the first universal input/output interface to The data line of the two-wire interface configures the second universal input/output interface as a power line of the two-wire interface, and configures the third universal input/output interface as a clock line of the two-wire interface.

The multiplexer circuit structure of the headset interface and the universal input/output interface according to claim 1, wherein the output end of the first power amplifier is connected to the left channel headphone interface, and the The output of the second power amplifier is connected to the right channel earphone interface, and a resistor is connected between the microphone interface and the left channel earphone interface, and the left channel earphone interface is connected to the Connecting a resistor between the right channel headphone interface; the low dropout linear regulator, the programmable gain amplifier, the first power amplifier and the second power amplifier are both disconnected; configuring the first universal input/output interface as a USB A positive differential data line of the interface, the second universal input/output interface is configured as a power line of the USB interface, and the third universal input/output interface is configured as a negative differential data line of the USB interface.