CN102427569A - Headset interface and GPIO (General Purpose Input/Output) interface multiplex circuit structure - Google Patents
Headset interface and GPIO (General Purpose Input/Output) interface multiplex circuit structure Download PDFInfo
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- CN102427569A CN102427569A CN201110428776XA CN201110428776A CN102427569A CN 102427569 A CN102427569 A CN 102427569A CN 201110428776X A CN201110428776X A CN 201110428776XA CN 201110428776 A CN201110428776 A CN 201110428776A CN 102427569 A CN102427569 A CN 102427569A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
- H04R5/00—Stereophonic arrangements
- H04R5/04—Circuit arrangements, e.g. for selective connection of amplifier inputs/outputs to loudspeakers, for loudspeaker detection, or for adaptation of settings to personal preferences or hearing impairments
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
- H04R5/00—Stereophonic arrangements
- H04R5/033—Headphones for stereophonic communication
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Abstract
The invention provides a headset interface and GPIO (General Purpose Input/Output) interface multiplex circuit structure. A host base band or host audio codec comprises a low dropout linear regulator, a programmable grain amplifier, a first power amplifier, a second power amplifier and a grounding terminal, wherein the output end of the low dropout linear regulator, the input end of the programmable grain amplifier and a first general input/output interface are connected in parallel and then the paralleled integrated body is connected with a microphone interface; the grounding terminal of the host base band is connected with a grounding port; the output end of the first power amplifier is connected with a second general input/output interface in parallel and is then is connected with a left channel headset interface; and the output end of the second power amplifier is connected with a third general input/output interface in parallel and is then is connected with a right channel headset interface. According to the headset interface and GPIO interface multiplex circuit structure disclosed by the invention, the connection between the host and headset equipment can be realized, the connection between the host and data interface equipment can be realized and the functions of the headset interface are expanded.
Description
Technical field
The present invention relates to a kind of headset interface and GPIO interface duplex circuit structure.
Background technology
The application of headset is extremely extensive, therefore on a lot of equipment, the headset interface is arranged all.The headset interface only serves as the bridge that is connected of headset equipment and audio codec, base band or processor etc. in the prior art, and therefore, the headset interface of prior art can only be realized being connected of main frame and headset equipment.
Summary of the invention
The object of the present invention is to provide a kind of headset interface and GPIO interface duplex circuit structure, the both configurable one-tenth headset of this circuit structure interface, configurable again one-tenth GPIO interface.
In order to reach above-mentioned purpose; The present invention provides a kind of headset interface and universal input/output interface multiplex circuit structure; Comprise: main frame base band or main frame audio codec, first universal input/output interface, second universal input/output interface, the 3rd general input/output interface, microphone interface, L channel earphone interface, R channel earphone interface and ground connection mouth, said main frame base band or main frame audio codec comprise low pressure difference linear voltage regulator, programmable gain amplifier, first power amplifier, second power amplifier and earth terminal; The output of said low pressure difference linear voltage regulator is connected with said microphone interface after connecting first resistance; Said microphone interface is connected with the input of said programmable gain amplifier after connecting first electric capacity, and said first universal input/output interface is connected with said microphone interface; The earth terminal of said main frame base band or main frame audio codec is connected with said ground connection mouth; The output of said first power amplifier is connected with said L channel earphone interface, and said second universal input/output interface is connected with said L channel earphone interface; The output of said second power amplifier is connected with said R channel earphone interface, and the said the 3rd general input/output interface is connected with said R channel earphone interface.
Above-mentioned headset interface and universal input/output interface multiplex circuit structure; Wherein, The control end of said low pressure difference linear voltage regulator is connected with host register; By said its operating state of host register control, the input of said low pressure difference linear voltage regulator connects the voltage that main frame sends, and the voltage that this main frame sends is exported microphone bias voltage after said low pressure difference linear voltage regulator voltage stabilizing.
Above-mentioned headset interface and universal input/output interface multiplex circuit structure; Wherein, The control end of said programmable gain amplifier is connected with host register, and by said its operating state of host register control, the output of said programmable gain amplifier is connected with the analog to digital converter of main frame.
Above-mentioned headset interface and universal input/output interface multiplex circuit structure; Wherein, The control end of said first power amplifier is connected with host register, and by said its operating state of host register control, the input of said first power amplifier is connected with the digital to analog converter of main frame.
Above-mentioned headset interface and universal input/output interface multiplex circuit structure; Wherein, The control end of said second power amplifier is connected with host register, and by said its operating state of host register control, the input of said second power amplifier is connected with the digital to analog converter of main frame.
Above-mentioned headset interface and universal input/output interface multiplex circuit structure; Wherein, Said first universal input/output interface, second universal input/output interface and the 3rd general input/output interface are connected with said host register respectively, by the control of said host register itself or be input state or be output state.
Above-mentioned headset interface and universal input/output interface multiplex circuit structure, wherein, said input state draw for floating empty input, on weak input or a little less than drop-down input.
Above-mentioned headset interface and universal input/output interface multiplex circuit structure; Wherein, The output of said first power amplifier is connected with said L channel earphone interface after connecting an electric capacity; The output of said second power amplifier is connected with said R channel earphone interface after connecting an electric capacity; Microphone is connected between said microphone interface and the ground connection mouth, and left earphone is connected between said L channel earphone interface and the ground connection mouth, and right earphone is connected between said R channel earphone interface and the ground connection mouth; Said low pressure difference linear voltage regulator, programmable gain amplifier, first power amplifier and second power amplifier are all opened, and said first universal input/output interface, second universal input/output interface and the 3rd general input/output interface all are configured to floating empty input.
Above-mentioned headset interface and universal input/output interface multiplex circuit structure; Wherein, The output of said first power amplifier is connected with said L channel earphone interface after connecting an electric capacity; The output of said second power amplifier is connected with said R channel earphone interface after connecting an electric capacity; Said low pressure difference linear voltage regulator, programmable gain amplifier, first power amplifier and second power amplifier all break off, and form bus through the configuration to said first universal input/output interface, second universal input/output interface and the 3rd general input/output interface.
Above-mentioned headset interface and universal input/output interface multiplex circuit structure; Wherein, The output of said first power amplifier is connected with said L channel earphone interface after connecting an electric capacity; The output of said second power amplifier is connected with said R channel earphone interface after connecting an electric capacity, between said microphone interface and said L channel earphone interface, is connected a resistance, between said L channel earphone interface and said R channel earphone interface, is connected a resistance; Said low pressure difference linear voltage regulator, programmable gain amplifier, first power amplifier and second power amplifier all break off; Said first universal input/output interface is configured to the data wire of I2C interface, said second universal input/output interface is configured to the power line of I2C interface, the said the 3rd general input/output interface is configured to the clock line of I2C interface.
Above-mentioned headset interface and universal input/output interface multiplex circuit structure; Wherein, The output of said first power amplifier is connected with said L channel earphone interface after connecting an electric capacity; The output of said second power amplifier is connected with said R channel earphone interface after connecting an electric capacity, between said microphone interface and said L channel earphone interface, is connected a resistance, between said L channel earphone interface and said R channel earphone interface, is connected a resistance; Said low pressure difference linear voltage regulator, programmable gain amplifier, first power amplifier and second power amplifier all break off; Said first universal input/output interface is configured to the data wire of two line interfaces, said second universal input/output interface is configured to the power line of two line interfaces, the said the 3rd general input/output interface is configured to the clock line of two line interfaces.
Above-mentioned headset interface and universal input/output interface multiplex circuit structure; Wherein, The output of said first power amplifier is connected with said L channel earphone interface after connecting an electric capacity; The output of said second power amplifier is connected with said R channel earphone interface after connecting an electric capacity, between said microphone interface and said L channel earphone interface, is connected a resistance, between said L channel earphone interface and said R channel earphone interface, is connected a resistance; Said low pressure difference linear voltage regulator, programmable gain amplifier, first power amplifier and second power amplifier all break off; Said first universal input/output interface is configured to the positive differential data wire (D+) of USB interface; Said second universal input/output interface is configured to the power line of USB interface, the said the 3rd general input/output interface is configured to the negative differential data line (D-) of USB interface.
Headset interface of the present invention and GPIO interface duplex circuit structure be both configurable to become the headset interface, and configurable again one-tenth GPIO interface has been expanded the function of headset interface.
Description of drawings
Headset interface of the present invention and GPIO interface duplex circuit structure are provided by following embodiment and accompanying drawing.
Fig. 1 is the sketch map of headset interface of the present invention and GPIO interface duplex circuit structure.
Fig. 2 is the sketch map that multiplex circuit structural arrangements of the present invention becomes traditional headset interface.
Fig. 3 is the sketch map that multiplex circuit structural arrangements of the present invention becomes the GPIO universal data interface.
Fig. 4 is the sketch map that multiplex circuit structural arrangements of the present invention becomes the I2C interface.
Fig. 5 is the sketch map that multiplex circuit structural arrangements of the present invention becomes two line interfaces.
Embodiment
Below will combine Fig. 1～Fig. 5 that headset interface of the present invention and GPIO interface duplex circuit structure are done further to describe in detail.
Referring to Fig. 1; Headset interface of the present invention and GPIO interface duplex circuit structure comprise main frame base band, the first general input and output (General Purpose Input Output; GPIO) interface GPIO1, the second universal input/output interface GPIO2, the 3rd general input/output interface GPIO3, microphone interface MIC, L channel earphone interface HPL, R channel earphone interface HPR and ground connection mouth GND, said main frame base band comprises low pressure difference linear voltage regulator LDO, programmable gain amplifier PGA, the first power amplifier PA1, the second power amplifier PA2 and earth terminal GND1;
Above-mentioned main frame base band also can be the main frame audio codec, and the structure of this main frame audio codec is identical with the structure of above-mentioned main frame base band;
The output 11 of said low pressure difference linear voltage regulator LDO connects first resistance R, 1 back and is connected with said microphone interface MIC; Said microphone interface MIC connects first capacitor C, 1 back and is connected with the input 21 of said programmable gain amplifier PGA, and the said first universal input/output interface GPIO1 is connected with said microphone interface MIC;
The earth terminal GND1 of said main frame base band is connected with said ground connection mouth GND;
The output 31 of the said first power amplifier PA1 is connected with said L channel earphone interface HPL, and the said second universal input/output interface GPIO2 is connected with said L channel earphone interface HPL;
The output 41 of the said second power amplifier PA2 is connected with said R channel earphone interface HPR, and the said the 3rd general input/output interface GPIO3 is connected with said R channel earphone interface HPR.
The control end 12 of said low pressure difference linear voltage regulator LDO is connected with host register (not showing among Fig. 1); The first control signal SHD_BIAS that is sent by said host register controls the operating state of said low pressure difference linear voltage regulator LDO, for the ease of explanation, supposes when the said first control signal SHD_BIAS is high level; Said low pressure difference linear voltage regulator LDO breaks off; Simultaneously, the output 11 of said low pressure difference linear voltage regulator LDO is set to high-impedance state, when the said first control signal SHD_BIAS is low level; Said low pressure difference linear voltage regulator LDO opens; After low pressure difference linear voltage regulator LDO voltage stabilizing, output 11 outputs through said low pressure difference linear voltage regulator LDO obtain microphone bias voltage MIC_BIAS from the voltage VDD of the input of said low pressure difference linear voltage regulator LDO 13 inputs.
The control end 22 of said programmable gain amplifier PGA is connected with said host register; The second control signal SHD_MIC that is sent by said host register controls the operating state of said programmable gain amplifier PGA; The output 23 of said programmable gain amplifier PGA is connected with the analog to digital converter (not showing among Fig. 1) of main frame; For the ease of explanation; Suppose when the said second control signal SHD_MIC is high level that said programmable gain amplifier PGA breaks off, when the said second control signal SHD_MIC is low level; Said programmable gain amplifier PGA opens; After said programmable gain amplifier PGA amplified, by output 23 outputs of said programmable gain amplifier PGA, the signal MIC_ADC of said programmable gain amplifier PGA output inputed to the analog to digital converter of said main frame from the microphone information MICIN of said microphone interface MIC input.
The control end 32 of the said first power amplifier PA1 is connected with said host register; The 3rd control signal SHD_HPL that is sent by said host register controls the operating state of the said first power amplifier PA1; The input 33 of the said first power amplifier PA1 is connected with the digital to analog converter (not showing among Fig. 1) of main frame, for the ease of explanation, supposes when said the 3rd control signal SHD_HPL is high level; The said first power amplifier PA1 breaks off; Simultaneously, the output 31 of the said first power amplifier PA1 is set to high-impedance state, when said the 3rd control signal SHD_HPL is low level; The said first power amplifier PA1 opens, and the L channel earphone drive signal HPL_DAC that the digital to analog converter of said main frame sends is through output 31 outputs of the said first power amplifier PA1.
The control end 42 of the said second power amplifier PA2 is connected with said host register; The 4th control signal SHD_HPR that is sent by said host register controls the operating state of the said second power amplifier PA2; The input 43 of the said second power amplifier PA2 is connected with the digital to analog converter of said main frame, for the ease of explanation, supposes when said the 4th control signal SHD_HPR is high level; The said second power amplifier PA2 breaks off; Simultaneously, the output 41 of the said second power amplifier PA2 is set to high-impedance state, when said the 4th control signal SHD_HPR is low level; The said second power amplifier PA2 opens, and the R channel earphone drive signal HPR_DAC that the digital to analog converter of said main frame sends is through output 41 outputs of the said second power amplifier PA2.
The said first universal input/output interface GPIO1, the second universal input/output interface GPIO2 and the 3rd general input/output interface GPIO3 are connected with said host register respectively; By the control of said host register itself or be input state or be output state; Said input state can be floating empty input, draw input on weak, a little less than drop-down input, said output state can be that the NMOS pipe is opened output with Louing, PMOS manages to open Lou and exports, recommends output.Be the operating state of said host register control corresponding headset interface of base band/audio codec and GPIO interface,, can obtain difference in functionality through different combinations.
Because the input 21 of the output 11 of said low pressure difference linear voltage regulator LDO, programmable gain amplifier PGA is parallelly connected with the first universal input/output interface GPIO1; Therefore, said microphone interface MIC just becomes the multiplex interface of microphone interface and universal input/output interface; Because the output 31 of the said first power amplifier PA1 is parallelly connected with the second universal input/output interface GPIO2, therefore, said L channel earphone interface HPL just becomes the multiplex interface of L channel earphone interface and universal input/output interface; Because the output 41 of the said second power amplifier PA2 is parallelly connected with the 3rd general input/output interface GPIO3, therefore, said R channel earphone interface HPR just becomes the multiplex interface of R channel earphone interface and universal input/output interface.
When said headset interface and GPIO interface duplex circuit structure are configured to traditional headset interface; Can realize being connected between main frame and the headset equipment through said microphone interface MIC, L channel earphone interface HPL, R channel earphone interface HPR and ground connection mouth GND; When said headset interface and GPIO interface duplex circuit structure are configured to universal input/output interface; Can realize being connected between main frame and the data interface unit through said microphone interface MIC, L channel earphone interface HPL, R channel earphone interface HPR and ground connection mouth GND, expand the function of headset interface.
Specify the use of headset interface of the present invention and GPIO interface duplex circuit structure through embodiment at present:
Embodiment one
Referring to Fig. 2, this embodiment is configured to traditional headset interface with said headset interface and GPIO interface duplex circuit structure.The output 31 of the said first power amplifier PA1 connects second capacitor C, 2 backs and is connected with said L channel earphone interface HPL, and the said second universal input/output interface GPIO2 is connected with said L channel earphone interface HPL; The output 41 of the said second power amplifier PA2 connects the 3rd capacitor C 3 backs and is connected with said R channel earphone interface HPR, and the said the 3rd general input/output interface GPIO3 is connected with said R channel earphone interface HPR; Microphone 51 is connected between said microphone interface MIC and the ground connection mouth GND, and left earphone 52 is connected between said L channel earphone interface HPL and the ground connection mouth GND, and right earphone 53 is connected between said R channel earphone interface HPR and the ground connection mouth GND.The first control signal SHD_BIAS that said host register is sent, the second control signal SHD_MIC, the 3rd control signal SHD_HPL, the 4th control signal SHD_HPR are low level; Correspondingly; Said low pressure difference linear voltage regulator LDO, programmable gain amplifier PGA, the first power amplifier PA1 and the second power amplifier PA2 all open; The said first universal input/output interface GPIO1, the second universal input/output interface GPIO2 and the 3rd general input/output interface GPIO3 generally are configured to floating empty input; Externally be presented as high-impedance state, also can the said first universal input/output interface GPIO1 be configured to NMOS and open Lou output.
Embodiment two
Referring to Fig. 3, this embodiment is configured to the GPIO universal data interface with said headset interface and GPIO interface duplex circuit structure.The output 31 of the said first power amplifier PA1 connects the 4th capacitor C 4 backs and is connected with said L channel earphone interface HPL, and the said second universal input/output interface GPIO2 is connected with said L channel earphone interface HPL; The output 41 of the said second power amplifier PA2 connects the 5th capacitor C 5 backs and is connected with said R channel earphone interface HPR, and the said the 3rd general input/output interface GPIO3 is connected with said R channel earphone interface HPR.The first control signal SHD_BIAS that said host register is sent, the second control signal SHD_MIC, the 3rd control signal SHD_HPL, the 4th control signal SHD_HPR are high level; Correspondingly; Said low pressure difference linear voltage regulator LDO, programmable gain amplifier PGA, the first power amplifier PA1 and the second power amplifier PA2 all break off; Externally be presented as high-impedance state; Configuration through to the said first universal input/output interface GPIO1, the second universal input/output interface GPIO2 and the 3rd general input/output interface GPIO3 forms bus, realizes the data communication between main frame and the data interface unit.
Embodiment three
Referring to Fig. 4, this embodiment is configured to the I2C interface with said headset interface and GPIO interface duplex circuit structure.The first control signal SHD_BIAS that said host register is sent, the second control signal SHD_MIC, the 3rd control signal SHD_HPL, the 4th control signal SHD_HPR are high level; Correspondingly; Said low pressure difference linear voltage regulator LDO, programmable gain amplifier PGA, the first power amplifier PA1 and the second power amplifier PA2 all break off; Externally be presented as high-impedance state; And the said first universal input/output interface GPIO1, the second universal input/output interface GPIO2 and the 3rd general input/output interface GPIO3 form the I2C interface through suitable configuration; When these three universal input/output interfaces of configuration, can rotate, Fig. 4 has only shown wherein a kind of possible configuration.As shown in Figure 4; The said first universal input/output interface GPIO1 is configured to the data wire SDA of I2C interface; The said second universal input/output interface GPIO2 is configured to the power line VDD of I2C interface, the said the 3rd general input/output interface GPIO3 is configured to the clock line SCL of I2C interface; The output 31 of the said first power amplifier PA1 connects the 6th capacitor C 6 backs and is connected with said L channel earphone interface HPL; The said second universal input/output interface GPIO2 is connected with said L channel earphone interface HPL; The output 41 of the said second power amplifier PA2 connects the 7th capacitor C 7 backs and is connected with said R channel earphone interface HPR; The said the 3rd general input/output interface GPIO3 is connected with said R channel earphone interface HPR; Between said microphone interface MIC and said L channel earphone interface HPL, be connected the 3rd resistance R 3; Between said L channel earphone interface HPL and said R channel earphone interface HPR, be connected second resistance R 2, according to the I2C agreement, the said first universal input/output interface GPIO1 is configured to NMOS and opens Lou output; The said second universal input/output interface GPIO2 is configured to perseverance " 1 " output power supply is provided; The said the 3rd general input/output interface GPIO3 is configured to NMOS and opens Lou output, on data/address bus, can hang a plurality of I2C interface equipments 61, and said I2C interface equipment 61 for example is gyroscope, accelerometer, thermometer, pressure gauge etc.
Embodiment four
Referring to Fig. 5, this embodiment is configured to two line interfaces with said headset interface and GPIO interface duplex circuit structure.The first control signal SHD_BIAS that said host register is sent, the second control signal SHD_MIC, the 3rd control signal SHD_HPL, the 4th control signal SHD_HPR are high level; Correspondingly; Said low pressure difference linear voltage regulator LDO, programmable gain amplifier PGA, the first power amplifier PA1 and the second power amplifier PA2 all break off; Externally be presented as high-impedance state; And the said first universal input/output interface GPIO1, the second universal input/output interface GPIO2 and the 3rd general input/output interface GPIO3 form two line interfaces through suitable configuration; As shown in Figure 5; The said first universal input/output interface GPIO1 is configured to the data wire SDIN of two line interfaces, the said second universal input/output interface GPIO2 is configured to the power line VDD of two line interfaces, the said the 3rd general input/output interface GPIO3 is configured to the clock line SCLK of two line interfaces; The output 31 of the said first power amplifier PA1 connects the 8th capacitor C 8 backs and is connected with said L channel earphone interface HPL; The said second universal input/output interface GPIO2 is connected with said L channel earphone interface HPL; The output 41 of the said second power amplifier PA2 connects the 9th capacitor C 9 backs and is connected with said R channel earphone interface HPR; The said the 3rd general input/output interface GPIO3 is connected with said R channel earphone interface HPR; Between said microphone interface MIC and said L channel earphone interface HPL, be connected the 4th resistance R 4, between said L channel earphone interface HPL and said R channel earphone interface HPR, be connected the 5th resistance R 5, according to two line interface agreements; The said first universal input/output interface GPIO1 is configured to NMOS and opens Lou output; The said second universal input/output interface GPIO2 is configured to perseverance " 1 " output to be provided power supply, the said the 3rd general input/output interface GPIO3 to be configured to NMOS to open with Louing and export, on data/address bus, can hang a plurality of two line interface equipment 71.
Embodiment five
This embodiment is configured to USB interface with said headset interface and GPIO interface duplex circuit structure.The output of said first power amplifier is connected with said L channel earphone interface after connecting an electric capacity; The output of said second power amplifier is connected with said R channel earphone interface after connecting an electric capacity; Between said microphone interface and said L channel earphone interface, be connected a resistance, between said L channel earphone interface and said R channel earphone interface, be connected a resistance; The first control signal SHD_BIAS that said host register is sent, the second control signal SHD_MIC, the 3rd control signal SHD_HPL, the 4th control signal SHD_HPR are high level; Correspondingly; Said low pressure difference linear voltage regulator LDO, programmable gain amplifier PGA, the first power amplifier PA1 and the second power amplifier PA2 all break off, and externally are presented as high-impedance state; Said first universal input/output interface is configured to the positive differential data wire (D+) of USB interface; Said second universal input/output interface is configured to the power line of USB interface, the said the 3rd general input/output interface is configured to the negative differential data line (D-) of USB interface.
Obviously, those skilled in the art can carry out various changes and modification to invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these revise and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these change and modification.
Claims (11)
1. headset interface and universal input/output interface multiplex circuit structure; It is characterized in that; Comprise: main frame base band or main frame audio codec, first universal input/output interface, second universal input/output interface, the 3rd general input/output interface, microphone interface, L channel earphone interface, R channel earphone interface and ground connection mouth, said main frame base band or main frame audio codec comprise low pressure difference linear voltage regulator, programmable gain amplifier, first power amplifier, second power amplifier and earth terminal;
The output of said low pressure difference linear voltage regulator is connected with said microphone interface after connecting first resistance; Said microphone interface is connected with the input of said programmable gain amplifier after connecting first electric capacity, and said first universal input/output interface is connected with said microphone interface;
The earth terminal of said main frame base band or main frame audio codec is connected with said ground connection mouth;
The output of said first power amplifier is connected with said L channel earphone interface, and said second universal input/output interface is connected with said L channel earphone interface;
The output of said second power amplifier is connected with said R channel earphone interface, and the said the 3rd general input/output interface is connected with said R channel earphone interface.
2. headset interface as claimed in claim 1 and universal input/output interface multiplex circuit structure; It is characterized in that; The control end of said low pressure difference linear voltage regulator is connected with host register; By said its operating state of host register control, the input of said low pressure difference linear voltage regulator connects the voltage that main frame sends, and the voltage that this main frame sends is exported microphone bias voltage after said low pressure difference linear voltage regulator voltage stabilizing.
3. headset interface as claimed in claim 1 and universal input/output interface multiplex circuit structure; It is characterized in that; The control end of said programmable gain amplifier is connected with host register; By said its operating state of host register control, the output of said programmable gain amplifier is connected with the analog to digital converter of main frame.
4. headset interface as claimed in claim 1 and universal input/output interface multiplex circuit structure; It is characterized in that; The control end of said first power amplifier is connected with host register; By said its operating state of host register control, the input of said first power amplifier is connected with the digital to analog converter of main frame.
5. headset interface as claimed in claim 1 and universal input/output interface multiplex circuit structure; It is characterized in that; The control end of said second power amplifier is connected with host register; By said its operating state of host register control, the input of said second power amplifier is connected with the digital to analog converter of main frame.
6. headset interface as claimed in claim 1 and universal input/output interface multiplex circuit structure; It is characterized in that; Said first universal input/output interface, second universal input/output interface and the 3rd general input/output interface are connected with said host register respectively, by the control of said host register itself or be input state or be output state.
7. headset interface as claimed in claim 1 and universal input/output interface multiplex circuit structure; It is characterized in that; The output of said first power amplifier is connected with said L channel earphone interface after connecting an electric capacity; The output of said second power amplifier is connected with said R channel earphone interface after connecting an electric capacity; Microphone is connected between said microphone interface and the ground connection mouth, and left earphone is connected between said L channel earphone interface and the ground connection mouth, and right earphone is connected between said R channel earphone interface and the ground connection mouth; Said low pressure difference linear voltage regulator, programmable gain amplifier, first power amplifier and second power amplifier are all opened, and said first universal input/output interface, second universal input/output interface and the 3rd general input/output interface all are configured to floating empty input.
8. headset interface as claimed in claim 1 and universal input/output interface multiplex circuit structure; It is characterized in that; The output of said first power amplifier is connected with said L channel earphone interface after connecting an electric capacity; The output of said second power amplifier is connected with said R channel earphone interface after connecting an electric capacity; Said low pressure difference linear voltage regulator, programmable gain amplifier, first power amplifier and second power amplifier all break off, and form bus through the configuration to said first universal input/output interface, second universal input/output interface and the 3rd general input/output interface.
9. headset interface as claimed in claim 1 and universal input/output interface multiplex circuit structure; It is characterized in that; The output of said first power amplifier is connected with said L channel earphone interface after connecting an electric capacity; The output of said second power amplifier is connected with said R channel earphone interface after connecting an electric capacity; Between said microphone interface and said L channel earphone interface, be connected a resistance, between said L channel earphone interface and said R channel earphone interface, be connected a resistance; Said low pressure difference linear voltage regulator, programmable gain amplifier, first power amplifier and second power amplifier all break off; Said first universal input/output interface is configured to the data wire of I2C interface, said second universal input/output interface is configured to the power line of I2C interface, the said the 3rd general input/output interface is configured to the clock line of I2C interface.
10. headset interface as claimed in claim 1 and universal input/output interface multiplex circuit structure; It is characterized in that; The output of said first power amplifier is connected with said L channel earphone interface after connecting an electric capacity; The output of said second power amplifier is connected with said R channel earphone interface after connecting an electric capacity; Between said microphone interface and said L channel earphone interface, be connected a resistance, between said L channel earphone interface and said R channel earphone interface, be connected a resistance; Said low pressure difference linear voltage regulator, programmable gain amplifier, first power amplifier and second power amplifier all break off; Said first universal input/output interface is configured to the data wire of two line interfaces, said second universal input/output interface is configured to the power line of two line interfaces, the said the 3rd general input/output interface is configured to the clock line of two line interfaces.
11. headset interface as claimed in claim 1 and universal input/output interface multiplex circuit structure; It is characterized in that; The output of said first power amplifier is connected with said L channel earphone interface after connecting an electric capacity; The output of said second power amplifier is connected with said R channel earphone interface after connecting an electric capacity; Between said microphone interface and said L channel earphone interface, be connected a resistance, between said L channel earphone interface and said R channel earphone interface, be connected a resistance; Said low pressure difference linear voltage regulator, programmable gain amplifier, first power amplifier and second power amplifier all break off; Said first universal input/output interface is configured to the positive differential data wire of USB interface, said second universal input/output interface is configured to the power line of USB interface, the said the 3rd general input/output interface is configured to the negative differential data line of USB interface.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110428776XA CN102427569A (en) | 2011-12-20 | 2011-12-20 | Headset interface and GPIO (General Purpose Input/Output) interface multiplex circuit structure |
| PCT/CN2012/086745 WO2013091516A1 (en) | 2011-12-20 | 2012-12-17 | Earphone interface and gpio interface multiplexing circuit structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110428776XA CN102427569A (en) | 2011-12-20 | 2011-12-20 | Headset interface and GPIO (General Purpose Input/Output) interface multiplex circuit structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102427569A true CN102427569A (en) | 2012-04-25 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110428776XA Pending CN102427569A (en) | 2011-12-20 | 2011-12-20 | Headset interface and GPIO (General Purpose Input/Output) interface multiplex circuit structure |
Country Status (2)
| Country | Link |
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| CN (1) | CN102427569A (en) |
| WO (1) | WO2013091516A1 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013091516A1 (en) * | 2011-12-20 | 2013-06-27 | 杭州硅星科技有限公司 | Earphone interface and gpio interface multiplexing circuit structure |
| WO2016000639A1 (en) * | 2014-07-04 | 2016-01-07 | 王玮冰 | Headset interface control system and headset interface control method |
| CN105977740A (en) * | 2016-05-30 | 2016-09-28 | 歌尔股份有限公司 | Earphone adapter |
| CN107192880A (en) * | 2017-04-28 | 2017-09-22 | 上海与德科技有限公司 | The detection circuit and its detection method of mobile terminal |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101006623A (en) * | 2004-06-30 | 2007-07-25 | 维夫康姆公司 | Single connector for a communication terminal, corresponding electronic circuit, terminal and cable |
| US20070229518A1 (en) * | 2005-12-28 | 2007-10-04 | Manabu Kii | Information processing apparatus, information processing method, information processing program and recording medium |
| CN101350989A (en) * | 2008-08-18 | 2009-01-21 | 嘉兴闻泰通讯科技有限公司 | Plug adapter for a mobile terminal |
| CN101931674A (en) * | 2010-09-01 | 2010-12-29 | 惠州Tcl移动通信有限公司 | Method and device for sharing Micro-USB interface |
| CN101951421A (en) * | 2010-09-20 | 2011-01-19 | 深圳桑菲消费通信有限公司 | Expansion use method for cell phone earphone interface |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100570591C (en) * | 2007-09-29 | 2009-12-16 | 中兴通讯股份有限公司 | Terminal chip pin multiplexing device |
| US8666091B2 (en) * | 2008-06-13 | 2014-03-04 | Sony Corporation | Method for reducing a disturbance in an input signal caused by an output signal in a multi-port connector, multi-port connector, and mobile device |
| US20100073079A1 (en) * | 2008-09-24 | 2010-03-25 | Sony Ericsson Mobile Communications Ab | Bias arrangement and apparatus |
| CN102395084B (en) * | 2011-11-11 | 2014-05-14 | 杭州硅星科技有限公司 | Headset circuit |
| CN102427569A (en) * | 2011-12-20 | 2012-04-25 | 杭州硅星科技有限公司 | Headset interface and GPIO (General Purpose Input/Output) interface multiplex circuit structure |
-
2011
- 2011-12-20 CN CN201110428776XA patent/CN102427569A/en active Pending
-
2012
- 2012-12-17 WO PCT/CN2012/086745 patent/WO2013091516A1/en active Application Filing
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101006623A (en) * | 2004-06-30 | 2007-07-25 | 维夫康姆公司 | Single connector for a communication terminal, corresponding electronic circuit, terminal and cable |
| US20070229518A1 (en) * | 2005-12-28 | 2007-10-04 | Manabu Kii | Information processing apparatus, information processing method, information processing program and recording medium |
| CN101350989A (en) * | 2008-08-18 | 2009-01-21 | 嘉兴闻泰通讯科技有限公司 | Plug adapter for a mobile terminal |
| CN101931674A (en) * | 2010-09-01 | 2010-12-29 | 惠州Tcl移动通信有限公司 | Method and device for sharing Micro-USB interface |
| CN101951421A (en) * | 2010-09-20 | 2011-01-19 | 深圳桑菲消费通信有限公司 | Expansion use method for cell phone earphone interface |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013091516A1 (en) * | 2011-12-20 | 2013-06-27 | 杭州硅星科技有限公司 | Earphone interface and gpio interface multiplexing circuit structure |
| WO2016000639A1 (en) * | 2014-07-04 | 2016-01-07 | 王玮冰 | Headset interface control system and headset interface control method |
| CN105282639A (en) * | 2014-07-04 | 2016-01-27 | 杭州硅星科技有限公司 | Headset interface control system and headset interface control method |
| CN105282639B (en) * | 2014-07-04 | 2019-07-23 | 杭州硅星科技有限公司 | Earphone microphone interface control system and earphone microphone interface control method |
| CN105977740A (en) * | 2016-05-30 | 2016-09-28 | 歌尔股份有限公司 | Earphone adapter |
| CN105977740B (en) * | 2016-05-30 | 2018-04-27 | 歌尔股份有限公司 | A kind of earphone joint |
| CN107192880A (en) * | 2017-04-28 | 2017-09-22 | 上海与德科技有限公司 | The detection circuit and its detection method of mobile terminal |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2013091516A1 (en) | 2013-06-27 |
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Application publication date: 20120425 |