WO2016000639A1

WO2016000639A1 - Headset interface control system and headset interface control method

Info

Publication number: WO2016000639A1
Application number: PCT/CN2015/083180
Authority: WO
Inventors: 陈锋
Original assignee: 王玮冰
Priority date: 2014-07-04
Filing date: 2015-07-02
Publication date: 2016-01-07
Also published as: CN105282639B; CN105282639A

Abstract

A headset interface control system and a headset interface control method. The headset interface control system comprises: a host controller (10), a headset interface, and a slave conversion module (13). The host controller (10) configures the headset interface. The slave conversion module (13) is connected to the headset interface and converts a signal on the headset interface into a bus signal. The headset interface control system and method implement connection between a host and various devices via the headset interface, thus allowing functional diversification of the headset interface.

Description

Headset interface control system and headset interface control method

Technical field

The present invention relates to the field of terminal equipment technologies, and in particular, to a headset interface control system and a headset interface control method.

Background technique

Headsets are extremely versatile, so there are headsets on many devices. The prior art headset interface only serves as a bridge between the headset device and the audio codec, baseband or processor, etc. Therefore, the prior art headset interface can only implement the connection between the host and the headset device.

Summary of the invention

The object of the present invention is to provide a headset interface control system and a headset interface control method, so as to solve the problem that the headset interface in the prior art only serves as a bridge between the headset device and the audio codec, baseband or processor, and has a relatively simple function. problem.

In order to solve the above technical problem, the present invention provides a headset interface control system, where the headset interface control system includes: a host controller, a headset interface, and a slave conversion module, wherein the host controller configures the headset interface, The slave conversion module is coupled to the headset interface to convert signals on the headset interface into bus signals.

Optionally, in the headset interface control system, the method further includes: a host baseband or a host audio codec connected to the host controller, and a filtering connection with the host baseband or the host audio codec. A bias circuit, wherein the host baseband or host audio codec includes a buffer and a register coupled to the buffer, the headset interface being disposed on the filtering and biasing circuit.

Optionally, in the headset interface control system, the headset interface includes a microphone interface, a grounding port, a left channel earphone interface, and a right channel earphone interface.

Optionally, in the headset interface control system, the slave conversion module converts a signal on the headset interface into an I2C bus signal or an SPI bus signal.

The invention also provides a headset interface control method, and the headset interface control method includes:

The host controller configures a signal on the headset interface;

The slave conversion module converts the signal on the headset interface into a bus signal.

Optionally, in the headset interface control method, the signal that the host controller configures the headset interface includes:

The host controller configures an input signal of the buffer;

Buffer output signal to the filtering and biasing circuit;

Filter and bias circuit output signals.

Optionally, in the headset interface control method, the input signal of the host controller configuration buffer includes:

The output signal of the host controller configuration register and the offset input level, the left channel digital-to-analog signal, and the right-channel digital-to-analog signal.

Optionally, in the headset interface control method, the output signal of the register includes: the zeroth register is a logic high level or a logic low level, the first register is a logic high level or a logic low level, or The second register is logic high or logic low.

Optionally, in the headset interface control method, the bias input level includes: a logic high level or a logic low level.

Optionally, in the headset interface control method, the left channel digital-to-analog signal includes: a digital signal or an analog signal.

Optionally, in the headset interface control method, the right channel digital-to-analog signal comprises: a digital signal or an analog signal.

Optionally, in the headset interface control method, the buffer output signal to the filtering and biasing circuit includes:

The buffer outputs a microphone bias level, a left channel output signal, and a right channel output signal to the filtering and biasing circuit.

Optionally, in the headset interface control method, the microphone bias level includes: a low resistance high level, a logic low level, or a high resistance.

Optionally, in the headset interface control method, the left channel output signal includes: a buffered left channel digital-to-analog signal or a high impedance.

Optionally, in the headset interface control method, the right channel output signal includes: a buffered right channel digital-to-analog signal or a high impedance.

Optionally, in the headset interface control method, when the headset interface is configured as an I2C interface, the input signals of the host controller configuration buffer include:

Configuring the second register to be a logic high level; configuring the first register to be a logic high level, configuring the left channel digital-to-analog signal to be an AC signal or a DC high level; configuring the zeroth register to a logic high level, configuring the right channel The digital-to-analog signal is an AC clock signal or a logic low level.

Optionally, in the headset interface control method, when the headset interface is configured as an SPI interface, the input signals of the host controller configuration buffer include:

Configuring the second register to be a logic low level; configuring the first register to be a logic high level, configuring the left channel digital-to-analog signal to be an AC signal; configuring the zeroth register to a logic high level, configuring the right channel digital-to-analog signal to be send data.

In the headset interface control system and the headset interface control method provided by the present invention, the host controller configures a headset interface, and the slave converter module is connected to the headset interface to convert the signal on the headset interface into a bus signal, thereby implementing the host through the headset interface. Connecting with a variety of devices makes the functions of the headset interface diversified.

DRAWINGS

1 is a block diagram showing the structure of a headset interface control system according to an embodiment of the present invention;

2 is a schematic structural diagram of a frame in which a headset interface is configured as an I2C interface according to an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of a frame in which a headset interface is configured as an SPI interface according to an embodiment of the present invention.

detailed description

The headset interface control system and the headset interface control method proposed by the present invention are further described in detail below with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will be apparent from the description and appended claims. It should be noted that the drawings are in a very simplified form and all use non-precise proportions, and are only for convenience and clarity to assist the purpose of the embodiments of the present invention.

Please refer to FIG. 1 , which is a block diagram of a headset interface control system according to an embodiment of the present invention. As shown in FIG. 1, the headset interface control system includes: a host controller 10, a headset interface, and a slave conversion module 13, wherein the host controller 10 configures the headset interface, and the slave conversion module 13 and The headset interfaces are connected to convert signals on the headset interface into bus signals.

Further, the headset interface control system further includes: a host baseband or host audio codec (BaseBand/Codec) 11 connected to the host controller 10, and connected to the host baseband or host audio codec 11 Filtering and biasing circuit (RC) 12, wherein the host baseband or host audio codec 11 includes a buffer 20 and a register 21 connected to the buffer 20, the headset interface is disposed in the The filtering and biasing circuit 12 is described.

The headset interface includes a microphone interface MIC, a grounding port GND, a left channel earphone interface HPL, and a right channel headphone interface HPR. The slave conversion module 13 converts output signals of the microphone interface MIC, the grounding port GND, the left channel headphone interface HPL, and the right channel headphone interface HPR. Specifically, the slave conversion module 13 converts the signal on the headset interface into an I2C bus signal or an SPI bus signal. Therefore, the corresponding slave conversion module 13 can be an I2C conversion module or an SPI conversion module.

Specifically, the register 21 is a 3-bit register of the control buffer 20 in the host baseband or host audio codec 11, which can be represented as CTRL<2:0>. Further, CTRL<0> indicates The zeroth register, CTRL<1> represents the first bit register, and CTRL<2> represents the second bit register.

Correspondingly, the embodiment further provides a headset interface control method, which specifically includes:

The host controller configures a signal on the headset interface;

The signal configured on the headset interface by the host controller includes:

The host controller 10 configures an input signal of the buffer 20;

The buffer 20 outputs a signal to the filtering and biasing circuit 12;

The filtering and biasing circuit 12 outputs a signal.

The input signal of the host controller 10 configuring the buffer 20 includes: an output signal of the host controller 10 configuration register 21 and a bias input level BIAS_IN, a left channel digital-to-analog signal/port HPL_DAC, and a right channel digital-to-analog signal/ Port HPR_DAC. The buffer 20 output signal to the filtering and biasing circuit 12 includes a buffer 20 outputting a microphone bias level MIC_BIAS, a left channel output signal/port HPLOUT, and a right channel output signal/port HPROUT to the filtering and biasing circuit 12.

Specifically, the microphone bias level MIC_BIAS output by the buffer 20 (ie, the host baseband or the host audio codec 11) is generally connected to the microphone interface MIC via a resistor in the filter and bias circuit 12, and the microphone is biased. The level MIC_BIAS internal buffer 20 is controlled by the bias input level BIAS_IN and the second bit register CTRL<2>. The microphone bias level MIC_BIAS is traditionally used as the bias port of the microphone, and can be used as an output port of data in subsequent applications of the present application.

The microphone bias level MIC_BIAS is controlled as follows: the bias input level BIAS_IN is from the signal in the host audio codec 11, the bias input level BIAS_IN is logic high and the second bit register CTRL<2> is logic High level, buffer 20 outputs microphone bias level MIC_BIAS (typically low impedance high level); bias input level BIAS_IN is logic low and The second bit register CTRL<2> is a logic high level, and the buffer 20 outputs the microphone bias level MIC_BIAS to a logic low level; as long as the second bit register CTRL<2> is a logic low level, the buffer 20 outputs a microphone. The bias level MIC_BIAS is high impedance. Specifically, the control of the microphone bias level MIC_BIAS is as shown in Table 1.

Table 1 microphone bias level MIC_BIAS

The microphone input signal/port MICI of the host baseband or the host audio codec 11 is generally connected to the microphone interface MIC through the DC blocking capacitor inside the filtering and biasing circuit 12, and the gain adjustable amplifier outputting the microphone modulus through the buffer 20 internally. Signal/port MIC_ADC, microphone analog signal/port MIC_ADC is connected to the analog to digital converter inside the host baseband or host audio codec 11. The microphone analog-to-digital signal/port MIC_ADC is traditionally used as an input port for an audio microphone signal and can be used as an input port for data in subsequent applications of the present application.

GND is the ground of the buffer 20 and the host baseband or host audio codec 11.

The left channel output signal/port HPLOUT of the host baseband or host audio codec 11 is typically connected to the left channel headphone interface HPL via a DC blocking capacitor inside the filter and bias circuit 12, either directly or directly via a wire (CLASS) -G output). Internally from the power amplifier output in the buffer 20, the input left channel digital-to-analog signal/port HPL_DAC of the power amplifier is derived from the output of the internal digital-to-analog converter. The right channel output signal/port HPROUT is traditionally used as the output port of the left channel of the audio headphone port. It can be used as a power generation port or as a clock generation port in the subsequent applications of this application. Can be used as a data port. When used as a clock port, different duty cycles of CLK can be configured. With different duty cycles, additional information can be transferred from the master to the slave.

The right channel output signal/port HPROUT control method is as follows: the left channel digital-to-analog signal/port HPL_DAC is derived from the analog signal outputted by the internal baseband or the host audio codec 11 internal digital-to-analog converter, and the first bit register CTRL<1> is Logic high, left channel digital-to-analog signal/port HPL_DAC is typically driven by the power amplifier inside buffer 20 to the left channel output signal/port HPLOUT of buffer 20; as long as the first bit register CTRL<1> is logic low Level, buffer 20 outputs left channel output signal / port HPLOUT is high impedance. The last left channel output signal/port HPLOUT is output to the left channel headphone interface HPL via the filtering and biasing circuit 12. The control of the left channel output signal/port HPLOUT is shown in Table 2.

Table 2 left channel output signal / port HPLOUT

The right channel output signal/port HPROUT of the host baseband or host audio codec 11 is generally connected to the right channel headphone interface HPR through the DC blocking capacitor inside the filtering and biasing circuit 12, and the two are directly connected directly through the wire (CLASS) -G output). Internally from the power amplifier output in the buffer 20, the input left channel digital-to-analog signal/port HPL_DAC of the power amplifier is derived from the output of the internal digital-to-analog converter. The right channel output signal/port HPROUT is traditionally used as the output port of the right channel of the audio headphone port. It can be used as a power generation port in the subsequent applications of this application, as a clock generation port, or as a data port. When used as a clock port, different duty cycles of CLK can be configured. With different duty cycles, additional information can be transferred from the master to the slave.

The right channel output signal / port HPROUT control method is as follows: left channel digital analog signal / port The HPL_DAC is derived from the analog signal output from the internal baseband or host audio codec 11 internal digital-to-analog converter. The zeroth register CTRL<0> is logic high, and the left channel digital-to-analog signal/port HPL_DAC is generally passed through the buffer 20. The power amplifier is driven to the right channel output signal/port HPROUT of the buffer 20; as long as the zeroth register CTRL<0> is logic low, the buffer 20 outputs the right channel output signal/port HPROUT to high impedance. Finally, the right channel output signal/port HPROUT is output to the left channel headphone interface HPL via the filtering and biasing circuit 12. The control of the right channel output signal/port HPROUT is shown in Table 3.

Table 3 right channel output signal / port HPROUT

Various data interfaces can be configured by different configurations of the output signal of the register 21, the bias input level BIAS_IN, the left channel digital-to-analog signal/port HPL_DAC, and the right channel digital-to-analog signal/port HPR_DAC. Next, the implementation method of configuring the headset interface as an I2C interface will be described. For details, refer to FIG. 2 .

At this time, the conversion module is specifically an I2C conversion module, and the microphone interface MIC is generally connected to the SDA port via the I2C conversion module; the grounding port GND is generally directly connected to the GND port via the internal wire of the I2C conversion module; the left channel headphone interface HPL is generally converted via I2C. The power submodule inside the module is connected to the VDD port; the right channel headphone interface HPR is generally connected to the SCL port via the clock recovery and processing circuit sub-module inside the I2C conversion module.

The bias input level BIAS_IN is configured to a logic low level.

The second register CTRL<2> is configured to be a logic high level, and then the microphone bias level MIC_BIAS is outputted to a logic low level via the buffer 20, and then filtered and biased through the resistor 12 The resistor divider in R3 and filter and bias circuit 12 is at a logic low level (selecting a suitable resistor ratio) at the microphone interface MIC of filter and bias circuit 12. The last logic low level is communicated to the SDA port via the I2C conversion module. The second register CTRL<2> is configured to be logic low. From the above signal path, an equivalent open-drain logic high level is obtained at the SDA port (because the resistor R3 is pulled up to the VDD port). This is the typical SDA port for the I2C interface.

Configure the first register CTRL<1> to be logic high, configure the right channel digital-to-analog signal/port HPR_DAC to be an AC signal (corresponding to the right channel output signal/port HPROUT has a DC blocking capacitor) or configure the right channel digital-to-analog signal. / Port HPR_DAC is DC high level (corresponding to the right channel output signal / port HPROUT is CLASS-G output). The right channel digital-to-analog signal/port HPR_DAC reaches the right channel output signal/port HPROUT via the power amplifier in the buffer 20, and the right channel output signal/port HPROUT is isolated by the filtering and biasing circuit 12 or directly to the left channel earphone The interface HPL, the left channel headphone interface HPL passes through the power submodule inside the I2C conversion module (if the CLASS-G output can directly replace the power module with a wire), the power from the left channel headphone interface HPL is output to the VDD port.

Corresponding to the right channel output signal / port HPROUT has a DC blocking capacitor, configure the zeroth register CTRL<0> to be a logic high level, and configure the right channel digital-to-analog signal/port HPR_DAC to be an AC clock signal (periodic signal). The right channel digital-to-analog signal/port HPR_DAC reaches the right channel output signal/port HPROUT via the power amplifier in the buffer 20, and the right channel output signal/port HPROUT is isolated by the filtering and biasing circuit 12 to the right channel headphone interface HPR The right channel headphone interface HPR outputs the clock from the right channel headphone interface HPR to the SCL port through the clock recovery and processing circuit sub-module inside the I2C conversion module, making it a clock signal conforming to the I2C standard.

Corresponding to the right channel output signal / port HPROUT without DC blocking capacitor (CLASS-G output), then direct wire connection from the right channel output signal / port HPROUT to the SCL port. Configure the zeroth register CTRL<0> to be logic high and configure the right channel digital-to-analog signal/port HPR_DAC to be logic The low level, then, the SCL port signal is logic low. Configure the zeroth register CTRL<0> to be logic low, then the SCL port gets an equivalent open-drain logic high (because the resistor R2 is pulled up to the VDD port). This is a typical clock interface for the I2C interface. Different CLK duty cycles can be configured, and different information can be transferred from the master to the slave through different duty cycles.

On the data bus (ie VDD port, SDA port, SCL port and GND port), you can hang a bunch of I2C interface devices such as gyroscopes, accelerometers, thermometers, pressure gauges, etc.

Next, the implementation method of configuring the headset interface as an SPI interface will be described. For details, refer to FIG. 3.

At this time, the conversion module is specifically an SPI conversion module, and the microphone interface MIC is generally connected to the MISO port via the SPI conversion module; the grounding port GND is generally directly connected to the GND port via the internal wire of the SPI conversion module; the left channel headphone interface HPL is generally converted via SPI. The power module and the clock circuit module and the duty cycle decoding module inside the module are connected to the VDD, CLK and CS ports respectively; the right channel headphone interface HPR is generally connected to the MOSI port via the circuit module inside the SPI conversion module.

The second register CTRL<2> is configured to be a logic low level, and then the microphone bias level MIC_BIAS outputs a high impedance via the buffer 20. The MISO port is directly connected to the microphone interface MIC, and the data from the SPI slave is coupled to the microphone input signal/port MICI via the capacitance inside the filter and bias circuit 12, and reaches the microphone analog signal/port MIC_ADC via the PGA in the buffer 20. This configures an SPI host side data input channel.

The first register CTRL<1> is configured to be a logic high level, and the left channel digital-to-analog signal/port HPL_DAC is configured as an alternating current signal. The left channel digital-to-analog signal/port HPL_DAC reaches the right channel output signal/port HPROUT via the power amplifier in the buffer 20, and the right channel output signal/port HPROUT is isolated by the filtering and biasing circuit 12 or directly to the left channel earphone Interface HPL, left The channel headphone interface HPL outputs the power from the left channel headphone interface HPL to the VDD port through the power module inside the SPI conversion module, while the left channel headphone interface HPL passes the clock recovery module inside the SPI conversion module to the left channel earphone. The clock information of the interface HPL is output to the CLK port, and the duty ratio of the left channel digital-to-analog signal/port HPL_DAC AC clock signal is configured, and the duty cycle signal is decoded into CS<N by the duty ratio decoding circuit inside the SPI conversion module. The N-bit SPI chip select signal of -1:0> configures the VDD, CLK, and CS<N-1:0> ports of the SPI.

Corresponding to the right channel output signal / port HPROUT has DC blocking capacitor or no DC blocking capacitor (CLASS-G output), configure the zeroth register CTRL<0> to logic high level, configure the right channel digital-to-analog signal/port HPR_DAC to Data to be sent on the SPI host. The left channel digital-to-analog signal/port HPL_DAC reaches the right channel output signal/port HPROUT via the power amplifier in the buffer 20, and the left channel output signal/port HPLOUT passes through the filtering and biasing circuit 12 to the right channel headphone interface HPR. The right channel headphone interface HPR outputs the data from the right channel headphone interface HPR to the MOSI port through the circuit module inside the SPI conversion module, thus configuring an SPI host side data output channel.

On the SPI data bus (ie VDD port, MISO port, MOSI port, CLK port, CS<N-1:0> port and GND port), you can hang a bunch of SPI interface devices such as gyroscopes, accelerometers, thermometers, Pressure gauges, etc.

In summary, in the headset interface control system and the headset interface control method provided by the embodiments of the present invention, the headset interface can be configured by configuring the input signal of the buffer, so that the host and the multiple devices can be implemented through the headset interface. The connection makes the functions of the headset interface diversified.

The above description is only for the description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes and modifications made by those skilled in the art in light of the above disclosure are all within the scope of the appended claims.

Claims

A headset interface control system, comprising: a host controller, a headset interface, and a slave conversion module, wherein the host controller configures the headset interface, and the slave conversion module is connected to the headset interface Transmitting the signal on the headset interface into a bus signal.
The headset interface control system of claim 1 further comprising: a host baseband or host audio codec coupled to said host controller, and coupled to said host baseband or host audio codec And a filter and bias circuit, wherein the host baseband or host audio codec includes a buffer and a register coupled to the buffer, the headset interface being disposed on the filtering and biasing circuit.
The headset interface control system according to claim 1, wherein the headset interface comprises a microphone interface, a grounding port, a left channel earphone interface, and a right channel earphone interface.
The headset interface control system of claim 1 wherein said slave conversion module converts a signal on said headset interface into an I2C bus signal or an SPI bus signal.
A headset interface control method, comprising:

The host controller configures a signal on the headset interface;

The slave conversion module converts the signal on the headset interface into a bus signal.
The headset interface control method according to claim 5, wherein the signal configured on the headset interface by the host controller comprises:

The host controller configures an input signal of the buffer;

Buffer output signal to the filtering and biasing circuit;

Filter and bias circuit output signals.
The headset interface control method according to claim 6, wherein the input signal of the host controller configuring the buffer comprises:

Output signal of the host controller configuration register and offset input level, left channel digital analog Number and right channel digital-to-analog signals.
The headset interface control method according to claim 7, wherein the output signal of the register comprises: the zeroth register is a logic high level or a logic low level, and the first register is a logic high level or a logic low level, Or the second register is logic high or logic low.
The headset interface control method according to claim 7, wherein the bias input level comprises: a logic high level or a logic low level.
The headset interface control method according to claim 7, wherein the left channel digital-to-analog signal comprises: a digital signal or an analog signal.
The headset interface control method according to claim 7, wherein the right channel digital-to-analog signal comprises: a digital signal or an analog signal.
The headset interface control method according to claim 7, wherein the buffer output signal to the filtering and biasing circuit comprises:

The buffer outputs a microphone bias level, a left channel output signal, and a right channel output signal to the filtering and biasing circuit.
The headset interface control method according to claim 12, wherein the microphone bias level comprises: a low resistance high level, a logic low level or a high resistance.
The headset interface control method according to claim 12, wherein the left channel output signal comprises: a buffered left channel digital-to-analog signal or a high impedance.
The headset interface control method according to claim 12, wherein the right channel output signal comprises: a buffered right channel digital-to-analog signal or a high impedance.
The headset interface control method according to claim 7, wherein when the headset interface is configured as an I2C interface, the input signal of the host controller configuration buffer includes:

Configuring the second register to be a logic high level; configuring the first register to be a logic high level, configuring the left channel digital-to-analog signal to be an AC signal or a DC high level; configuring the zeroth register to a logic high level, configuring the right channel The digital-to-analog signal is an AC clock signal or a logic low level.
The headset interface control method according to claim 7, wherein when the headset interface is configured as an SPI interface, the input signal of the host controller configuration buffer includes:

Configuring the second register to be a logic low level; configuring the first register to be a logic high level, configuring the left channel digital-to-analog signal to be an AC signal; configuring the zeroth register to a logic high level, configuring the right channel digital-to-analog signal to be send data.