CN113506788A - Multi-row IO chip and design method thereof - Google Patents
Multi-row IO chip and design method thereof Download PDFInfo
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- CN113506788A CN113506788A CN202110639913.8A CN202110639913A CN113506788A CN 113506788 A CN113506788 A CN 113506788A CN 202110639913 A CN202110639913 A CN 202110639913A CN 113506788 A CN113506788 A CN 113506788A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
Abstract
The application discloses multirow IO chip and design method thereof, wherein multirow IO chip includes: a chip body; the IO ring is composed of a plurality of chips IO and arranged on the outermost side of the chip body and surrounding the periphery of the chip body, and the chips are communicated with the outside and supplied with power through the IO ring; the IO ring at least comprises a first IO ring and a second IO ring, the first IO ring is connected with the second IO ring, and the length of the first IO ring is equal to the perimeter of the chip; the second IO ring is the part of the IO ring beyond the perimeter of the chip. In this way, this application will surpass the part of chip girth and constitute the second IO circle, reduce the length of first IO circle to avoided too much IO to lead to the chip area to prop big problem, and need not to reduce chip function and chip logic.
Description
Technical Field
The application relates to the technical field of chip physics, in particular to a multi-row IO chip and a design method thereof.
Background
The layout planning (Floorplan) is a very important step in the physical realization of the chip, and a reasonable layout planning can reduce the difficulty of time-allowed convergence, improve the success rate of winding and enhance the stability of a power supply. The layout planning mainly comprises chip area, planning and placing IO, IP and various modules and the like.
The cost of a chip is related to the area, because the size of each silicon wafer is fixed, and the smaller the area of the chip is, the larger the number of dies (die) that can be produced on each silicon wafer will be, so that the cost of a single chip will be reduced. Therefore, the area needs to be estimated preferentially when the chip is planned, which results in waste when the chip area is too large, and results in difficulty in laying out and routing when the chip area is too small.
There are two factors that determine the chip area. The first is Core dependent, meaning that the chip standard cells are too much outside the Core area plan expectations, so that the chip area needs to be increased. The second is determined by IO, which is usually placed around the chip due to the requirement of packaging, and too many IO will increase the length and width of the chip, resulting in an increase in area. To control cost, both factors are typically controlled for physical implementation to save chip area.
In the existing method, because the IO is placed in a circle around the chip, if the number of the IO is too large, the IO Ring is lengthened to increase the length and width of the chip, so that the area is increased, and the cost is increased and the internal area of the chip is wasted. In order to reduce the influence of IO on the area, only IO or multiplexing IO can be reduced, and the logic function of the chip is influenced. Therefore, at present, no good design scheme is available for solving the problem that the area of the chip is enlarged due to excessive IO.
Disclosure of Invention
The application provides a multi-row IO chip and a design method thereof, and aims to solve the problem that in the prior art, too much IO quantity influences the area of the chip.
In order to solve the above technical problem, the present application provides a multi-row IO chip, including: a chip body; the IO ring is composed of a plurality of chips IO and arranged on the outermost side of the chip body and surrounding the periphery of the chip body, and the chips are communicated with the outside and supplied with power through the IO ring; the IO ring at least comprises a first IO ring and a second IO ring, the first IO ring is connected with the second IO ring, and the length of the first IO ring is equal to the perimeter of the chip; the second IO ring is the part of the IO ring beyond the perimeter of the chip.
In order to solve the technical problem, the present application provides a method for counting multiple rows of IO chips, including: when the length of the IO ring exceeds the perimeter of the chip, the IO ring is designed to at least comprise a first IO ring and a second IO ring, the first IO ring is connected with the second IO ring, and the length of the first IO ring is equal to the perimeter of the chip; the second IO ring is the part of the IO ring beyond the perimeter of the chip.
The application provides a multi-row IO chip and a design method thereof, wherein the multi-row IO chip comprises: a chip body; the IO ring is composed of a plurality of chips IO and arranged on the outermost side of the chip body and surrounding the periphery of the chip body, and the chips are communicated with the outside and supplied with power through the IO ring; the IO ring at least comprises a first IO ring and a second IO ring, the first IO ring is connected with the second IO ring, and the length of the first IO ring is equal to the perimeter of the chip; the second IO ring is the part of the IO ring beyond the perimeter of the chip. In this way, this application will surpass the part of chip girth and constitute the second IO circle, reduce the length of first IO circle to avoided too much IO to lead to the chip area to prop big problem, and need not to reduce chip function and chip logic.
Drawings
In order to more clearly illustrate the technical solution of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
FIG. 1 is a diagram of an embodiment of an IO array of a chip in the prior art;
FIG. 2 is a schematic structural diagram of an embodiment of IO arrangement of multiple IO chips according to the present disclosure;
fig. 3 is a schematic connection diagram of an embodiment of a first IO ring and a second IO ring in the present application;
fig. 4 is a schematic flowchart of an embodiment of a method for designing a multi-row IO chip according to the present application.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present application, the multi-row IO chip and the design method thereof provided in the present application are further described in detail below with reference to the accompanying drawings and the detailed description.
Referring to fig. 1, fig. 1 is a schematic diagram of an embodiment of an IO array of a chip in the prior art. It can be seen that if the length of the IO Ring is too long to exceed the perimeter of the chip, the area of the chip will be forced to be large. The area of the whole chip is limited by the length and width of the IO ring.
In order to reduce the length of the IO loop, the prior art generally adopts a method of reducing the number of the IO or multiplexing the IO. Although the length of the IO loop can be effectively reduced by using the two methods, risks of chip function reduction, logic reduction and the like can be met.
Accordingly, the present application discloses a multi-row IO chip, please refer to fig. 2, and fig. 2 is a schematic structural diagram of an embodiment of an IO arrangement of the multi-row IO chip of the present application. In this embodiment, the method specifically includes: chip body and IO circle.
The IO circle comprises a plurality of chips IO, sets up in the outside of chip body, encloses around the chip body, and the chip can realize with outside communication and power supply through the IO circle. IO circle sets up can be convenient for encapsulate in the outside of chip body.
The IO ring at least comprises a first IO ring and a second IO ring, the first IO ring is connected with the second IO ring, and the length of the first IO ring is equal to the perimeter of the chip; the second IO ring is the part of the IO ring beyond the perimeter of the chip.
In this embodiment, when the length of the IO ring exceeds the perimeter of the chip, the IO exceeding part is set to be the second IO ring, so as to reduce the length of the first IO ring, thereby avoiding the expansion of the IO to the area of the chip.
The second IO circle is compared first IO circle, sets up the more inboard at the chip body. In some embodiments, the first IO ring is a plurality of IOs arranged in a closed graph, and the second IO ring is a plurality of IOs arranged continuously or discontinuously.
As shown in fig. 2, the first IO ring is a rectangle having the same shape as the chip and a different size, and is a closed figure; the second IO ring can be regarded as that certain IOs on the left side and the right side in the first IO ring are moved into the second IO ring to form an inner ring, so that the height of the whole chip is reduced, and the aim of reducing the total area of the chip is fulfilled.
In some embodiments, the first IO ring may be a non-closed figure. But generally the number of IOs in the first IO circle is larger than the number of IOs in the second IO circle.
It should be noted that, in some other embodiments, the multiple rows of IO chips may further include a third IO ring, for example, when the IO of the second IO ring is also almost fully arranged, the third IO ring may be continuously opened up, where the first IO ring, the second IO ring, and the third IO ring are connected.
It should be noted that the first IO ring is generally disposed on the outermost side of the chip body, and the second IO ring and the third IO ring gradually approach the center in sequence. However, in some embodiments, the second IO ring and the third IO ring may also be arranged according to the arrangement of the components inside the chip, which is not described herein.
Further, all the IOs of the IO chips in the rows are internally run through to form a network. Specifically, a plurality of IOs of the first IO ring form a through first network, a plurality of IOs of the second IO ring form a through second network, and the first network and the second network are electrically connected through a redistribution Layer (RDL) technology.
Optionally, the plurality of IOs of the first IO ring form a through first network through M5 metal, and the plurality of IOs of the second IO ring form a through second network through M5 metal.
Illustrate by way of example
Referring to fig. 3, fig. 3 is a schematic connection diagram of an embodiment of a first IO ring and a second IO ring in the present application. The first IO circle and the second IO circle respectively comprise three IOs: VDD IO, VSSIO IO, and VDDIO IO, where VDD IO is used to power the core; VSSIO/VDDIO IO is used to power IO. Each covered with PAD OPEN. The PAD OPEN is connected to the IO internal network through VIA (VIA).
The VDD IO of the first IO ring is connected with the VDD IO of the second IO ring to form a VDD network; the VSSIO IO of the first IO ring is connected with the VSSIO IO of the second IO ring to form a VSSIO network; VDDIO of the first IO ring is connected with VDDIO of the second IO ring to form a VDDIO network.
Optionally, the VDD IO of the first IO ring and the VDD IO of the second IO ring are connected through two PAD OPEN; the VSSIO IO of the first IO ring is connected with the VSSIO IO of the second IO ring through a PAD OPEN; VDDIO IO of the first IO ring and VDDIO IO of the second IO ring are connected through the two PAD OPENs.
Taking VDDIO as an example, VDDIO of the first IO ring and the second IO ring are internally formed into a network by splicing and penetrating through M5 layers of metal, but at the moment, the respective VDDIO networks of the first IO ring and the second IO ring are separated. Therefore, 2 PAD OPEN of the first IO ring and the second IO ring can be connected by using RDL layer metal, and at this time, VDDIO networks of the first IO ring and the second IO ring can be connected together.
To sum up, this embodiment provides a multirow IO chip, can save chip area, improves chip area utilization, reduces chip cost.
In addition, the present application further provides a method for designing a multi-row IO chip, please refer to fig. 4, where fig. 4 is a schematic flow chart of an embodiment of the method for designing a multi-row IO chip of the present application. In this embodiment, the method specifically includes the following steps:
s110: and judging whether the length of the IO ring exceeds the perimeter of the chip.
S120: when the length of the IO ring exceeds the perimeter of the chip, the IO ring is designed to at least comprise a first IO ring and a second IO ring, the first IO ring is connected with the second IO ring, and the length of the first IO ring is equal to the perimeter of the chip; the second IO ring is the part of the IO ring beyond the perimeter of the chip.
Optionally, the second IO ring is disposed on an inner side of the chip body than the first IO ring; the first IO circle is a plurality of IOs that the figure set up for sealing, and the second IO circle is a plurality of IOs that set up in succession or be interrupted.
Optionally, the plurality of IOs of the first IO ring form a through first network, the plurality of IOs of the second IO ring form a through second network, and the first network and the second network are electrically connected through a redistribution layer technology.
Optionally, the first IO ring and the second IO ring respectively include three IOs: VDD IO, VSSIO IO, and VDDIO IO, where VDD IO is used to power the core; VSSIO IO/VDDIO IO is used for supplying power to IO;
the VDD IO of the first IO ring is connected with the VDD IO of the second IO ring to form a VDD network; the VSSIO IO of the first IO ring is connected with the VSSIO IO of the second IO ring to form a VSSIO network; VDDIO of the first IO ring is connected with VDDIO of the second IO ring to form a VDDIO network.
Optionally, the VDD IO of the first IO ring and the VDD IO of the second IO ring are connected through two PAD OPEN; the VSSIO IO of the first IO ring is connected with the VSSIO IO of the second IO ring through a PAD OPEN; VDDIO IO of the first IO ring and VDDIO IO of the second IO ring are connected through the two PAD OPENs.
Optionally, the plurality of IOs of the first IO ring form a through first network through M5 metal, and the plurality of IOs of the second IO ring form a through second network through M5 metal.
The application discloses multirow IO chip and design method thereof, wherein multirow IO chip includes: a chip body; the IO ring is composed of a plurality of chips IO and arranged on the outermost side of the chip body and surrounding the periphery of the chip body, and the chips are communicated with the outside and supplied with power through the IO ring; the IO ring at least comprises a first IO ring and a second IO ring, the first IO ring is connected with the second IO ring, and the length of the first IO ring is equal to the perimeter of the chip; the second IO ring is the part of the IO ring beyond the perimeter of the chip. In this way, this application will surpass the part of chip girth and constitute the second IO circle, reduce the length of first IO circle to avoided too much IO to lead to the chip area to prop big problem, and need not to reduce chip function and chip logic.
It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not limiting of the application. In addition, for convenience of description, only a part of structures related to the present application, not all of the structures, are shown in the drawings. The step numbers used herein are also for convenience of description only and are not intended as limitations on the order in which the steps are performed. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms "first", "second", etc. in this application are used to distinguish between different objects and not to describe a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.
Claims (10)
1. A multi-row IO chip, comprising:
a chip body;
the IO ring is composed of a plurality of chips IO, is arranged on the outermost side of the chip body and surrounds the periphery of the chip body, and the chips are communicated with the outside and supplied with power through the IO ring;
the IO ring at least comprises a first IO ring and a second IO ring, the first IO ring is connected with the second IO ring, and the length of the first IO ring is equal to the perimeter of the chip; the second IO ring is a part of the IO ring exceeding the perimeter of the chip.
2. The multi-row IO chip of claim 1 wherein,
the second IO ring is arranged on the inner side of the chip body compared with the first IO ring; the first IO circle is a plurality of IOs that the figure set up for the closure, the second IO circle is a plurality of IOs that set up in succession or be interrupted the setting.
3. The multi-row IO chip of claim 1 wherein,
the plurality of IOs of the first IO ring form a through first network, the plurality of IOs of the second IO ring form a through second network, and the first network and the second network are electrically connected through a rewiring layer technology.
4. The multi-row IO chip of claim 3,
the first IO ring and the second IO ring respectively comprise three IOs: VDD IO, VSSIO IO, and VDDIO IO, wherein the VDD IO is used to power the core; the VSSIO IO/VDDIO IO is used for supplying power to IO;
the VDD IO of the first IO ring is connected with the VDD IO of the second IO ring to form a VDD network; the VSSIO IO of the first IO ring is connected with the VSSIO IO of the second IO ring to form a VSSIO network; VDDIO of the first IO ring is connected with VDDIO of the second IO ring to form a VDDIO network.
5. The multi-row IO chip of claim 4,
the VDD IO of the first IO ring and the VDD IO of the second IO ring are connected through two PAD OPENs; the VSSIO IO of the first IO ring and the VSSIO IO of the second IO ring are connected through a PAD OPEN; VDDIO IO of the first IO ring and VDDIO IO of the second IO ring are connected through two PAD OPENs.
6. The multi-row IO chip of claim 3,
the plurality of IOs of the first IO ring form a through first network through M5 metal, and the plurality of IOs of the second IO ring form a through second network through M5 metal.
7. A method for counting multiple rows of IO chips is characterized by comprising the following steps:
when the length of an IO ring exceeds the perimeter of a chip, designing the IO ring to at least comprise a first IO ring and a second IO ring, wherein the first IO ring is connected with the second IO ring, and the length of the first IO ring is equal to the perimeter of the chip; the second IO ring is a part of the IO ring exceeding the perimeter of the chip.
8. The multi-row design method for chip IO according to claim 7, wherein,
the second IO ring is arranged on the inner side of the chip body compared with the first IO ring; the first IO circle is a plurality of IOs that the figure set up for the closure, the second IO circle is a plurality of IOs that set up in succession or be interrupted the setting.
9. The method of designing multi-row IO chips in claim 8,
the plurality of IOs of the first IO ring form a through first network, the plurality of IOs of the second IO ring form a through second network, and the first network and the second network are electrically connected through a rewiring layer technology.
10. The method of designing multi-row IO chips in accordance with claim 9,
the first IO ring and the second IO ring respectively comprise three IOs: VDD IO, VSSIO IO, and VDDIO IO, wherein the VDD IO is used to power the core; the VSSIO IO/VDDIO IO is used for supplying power to IO;
the VDD IO of the first IO ring is connected with the VDD IO of the second IO ring to form a VDD network; the VSSIO IO of the first IO ring is connected with the VSSIO IO of the second IO ring to form a VSSIO network; VDDIO of the first IO ring is connected with VDDIO of the second IO ring to form a VDDIO network.
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| CN202110639913.8A CN113506788A (en) | 2021-06-08 | 2021-06-08 | Multi-row IO chip and design method thereof |
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| CN202110639913.8A CN113506788A (en) | 2021-06-08 | 2021-06-08 | Multi-row IO chip and design method thereof |
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| CN212182309U (en) * | 2020-10-26 | 2020-12-18 | 武汉新芯集成电路制造有限公司 | Chip packaging structure and storage packaging chip |
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| CN1369910A (en) * | 2001-02-14 | 2002-09-18 | 矽统科技股份有限公司 | Layout strcture for multi-layer metallic power/ground bus |
| CN1466210A (en) * | 2002-06-19 | 2004-01-07 | ��ͳ�Ƽ��ɷ�����˾ | Electrostatic discharge protection system for flip chip packaged IC and chip having said system |
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