CN101131971A - Semiconductor packaging construction for mold-sealing array processing and its manufacture process - Google Patents
Semiconductor packaging construction for mold-sealing array processing and its manufacture process Download PDFInfo
- Publication number
- CN101131971A CN101131971A CNA2006101114734A CN200610111473A CN101131971A CN 101131971 A CN101131971 A CN 101131971A CN A2006101114734 A CNA2006101114734 A CN A2006101114734A CN 200610111473 A CN200610111473 A CN 200610111473A CN 101131971 A CN101131971 A CN 101131971A
- Authority
- CN
- China
- Prior art keywords
- mould
- those
- chip carrier
- wafer
- packaging structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Landscapes
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
The present invention relates to a mold-array-processing, semiconductor-embedded structure and mold-array-process. The mold-array-process (MAP) semiconductor-embedded structure mainly includes a wafer carrier, a wafer at least and a seal colloid. The wafer is set on the wafer carrier and is electric connected to the carrier. The seal colloid covers the wafer carrier and seals the wafer, and two sides of the seal colloid are formed to be a mold-current-restricted region which is lower than central top surface of the seal colloid and aligns with the corresponding cut-margin of the wafer carrier. Therefore deformation of the seal colloid can reach balance between central and side mold currents, under conditions that no additional obstacle component for slowing current is needed, and there will not be MAP seal bubble beside the wafer.
Description
Technical field
The present invention relates to a kind of semiconductor packaging structure, particularly relate to a kind of semiconductor packaging structure (MAP type semiconductor package) and mould envelope ARRAY PROCESSING processing procedure thereof of mould envelope ARRAY PROCESSING.
Background technology
In the semiconductor packages field, (Mold Array Process MAP) can significantly reduce the manufacturing cost of adhesive body and promote packaging efficiency to use mould envelope ARRAY PROCESSING.A plurality of chip carriers are that one is included in the substrate strip, after pasting semiconductor wafer, use the mould encapsulation technique one adhesive body to be covered the most surfaces of a substrate strip, cut this adhesive body and this substrate strip along the border of those chip carriers, can obtain the MAP semiconductor packaging structure of box-shaped.
See also shown in Figure 1ly, a kind of semiconductor packaging structure 100 of existing known mould envelope ARRAY PROCESSING mainly comprises a chip carrier 110, a wafer 120 and an adhesive body 130.Semiconductor packaging structure maximum difference of single mould of itself and tradition envelope is that this adhesive body 130 is cut surfaces around having, and it is that cut edge with this chip carrier 110 is for vertically aliging.This wafer 120 is to be arranged on this chip carrier 110.A plurality of bonding wires 140 that routing forms electrically connect the weld pad 121 of this wafer 120 to this chip carrier 110, this adhesive body 130 is to be formed on this chip carrier 110 in mould envelope mode, and the below of this chip carrier 110 can be provided with the external terminal 150 of a plurality of for example soldered balls.This adhesive body 130 is to have the cut surface that aligns with this chip carrier 110.Yet mould envelope ARRAY PROCESSING (MAP) processing procedure forms an encapsulation bubble 131 at a side of wafer 120 easily.See also shown in Figure 2, this is because in mould envelope ARRAY PROCESSING (MAP) processing procedure, a plurality of chip carriers 110 are that array configurations and one connect into a substrate strip, the precursor material of one adhesive body 130 before slaking covers those chip carriers 110 according to mould envelope direction 132 with mould envelope mode large tracts of land, because those wafers 120 can stop the mould flow velocity degree of precursor material, so the precursor material of this adhesive body 130 can be less than the mould flow velocity degree in those chip carrier 110 both sides at the mould flow velocity degree of those wafers 120, and getting over wafer 120 parts that back segment is arranged, mould flow velocity degree in those chip carrier 110 central authorities (position with wafer 120) can be increasing with the mould flow velocity degree difference in those chip carrier 110 both sides, the air of wafer side has little time to discharge, and has the problem of MAP encapsulation bubble 131.
Invention patent certificate number several the 1240395th " glue sealing methods on the array kenel substrate " in Taiwan propose a kind of semiconductor packaging that solves MAP encapsulation bubble.In the MAP processing procedure, be provided with barrier (obstruction) in the upper surface both sides of each chip carrier, slowing down two side form flow velocity degree, and to have a mould flow velocity degree of wafer part suitable with the upper surface of chip carrier, to solve the problem of MAP encapsulation bubble.Yet those barriers are for additionally being attached on the chip carrier, can increasing fabrication steps and packaging cost.When adopting the thick film welding cover layer, its thickness deficiency then, the effect of slowing down mould flow velocity degree is limited.
This shows that the semiconductor packaging structure of above-mentioned existing mould envelope ARRAY PROCESSING obviously still has inconvenience and defective, and demands urgently further being improved in product structure, manufacture method and use.In order to solve the problem of above-mentioned existence, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but do not see always that for a long time suitable design finished by development, and common product and method do not have appropriate structure and method to address the above problem, and this obviously is the problem that the anxious desire of relevant dealer solves.Therefore how to found a kind of new mould and seal the semiconductor packaging structure of ARRAY PROCESSING, real one of the current important research and development problem that belongs to, also becoming the current industry utmost point needs improved target.
Because the defective that the semiconductor packaging structure of above-mentioned existing mould envelope ARRAY PROCESSING exists, the inventor is based on being engaged in this type of product design manufacturing abundant for many years practical experience and professional knowledge, and the utilization of cooperation scientific principle, actively studied innovation, seal the semiconductor packaging structure of ARRAY PROCESSING in the hope of founding a kind of new mould, can improve the semiconductor packaging structure of general existing mould envelope ARRAY PROCESSING, make it have more practicality.Through constantly research, design, and after studying sample and improvement repeatedly, create the present invention who has practical value finally.
Summary of the invention
Main purpose of the present invention is, overcome the defective of the semiconductor packaging structure existence of existing mould envelope ARRAY PROCESSING, and provide a kind of semiconductor packaging structure and mould of mould envelope ARRAY PROCESSING of new structure to seal the ARRAY PROCESSING processing procedure, technical problem to be solved is to make it can delete that the barrier in the prior art also still possesses the local flow speed of this adhesive body in the chip carrier both sides that delays, reach central authorities and side mould mobile equilibrium, can not produce MAP encapsulation bubble, so can reach existing known barrier technical characterictic abridged effect with the adhesive body change of shape of original element on the wafer next door.
The object of the invention to solve the technical problems realizes by the following technical solutions.The present invention discloses a kind of semiconductor packaging structure of mould envelope ARRAY PROCESSING, mainly comprises a chip carrier, at least one wafer and an adhesive body.This chip carrier is to have a upper surface, a lower surface and a plurality of cut edge between this upper surface and this lower surface.This wafer is to be arranged at the upper surface of this chip carrier and to electrically connect with this chip carrier.This adhesive body is that essence covers the upper surface of this chip carrier and seals this wafer, and wherein the wherein both sides of this adhesive body are the mould flow restriction portions that respectively forms, and it is the corresponding cut edge that is lower than the central end face of this adhesive body and is aligned to this chip carrier.Other discloses the mould envelope ARRAY PROCESSING processing procedure of this semiconductor packaging structure.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
In the semiconductor packaging structure of aforesaid mould envelope ARRAY PROCESSING, wherein those mould flow restriction portions have a side end face, highly are to reduce and approach to by the central end face of this adhesive body one second height to the active surface of this wafer by those side end faces to one first of the upper surface of this chip carrier.
In the semiconductor packaging structure of aforesaid mould envelope ARRAY PROCESSING, wherein this packaging structure is general rectangular packet, and this two moulds flow restriction portion is strip, and all the other both sides of this adhesive body then are not formed with mould flow restriction portion.
In the semiconductor packaging structure of aforesaid mould envelope ARRAY PROCESSING, wherein the width of those mould flow restriction portions is the sides that are no more than this wafer, and those mould flow restriction portions to the gap of this wafer side is roughly to be equal to or less than aforementioned first height.
In the semiconductor packaging structure of aforesaid mould envelope ARRAY PROCESSING, other includes a plurality of bonding wires, and it is to electrically connect this wafer and this chip carrier.
In the semiconductor packaging structure of aforesaid mould envelope ARRAY PROCESSING, wherein an active surface of this wafer is the upper surface that is attached at this chip carrier, and a plurality of weld pads of this wafer are to be aligned in the slotted eye of this chip carrier, and those bonding wires are to electrically connect those weld pads to this chip carrier by this slotted eye.
In the semiconductor packaging structure of aforesaid mould envelope ARRAY PROCESSING, wherein an active surface of this wafer is the upper surface away from this chip carrier, and with those bonding wires the weld pad of this wafer on this active surface is electrically connected to this chip carrier.
In the semiconductor packaging structure of aforesaid mould envelope ARRAY PROCESSING, other includes a plurality of external terminals, and it is the lower surface that is bonded on this chip carrier.
In the semiconductor packaging structure of aforesaid mould envelope ARRAY PROCESSING, wherein those external terminals are to comprise soldered ball.
By technique scheme, the semiconductor packaging structure of mould envelope ARRAY PROCESSING of the present invention has following advantage at least:
The semiconductor packaging structure of mould envelope ARRAY PROCESSING of the present invention and its mould envelope ARRAY PROCESSING processing procedure, it can be deleted the barrier in the prior art and still possess the local flow speed of this adhesive body in the chip carrier both sides that delays, reach central authorities and side mould mobile equilibrium, can not produce MAP encapsulation bubble, so can reach existing known barrier technical characterictic abridged effect with the adhesive body change of shape of original element on the wafer next door.By the change of shape of adhesive body, can be issued to central authorities and side mould mobile equilibrium in the condition that does not need to increase the unhurried current obstacle component, do not have MAP encapsulation bubble on the wafer next door.
In sum, the semiconductor packaging structure of the mould envelope ARRAY PROCESSING of novelty of the present invention has above-mentioned plurality of advantages and practical value, no matter it all has bigger improvement on product structure, method or function, obvious improvement is arranged technically, and produced handy and practical effect, and the semiconductor packaging structure of more existing mould envelope ARRAY PROCESSING has the outstanding effect of enhancement, thus be suitable for practicality more, and have the extensive value of industry, really be a new and innovative, progressive, practical new design.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, and for above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, below especially exemplified by preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Fig. 1 is a kind of schematic cross-section of semiconductor packaging structure of existing known mould envelope ARRAY PROCESSING.
Fig. 2 is the schematic diagram of an adhesive body mobile speed difference on array kenel substrate in existing known mould-seal array treating process.
Fig. 3 is according to first specific embodiment of the present invention, a kind of schematic cross-section of semiconductor packaging structure of mould envelope ARRAY PROCESSING.
Fig. 4 is according to first specific embodiment of the present invention, the end face schematic diagram of this semiconductor packaging structure.
Fig. 5 A to Fig. 5 D is according to first specific embodiment of the present invention, its chip carrier schematic cross-section in the mould-seal array treating process of this semiconductor packaging structure.
Fig. 6 is according to first specific embodiment of the present invention, illustrates the schematic diagram of adhesive body flowing velocity unification on array kenel substrate in mould-seal array treating process.
Fig. 7 is according to second specific embodiment of the present invention, the schematic cross-section of the semiconductor packaging structure of another kind of mould envelope ARRAY PROCESSING.
10: mold 20: bed die
100: semiconductor packaging structure 110: chip carrier
120: wafer 121: weld pad
130: adhesive body 131: bubble
132: mould flow path direction 140: bonding wire
150: external terminal 200: the semiconductor packaging structure of mould envelope ARRAY PROCESSING
210: chip carrier 211: upper surface
212: lower surface 213: cut edge
220: wafer 221: active surface
222: the back side 223: weld pad
230: adhesive body 231: mould flow restriction portion
232: mould flow path direction 233: central end face
234: side end face 240: bonding wire
250: external terminal 300: the semiconductor packaging structure of mould envelope ARRAY PROCESSING
310: chip carrier 311: upper surface
312: lower surface 313: slotted eye
314: cut edge 320: wafer
321: active surface 322: weld pad
330: adhesive body 331: mould flow restriction portion
332: central end face 340: bonding wire
350: external terminal H1: first height
H2: the second height S1: gap
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, its embodiment of semiconductor packaging structure, structure, manufacture method, step, feature and the effect thereof of the mould envelope ARRAY PROCESSING that foundation the present invention is proposed, describe in detail as after.
[execution mode]
In first specific embodiment of the present invention, a kind of semiconductor packaging structure 200 of mould envelope ARRAY PROCESSING mainly comprises a chip carrier 210, at least one wafer 220 and an adhesive body 230.Because this semiconductor packaging structure 200 is to form this adhesive body 230 with mould envelope ARRAY PROCESSING processing procedure, so this adhesive body 230 roughly is covered on this chip carrier 210 and the edge of this adhesive body 230 is that cut edge, four limits 213 with this chip carrier 210 is for trimming.
This chip carrier 210 is to have a upper surface 211, a lower surface 212 and a plurality of cut edge 213 between this upper surface 211 and this lower surface 212.In the present embodiment, this chip carrier 210 is to can be a printed circuit board (PCB), and its inside is provided with line construction, but also can be a ceramic circuit board, a lead frame or a metal support plate.
This wafer 220 is to be arranged at the upper surface 211 of this chip carrier 210 and to electrically connect with this chip carrier 210.Particularly, this wafer 220 be have an active surface 221 relative with one to the back side 222, a plurality of weld pads 223 are to be formed on this active surface 221, and can utilize existing known routing or chip bonding mode to be electrically connected to this chip carrier 210.In the present embodiment, this active surface 221 of this wafer 220 is the upper surfaces 211 away from this chip carrier 210, can utilize known sticking brilliant material that the back side 222 of this wafer 220 is adhered on the upper surface 211 or other wafer (figure does not draw) of this chip carrier 210, and can adopt traditional routing to electrically connect, bonding wire 240 those weld pads 223 of connection that form with a plurality of routings connect finger (figure does not draw) to this chip carrier 210.
See also shown in Figure 3ly, this adhesive body 230 is that essence covers the upper surface 211 of this chip carrier 210 and seals this wafer 220.This adhesive body 230 is with mould envelope ARRAY PROCESSING (Mold Array Process, MAP) fabrication techniques.Wherein, cooperation is consulted shown in Figure 4, and the wherein both sides of this adhesive body 230 are the mould flow restriction portions 231 that respectively form, and it is the corresponding cut edge 213 that is lower than the central end face 233 of this adhesive body 230 and is aligned to this chip carrier 210.In the present embodiment, this packaging structure 200 is general rectangular packets, and two mould flow restriction portions 231 are strip, and all the other both sides of this adhesive body 230 then are not formed with mould flow restriction portion 231.Preferably, again as shown in Figure 3, those side end faces 234 to one first height H 1 of the upper surface 211 of this chip carrier 210 is to reduce and approach to by the central end face 233 of this adhesive body 230 one second height H 2 to the active surface 221 of this wafer 220, so mould envelope ARRAY PROCESSING with the process that forms this adhesive body 230 in, the reduction of two side form flow restriction portions 231 highly can be identical or near the thickness of this wafer 220, will be slowly suitable according to as shown in Figure 6 mould flow path direction 232 to the central mould flow velocity degree that stops with these chip carrier 210 subject wafers 220 at two side form flow velocity degree of this chip carrier 210, so can prevent that producing MAP in the side than back segment wafer 220 encapsulates bubble.
See also Fig. 3 and shown in Figure 4, the width of those mould flow restriction portions 231 is the sides that are no more than this wafer 220, and the gap S1 of those mould flow restriction portions 231 to these wafer 220 sides roughly is equal to or less than aforementioned first height H 1, make this adhesive body 330 have a hat section, incite somebody to action more unification at the two side form flow velocity degree and the central mould flow velocity degree of this chip carrier 210.
In addition, this semiconductor packaging structure 200 is to include a plurality of external terminals 250 in addition, and it is the lower surface 212 that is bonded on this chip carrier 210.In the present embodiment, those external terminals 250 are to comprise soldered ball.
Therefore, in above-mentioned semiconductor packaging structure 200, can seal at mould and reach the balance of chip carrier 210 in ARRAY PROCESSING (MAP) process at central authorities and side mould stream, can not produce MAP encapsulation bubble, only just can reach existing known barrier technical characterictic and omit and still possess and delay the effect of this adhesive body 230 in the local flow speed of chip carrier 210 both sides with the change of shape of the adhesive body 230 of original element on wafer 220 next doors.
The mould of this semiconductor packaging structure 200 envelope ARRAY PROCESSING processing procedure further specify as after.At first, see also shown in Fig. 5 A and 6 figure, a substrate strip is provided, it is the chip carrier 210 that comprises a plurality of arrays and one connection.Then shown in Fig. 5 B, the upper surface 211 of a plurality of wafers 220 in those chip carriers 210 is set.And with those bonding wires 240 electric connections those wafers 220 and those chip carriers 210.Shown in Fig. 5 C and 6 figure, form an adhesive body 230 in transfer moulding (transfer molding) mode, it is that this mold 10 is to have an on-plane surface die cavity, with this adhesive body 230 that is shaped with a mold 10 and this substrate strip of a bed die 20 clampings.This adhesive body 230 is one essence to cover the upper surface 211 of those chip carriers 210 to seal those wafers 220.Wherein these adhesive body 230 correspondences respectively form a mould flow restriction portion 231 in the wherein both sides of each chip carrier 210, and it is the central end face 233 that is lower than this adhesive body 230, to slow down two side form flow velocity degree.As shown in Figure 6, according to mould flow path direction 232, this adhesive body 230 will be slowed down and roughly suitable with the central mould flow velocity degree of this adhesive body 230 above those wafers 220 at 210 liang of side form flow velocitys of each chip carrier degree.Shown in Fig. 5 D, after the demoulding, under the situation of not adding existing known barrier, can solve the problem of existing known MAP encapsulation bubble.At last, can sawing (sawing) mode cut this adhesive body 230 and this substrate strip, obtain a plurality of semiconductor packaging structures 200 as shown in Figure 3 and Figure 4, so that each chip carrier 210 is to have a plurality of cut edges 213 between this upper surface 211 and this lower surface 212, thus cutting single from after the mould flow restriction portion 231 of adhesive body 230 are the corresponding cut edges 213 that are aligned to corresponding chip carrier 210.
See also shown in Figure 7ly, in second specific embodiment of the present invention, the semiconductor packaging structure 300 of a kind of mould envelope ARRAY PROCESSING is mainly to comprise a chip carrier 310, at least one wafer 320 and an adhesive body 330.This chip carrier 310 is to have a upper surface 311, a lower surface 312 and a plurality of cut edge 314 between this upper surface 311 and this lower surface 312.This wafer 320 is to be arranged at the upper surface 311 of this chip carrier 310 and to electrically connect with this chip carrier 310.In the present embodiment, its encapsulation kenel is to be window sphere grid array (Window BGA), the active surface 321 of this wafer 320 is the upper surfaces 311 that are attached at this chip carrier 310, and a plurality of weld pads 322 of this wafer 320 are to be aligned in the slotted eye 313 of this chip carrier 310, and a plurality of bonding wires 340 are to electrically connect those weld pads 322 to this chip carrier 310 by this slotted eye 313.
This adhesive body 330 is that essence covers the upper surface 311 of this chip carrier 310 and fills up this slotted eye 313, to seal this wafer 320 and those bonding wires 340, wherein this adhesive body 330 is the mould flow restriction portions 331 that respectively form in the wherein both sides of this upper surface 311, and it is the corresponding cut edge 314 that is lower than the central end face 332 of this adhesive body 330 and is aligned to this chip carrier 310.Therefore, can be issued to central authorities and side mould mobile equilibrium, not have MAP encapsulation bubble on wafer 320 next doors in the condition that does not need to increase the unhurried current obstacle component.In addition, because the mould flow restriction portion 331 of both sides is lower with respect to the central authorities of this adhesive body 330,, can reduce the abrasion of sawing cutter so its cut surface is less.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the method that can utilize above-mentioned announcement and technology contents are made a little change or be modified to the equivalent embodiment of equivalent variations, in every case be the content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (18)
1. a mould seals the semiconductor packaging structure of ARRAY PROCESSING, it is characterized in that it mainly comprises:
One chip carrier, it is to have a upper surface, a lower surface and a plurality of cut edge between this upper surface and this lower surface;
At least one wafer, it is to be arranged at the upper surface of this chip carrier and to electrically connect with this chip carrier; And
One adhesive body, it is that essence covers the upper surface of this chip carrier and seals this wafer, and wherein the wherein both sides of this adhesive body are the mould flow restriction portions that respectively forms, and it is the corresponding cut edge that is lower than the central end face of this adhesive body and is aligned to this chip carrier.
2. the semiconductor packaging structure of mould envelope ARRAY PROCESSING according to claim 1, it is characterized in that wherein said those mould flow restriction portions have a side end face, highly is to reduce and approach to by the central end face of this adhesive body one second height to the active surface of this wafer by those side end faces to one first of the upper surface of this chip carrier.
3. the semiconductor packaging structure of mould envelope ARRAY PROCESSING according to claim 1 is characterized in that wherein this packaging structure is general rectangular packet, and this two moulds flow restriction portion is strip, and all the other both sides of this adhesive body then are not formed with mould flow restriction portion.
4. the semiconductor packaging structure of mould envelope ARRAY PROCESSING according to claim 2, the width that it is characterized in that wherein said those mould flow restriction portions is the side that is no more than this wafer, and those mould flow restriction portions to the gap of this wafer side is roughly to be equal to or less than aforementioned first height.
5. the semiconductor packaging structure of mould envelope ARRAY PROCESSING according to claim 1 is characterized in that it includes a plurality of bonding wires in addition, and it is to electrically connect this wafer and this chip carrier.
6. the semiconductor packaging structure of mould envelope ARRAY PROCESSING according to claim 5, an active surface that it is characterized in that wherein said wafer is the upper surface that is attached at this chip carrier, and a plurality of weld pads of this wafer are to be aligned in the slotted eye of this chip carrier, and those bonding wires are to electrically connect those weld pads to this chip carrier by this slotted eye.
7. the semiconductor packaging structure of mould envelope ARRAY PROCESSING according to claim 5, an active surface that it is characterized in that wherein said wafer is the upper surface away from this chip carrier, and with those bonding wires the weld pad of this wafer on this active surface is electrically connected to this chip carrier.
8. the semiconductor packaging structure of mould envelope ARRAY PROCESSING according to claim 1 is characterized in that it includes a plurality of external terminals in addition, and it is the lower surface that is bonded on this chip carrier.
9. the semiconductor packaging structure of mould envelope ARRAY PROCESSING according to claim 8 is characterized in that wherein said those external terminals are to comprise soldered ball.
10. the mould of a semiconductor packaging structure seals the ARRAY PROCESSING processing procedure, it is characterized in that it comprises following steps at least:
One substrate strip is provided, and it is the chip carrier that comprises a plurality of arrays and one connection, and those chip carriers are to have a upper surface and a lower surface;
The upper surface of a plurality of wafers in those chip carriers is set;
Electrically connect those wafers and those chip carriers;
Form an adhesive body in the transfer moulding mode, it is that one essence covers the upper surface of those chip carriers to seal those wafers, wherein this adhesive body correspondence respectively forms a mould flow restriction portion in the wherein both sides of each chip carrier, it is the central end face that is lower than this adhesive body, to slow down two side form flow velocity degree; And
Cut this adhesive body and this substrate strip so that each chip carrier is to have a plurality of cut edges between this upper surface and this lower surface, cutting single from after the mould flow restriction portion of adhesive body be the corresponding cut edge that is aligned to corresponding chip carrier.
11. the mould of semiconductor packaging structure according to claim 10 envelope ARRAY PROCESSING processing procedure, it is characterized in that wherein said each mould flow restriction portion has a side end face, highly is to reduce and approach to by the central end face of this adhesive body one second height to the active surface of corresponding wafer by those side end faces to one first of the upper surface of those chip carriers.
12. the mould of semiconductor packaging structure according to claim 10 envelope ARRAY PROCESSING processing procedure, it is characterized in that wherein a plurality of packaging structures after cutting are general rectangular packets, those mould flow restriction portions are strip, and all the other both sides of those adhesive bodies then are not formed with mould flow restriction portion.
13. the mould of semiconductor packaging structure according to claim 12 envelope ARRAY PROCESSING processing procedure, the width that it is characterized in that wherein said those mould flow restriction portions is the side that is no more than corresponding those wafers, and those mould flow restriction portions to the gap of corresponding wafer side is roughly to be equal to or less than aforementioned first height.
14. the mould of semiconductor packaging structure according to claim 10 envelope ARRAY PROCESSING processing procedure is characterized in that in the wherein said electric connection step it being to electrically connect those wafers and those chip carriers with a plurality of bonding wires.
15. the mould of semiconductor packaging structure according to claim 14 envelope ARRAY PROCESSING processing procedure, an active surface that it is characterized in that wherein said wafer is the upper surface that is attached at this chip carrier, and a plurality of weld pads of this wafer are to be aligned in the slotted eye of this chip carrier, and those bonding wires are to electrically connect those weld pads to this chip carrier by this slotted eye.
16. the mould of semiconductor packaging structure according to claim 14 envelope ARRAY PROCESSING processing procedure, an active surface that it is characterized in that wherein said wafer is the upper surface away from this chip carrier, and with those bonding wires the weld pad of this wafer on this active surface is electrically connected to this chip carrier.
17. the mould of semiconductor packaging structure according to claim 10 envelope ARRAY PROCESSING processing procedure is characterized in that it includes in addition: engage the lower surface of a plurality of external terminals at those chip carriers.
18. the mould of semiconductor packaging structure according to claim 17 envelope ARRAY PROCESSING processing procedure is characterized in that wherein said those external terminals are to comprise soldered ball.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006101114734A CN101131971A (en) | 2006-08-22 | 2006-08-22 | Semiconductor packaging construction for mold-sealing array processing and its manufacture process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006101114734A CN101131971A (en) | 2006-08-22 | 2006-08-22 | Semiconductor packaging construction for mold-sealing array processing and its manufacture process |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101131971A true CN101131971A (en) | 2008-02-27 |
Family
ID=39129164
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2006101114734A Pending CN101131971A (en) | 2006-08-22 | 2006-08-22 | Semiconductor packaging construction for mold-sealing array processing and its manufacture process |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101131971A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107329507A (en) * | 2016-04-29 | 2017-11-07 | 广西师范大学 | A kind of thermostatic control system |
-
2006
- 2006-08-22 CN CNA2006101114734A patent/CN101131971A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107329507A (en) * | 2016-04-29 | 2017-11-07 | 广西师范大学 | A kind of thermostatic control system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8609468B2 (en) | Semiconductor device and method of manufacturing the same | |
| CN100490131C (en) | Encapsulation construction of ball lattice array for preventing glue overflow | |
| KR20040037575A (en) | Micro leadless package having oblique etching line | |
| CN101131971A (en) | Semiconductor packaging construction for mold-sealing array processing and its manufacture process | |
| JP5125758B2 (en) | Resin-sealed semiconductor device and manufacturing method thereof | |
| JP2003224239A (en) | Semiconductor device and its manufacturing method | |
| JP5275019B2 (en) | Semiconductor device | |
| TW201308548A (en) | Multi-chip memory package having a small substrate | |
| JP2008053612A (en) | Semiconductor package | |
| US20030160308A1 (en) | Semiconductor device | |
| CN100490104C (en) | Mould-seal array treating process of packaging wafer and used substrates bar | |
| CN104465596A (en) | Lead frame, semiconductor packaging body and manufacturing method thereof | |
| CN202549841U (en) | Semiconductor module | |
| JP2017183417A (en) | Semiconductor device | |
| CN101127332A (en) | Pin ball grid array encapsulation structure of wafer | |
| TW200818349A (en) | Mold array process for semiconductor packages | |
| CN103130173B (en) | For MEMS chip encapsulation without little island lead frame, array of leadframes and encapsulating structure | |
| CN100490145C (en) | Package structure coated with asymmetric single-side pin lower wafer | |
| TWI307951B (en) | Mold array process for chip encapsulation and substrate strip utilized | |
| JPH03195052A (en) | Lead frame and manufacture thereof | |
| TWI242164B (en) | Method for constructing a memory card and structure thereof | |
| JP2005340309A (en) | Resin sealed semiconductor device and its manufacturing method | |
| TW200805592A (en) | MAP type semiconductor package | |
| JP2006332366A (en) | Semiconductor device | |
| KR100364842B1 (en) | Semiconductor package and method of manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |