CN101097953A - 半导体元件 - Google Patents

半导体元件 Download PDF

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CN101097953A
CN101097953A CNA2007100058337A CN200710005833A CN101097953A CN 101097953 A CN101097953 A CN 101097953A CN A2007100058337 A CNA2007100058337 A CN A2007100058337A CN 200710005833 A CN200710005833 A CN 200710005833A CN 101097953 A CN101097953 A CN 101097953A
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source
gate
silicide district
drain
district
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李丹晨
詹博文
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种半导体元件，其可改善电阻率下降效应和可靠度，包括：半导体基板；栅极介电质，位于上述半导体基板的上方；以及栅极，位于上述栅极介电质的上方；栅极硅化物区，位于上述栅极上；源/漏极区；邻接于上述栅极介电质；以及源/漏极硅化物区，位于上述源/漏极区上，其中上述源/漏极硅化物区和上述栅极硅化物区具有不同的金属组合。利用本发明形成的金属氧化物半导体元件具有已改善的电阻率下降效应和可靠度。

Description

半导体元件
技术领域
本发明涉及一种金属氧化物半导体(metal-oxide-semiconductor，MOS)元件的结构及其制造方法，特别涉及一种MOS元件硅化物区的形成。
背景技术
在微电子产业中，对于超大型集成电路(VLSI)系统而言，深次微米(deep-submicron)尺寸的要求主宰了设计的考虑。随着栅极尺寸的缩小，源/漏极的接面深度必须随之缩小以抑制所谓的短沟道效应(short channel effect，SCE)，其会降低微型化元件的性能。有关互补型金属氧化物半导体(complementary MOS，CMOS)尺寸缩小的一个主要问题为：不希望产生的寄生电容的增加。随着源/漏极的接面深度和多晶硅线宽缩小至深次微米的范围，接触孔的电阻变得更为重要且需要降低。
降低位于多晶硅栅极和源/漏极区与内连线之间的接触孔的电阻的方式为在外加导电薄膜以形成不同的导电内连线之前，于源/漏极区和栅极的顶面上形成金属硅化物。含镍的硅化物和含钴的硅化物为最常见的金属硅化物材料，其典型以硅化(自对准硅化)工艺形成。在硅化工艺中，于半导体基板上方，特别在暴露出的源/漏极区和栅极区的上方全面性地沉积金属薄膜。接着晶片受到一个或多个例如在700℃或更高温的退火步骤。上述的退火步骤使金属选择性的与暴露出的源/漏极区和栅极区产生反应，因此形成金属硅化物。因为上述硅化物层仅形成于金属材料与源/漏极区和多晶硅(polycrystalline silicon，polysilicon)栅极区直接接触的地方，为自对准硅化工艺。形成硅化物层之后，移除未反应的金属且进行内连线工艺以提供导电路径，例如形成介层孔以穿过沉积的层间介电层，和以例如钨的导电材料填充上述介层孔的内连线工艺。
然而，已知的硅化工艺具有下列缺点。举例来说，常用的含镍硅化物具有低电阻，且可于低温下形成。然而，含镍硅化物对于后续的高温工艺非常敏感，例如高应力的接触孔蚀刻停止层(contact etch stop layer，CESL)和/或层间介电层(ILD layer)的工艺。例如在仅有含镍硅化物的硅化工艺中，源/漏极区可能会产生纵条(stringer)和侵蚀(encroachment)等不希望看到的现象。因此集成电路的功能和可靠度会受到不利的影响。另一方面，含钴硅化物于高温环境下更为稳定且其工艺更为成熟，较不可能因后续高温工艺而受到不利的影响。然而，在约为35纳米(nm)尺寸或以下的工艺，含钴硅化物具有明显下降(roll-off)电阻率(resistivity)，其表示为当含钴硅化物的特征尺寸约接近35纳米(nm)尺寸或以下时，其电阻率会明显增加。由于MOS元件的栅极典型地具有较各别的源/漏极区小的尺寸，栅极硅化物区首先会看到电阻率下降的现象。上述现象会限制含钴硅化物在较小尺寸的先进工艺中的使用。
另外，此技术领域需要一种新的方法及结构，可包含利用硅化物以降低电阻率的优点，且同时克服先前技术的缺点。
发明内容
有鉴于此，本发明的主要目的提供一种半导体元件，包括：半导体基板；栅极介电质，位于上述半导体基板的上方；以及栅极，位于上述栅极介电质的上方；栅极硅化物区，位于上述栅极上；源/漏极区；邻接于包括上述栅极介电质和上述栅极的栅极叠层；以及源/漏极硅化物区，位于上述源/漏极区上，其中上述源/漏极硅化物区和上述栅极硅化物区具有不同的金属组合。
根据本发明的半导体元件，其中该源/漏极硅化物区和该栅极硅化物区的其中之一至少包含一金属。
根据本发明的半导体元件，其中该源/漏极硅化物区具有较该栅极硅化物区高的热稳定性。
根据本发明的半导体元件，其中该源/漏极硅化物区和该栅极硅化物区具有不同的厚度。
根据本发明的半导体元件，其中该源/漏极硅化物区不含镍，以及该栅极硅化物区不含钴。
根据本发明的半导体元件，其中该源/漏极硅化物区包含钴，其为唯一的金属成分，以及该栅极硅化物区包含镍，其为唯一的金属成分。
根据本发明的半导体元件，其中该源/漏极硅化物区具有较该栅极硅化物区高的钴浓度。
根据本发明的半导体元件，其中该源/漏极硅化物区具有较该栅极硅化物区低的镍浓度。
根据本发明的半导体元件，其中该源/漏极硅化物区包含金属，其择自包括钴、铂、镍及其组合的族群，以及该栅极硅化物区包含金属材料，其择自包括镍、镍铂合金、钴及其组合的族群。
为达成发明的另一目的，本发明提供一种半导体元件，包括：半导体基板，其包括沟道区；栅极介电质，位于上述半导体基板上以及上述沟道区上方；栅极硅化物区，位于上述栅极介电质上方；源/漏极区，邻接于上述栅极介电质；以及源/漏极硅化物区，位于上述源/漏极区上，其中上述源/漏极硅化物区大于上述栅极硅化物区的尺寸，具有下降的电阻率。
根据本发明的半导体元件，其中该源/漏极硅化物区包含硅化物，其具有较该栅极硅化物区高的热稳定性。
根据本发明的半导体元件，其中该源/漏极硅化物区包含金属，其择自包括钴、铂、镍及其组合的族群，以及该栅极硅化物区包含金属，其择自包括镍、镍铂合金、钴及其组合的族群。
根据本发明的半导体元件，其中该源/漏极硅化物区包含钴，以及其中该栅极硅化物区包含镍。
根据本发明的半导体元件，其中该栅极硅化物区还包括锗。
根据本发明的半导体元件，其中该栅极硅化物区直接位于该栅极介电质上。
根据本发明的半导体元件，其中还包括多晶硅区，其位于该栅极硅化物区和该栅极介电质之间。
为达成发明的又一目的，本发明提供一种半导体元件的形成方法，包括下列步骤：提供半导体基板；于上述半导体基板的上方形成栅极介电质；于上述栅极介电质的上方形成栅极；形成源/漏极区邻接于上述栅极介电质和上述栅极；于上述源/漏极区上形成源/漏极硅化物区；利用上述栅极，于上述栅极介电质上方形成栅极硅化物区；其中上述栅极硅化物区具有与上述源/漏极硅化物区不同的金属组合。
为达成发明的又一目的，本发明提供一种半导体元件的形成方法，包括下列步骤：提供半导体基板；于上述半导体基板的上方形成栅极介电质；于上述栅极介电质的上方形成栅极；形成源/漏极区邻接于上述栅极介电质；全面性形成第一金属层，进行第一退火步骤以于上述源/漏极区上形成源/漏极硅化物区；全面性形成介电层，且穿过上述介电层以暴露出上述第一金属层；移除上述第一金属层；全面性形成第二金属层，其中上述第二金属层具有与上述第一金属层不同的成分；以及进行第二退火步骤以于上述栅极介电质上方形成栅极硅化物区。于上述源/漏极区上形成源/漏极硅化物区；利用上述栅极，于上述栅极介电质上方形成栅极硅化物区；其中上述栅极硅化物区具有与上述源/漏极硅化物区不同的金属组合。
利用本发明较佳实施例形成的MOS元件具有已改善的电阻率下降效应(roll-off)和可靠度。
附图说明
图1至7为本发明较佳实施例的中间工艺剖面图，其中在形成接触孔蚀刻停止层后形成栅极硅化物区。
图8至10为本发明较佳实施例的另一变化例，其中在形成层间介电质后形成栅极硅化物区。
图11为本发明较佳实施例的又一变化例，其中源/漏极硅化物区再一次与栅极硅化物区形成。
其中，附图标记说明如下：
2～基板；4～栅极介电质；6～栅极；7～第一掩膜层；8～间隙壁；9～轻掺杂源/漏极区；10～浅沟槽隔离区；12～源/漏极区；14～金属层；16～源/漏极硅化物区；18～第二掩膜层；22～金属层；23～层间介电质；24～栅极硅化物区；34～金属层。
具体实施方式
以下利用工艺剖面图，以更详细地说明本发明较佳实施例的半导体元件及其形成方法，在本发明各实施例中，相同的符号表示相同的元件。
本发明提供一种利用新颖的硅化物工艺形成的半导体元件。其显示本发明较佳实施例的中间工艺步骤，在本发明各实施例中，相同的符号表示相同的元件。
请参考图1，其显示浅沟槽隔离(shallow trench isolation，STI)区10和一部分的金属氧化物半导体(metal-oxide-semiconductor，MOS)元件的形成，其包括位于基板2中的浅掺杂源/漏极区(lightly-doped drain/source，LDD)9，以及位于基板2上的栅极结构。在较佳实施例中，基板2为硅基板。在其他实施例中，可利用锗化硅(SiGe)、块状半导体(bulk semiconductor)、应变半导体(strained semiconductor)、化合物半导体(compound semiconductor)、绝缘层上覆硅(silicon on insulator，SOI)，或其他常用的半导体基板。较佳利用于基板2中蚀刻出浅沟槽以及利用例如为氧化硅的绝缘物填充上述沟槽的方式，形成浅沟槽隔离区10。
可利用各种已知的方法，例如热氧化法(thermal oxidation)、化学气相沉积法(chemical vapor deposition，CVD)等方法，于基板2上沉积栅极介电质4。栅极介电质4可为氧化物。由于氮化硅为有效的不纯物扩散阻障物，也可利用氮化硅做为栅极介电质4。氮化硅层较佳利用热氮化(thermal nitridation)硅的方式形成。也可利用氮-氢(nitrogen-hydrogen)的阳极等离子氮化法(plasmaanodic nitridation)或热氮化二氧化硅等方法制造氮化硅。栅极介电质4也可包括例如氧氮化合物(oxynitride)、含氧介电质(oxygen-containing dielectric)、含氮介电质(nitrogen-containing dielectric)或其组合的高介电常数(high-k)介电材料。
可利用化学气相沉积法(CVD)于栅极介电质4上形成栅极6。在较佳实施例中，栅极6包括多晶硅(polysilicon)。栅极6最好为掺杂不纯物以降低其片电阻(sheet resistance)。在其他实施例中，栅极6包括非晶硅(amorphoussilicon)。
如图1所示，于栅极6的上方形成第一掩膜层7。第一掩膜层7可包括氮化硅，然而也可利用例如为氧化物的其他材料形成第一掩膜层7。在较佳实施例中，利用抗反射层镀膜(anti-reflective coating layer，ARC layer)做为第一掩膜层7，抗反射层镀膜通常用于现行集成电路的图案化工艺步骤。于图案化栅极6后，保留且不移除上述抗反射层镀膜而做为掩膜层7。在其他实施例中，以特别的方式形成掩膜层7。较佳地，全面性地沉积然后图案化掩膜层7、栅极6和栅极介电质4。接着，较佳地利用栅极叠层做为掩膜，以掺杂适当的不纯物的方式形成浅掺杂源/漏极区9。
同样地如图1所示，可沿着栅极介电质4、栅极6和掩膜层7的侧壁形成一对间隙壁8。熟悉此技术可知，较佳于基板2与栅极叠层上方全面性沉积一介电层，以及接着进行一非等向性的蚀刻以移除水平表面上的介电质材料，而形成间隙壁8。如图1所示，间隙壁8可为单一介电层形成，或为包含多于一层介电层形成的复合层，举例来说，氧化硅层位于氮化硅层上所形成的复合层(图未显示)。值得注意的是，掩膜层7也可于形成间隙壁8之后形成，或于后续形成的源/漏极区硅化之前的任何时间形成。
请参考图2，其显示源/漏极区12的形成。在较佳实施例中，利用掺杂不纯物的方式于基板2中以形成源/漏极区12。间隙壁8和上述栅极叠层做为后续源/漏极掺杂工艺的掩膜。在其他实施例中，利用凹陷源/漏极区，以及接着于凹陷中磊晶成长例如硅、锗化硅或碳化硅的半导体材料，以形成源/漏极区12。可于磊晶成长的同时或于磊晶成长后掺杂所需的不纯物。
如图3所示，于源/漏极区12上沉积薄金属层14。金属层14较佳包括钴(Co)。然而，金属层14也可包括例如铂、镍或其组合的其他材料。通常不建议使用纯镍，但金属层14可为包括含镍的镍基合金(nickel-based alloy)。举例来说，合金中镍的重量百分比较佳约小于百分之九十九的重量百分比，更佳为约小于百分之九十七，最佳为小于百分之九十五。在较佳实施例中，物理气相沉积法(physical vapor deposition，PVD)用以形成金属层14，然而也可利用其他常用的方法形成金属层14，例如溅镀法(sputtering)、低压化学气相沉积法(low pressure CVD，LPCVD)和原子层化学气相沉积法(atomic layerCVD，ALD)。在另一实施例中，可利用无电镀膜法(electroless plating)形成金属层14，其可于源/漏极区12上选择性地形成金属层，但不会于例如间隙壁8和掩膜层7的介电层上形成金属层。
接着进行退火工艺，以形成源/漏极硅化物区16，且其形成的结构如图4所示。退火工艺较佳于400℃或高于400℃的温度下进行，然而为了顾及硅化物区的品质，较低的退火温度通常是较理想的。熟于此技术可知，可利用热退火法(thermal annealing)、快速退火法(flash annealing)、激光退火法(laserannealing)或其他类似的步骤执行退火工艺。在实施例中，退火工艺可包括两个步骤。第一步骤为包括在相对较低温度下的第一退火步骤。在第一步骤中，一部分的金属层14会与硅反应形成硅化物。此硅化物典型地具有比最终结构更高的电阻率。接着移除未反应的金属。第二步骤包括第二退火步骤，其将高电阻率的硅化物转变成为低电阻率的硅化物。在形成含钴硅化物的实施例中，在约300℃至400℃的温度下执行第一退火步骤，而在约700℃的温度下执行第二退火步骤。产生的源/漏极硅化物区16最好于较高温度下具有较高的热稳定性，且其可相容于例如高应力的接触孔蚀刻停止层和层间介电层等后续工艺。
请参考图5，其显示形成第二掩膜层18以覆盖源/漏极硅化物区16。在较佳实施例中，第二掩膜层18为接触孔蚀刻停止层(contact etch stop layer，CESL)，较佳为全面性沉积接触孔蚀刻停止层以覆盖整个元件，包括覆盖源/漏极硅化物区16和第一掩膜层7。在其他实施例中，第二掩膜层18特别为一栅极硅化物区而形成，且于形成栅极硅化物区后移除。于第二掩膜层18中形成开口20，且穿过开口20以暴露出第一掩膜层7。然后移除第一掩膜层7。
请参考图6，其显示第二金属层22的形成。第二金属层22较佳具有与金属层14不同的成分(请参考图3)，其中“不同的成分”意指不是金属层14至少具有一种与第二金属层22不同的金属元素，就是金属层14和22中金属元素大体上相同时，两者金属元素的百分比大体上不同。举例来说，如果金属层14和22的金属元素百分比差值约大于百分之五，金属层14和22则为不同的成分。更佳为，金属层22的金属硅化物具有相对较低的电阻率，且其硅化物的尺寸远小于源/漏极硅化物区16的尺寸时，其具有下降(roll-off)的电阻率。“下降”一词意指当硅化物区的尺寸小于某一数值时，各别硅化物区的电阻率明显增加。熟于此技术可知，MOS元件栅极的尺寸典型地小于其他横向的尺寸，且因此栅极会先产生电阻率增加的问题。金属层22较佳为包括镍，镍铂合金或其类似的金属。通常不建议使用钴，由于钴的硅化物于较例如镍的其他金属大的尺寸时，具有下降的电阻率。然而，金属层22可包含微小成分的钴，例如小于百分之五。由于金属层14(请参考图3)和22为不同的成分，结果由金属层14和22形成的硅化物区具有不同的成分。
接着执行第二硅化工艺。第二硅化工艺较佳于较第一硅化工艺低的温度下进行。较佳在约低于300℃的温度下执行第二硅化工艺。在实施例中，在约低于300℃的温度下执行第二硅化工艺的第一退火步骤，且在约低于400℃的温度下执行第二硅化工艺的第二退火步骤，以形成含镍的硅化物。如图7所示，第二硅化工艺于栅极6的顶部形成硅化物区24。
接着，在接触孔蚀刻停止层18的上方沉积层间介电质(inter-layerdielectric，ILD)23。层间介电质23较佳为低介电常数的介电层，具有介电常数，其值约小于3.5。然后形成接触插塞(图未显示)，其将源/漏极硅化物区16和栅极硅化物区24连接至其上金属层中的金属线。层间介电质23和接触插塞的工艺为此技术领域所熟知，因此不做重复叙述。
图8至10为本发明较佳实施例的另一变化例。在此实施例中，其起始步骤本质上与图1至4所示步骤相同。如图8至10所示，在形成源/漏极硅化物区16后，形成接触孔蚀刻停止层18和层间介电质23，且进行化学机械研磨(chemical mechanical polish，CMP)工艺以平坦化层间介电质23、接触孔蚀刻停止层18和间隙壁8与栅极6的表面。较佳地研磨掩膜层7直至暴露出栅极6。产生如图9所示的结构。另一方面，化学机械研磨工艺研磨至掩膜层7的顶面，再进行选择性的蚀刻以移除掩膜层7。然后形成金属层(图未显示)，其较佳包括本质上与金属层22相同的金属(请参考图6)。接着进行退火工艺，其本质上类似于金属层22的硅化工艺，且移除未反应的金属。产生如图10所示的具有栅极硅化物区24的结构。如有需要，接着可再次沉积层间介电质23以达到所需的厚度。
当可了解的是，栅极硅化物区24可于形成源/漏极硅化物区16之后的任何时间形成。更佳于高温工艺后形成栅极硅化物区24，因此栅极硅化物区24受到高温工艺的影响较小。
如图11所示，在本发明较佳实施例的又一变化例中，于形成接触孔蚀刻停止层18之前，移除掩膜层7。全面性地形成金属层34，其本质上与金属层22类似。然后进行退火工艺，以于栅极6的顶部上形成栅极硅化物区24。第二退火步骤导致额外的金属析出进入源/漏极硅化物区16内部。
由于栅极硅化物工艺和源/漏极硅化物工艺为不同的工艺，源/漏极硅化物区16和栅极硅化物区24很可能具有不同的厚度。可进一步控制硅化工艺以增加硅化物区厚度的差异。在实施例中，栅极6为完全硅化。例如利用沉积较厚的金属层和/或以持续较长的时间退火处理栅极6以达成完全硅化的栅极6。熟悉此技术可知，完全硅化的栅极可以避免电荷空乏效应，因此其为理想的特征。由于栅极硅化物区24和源/漏极硅化物区16不同时间形成，栅极6可以完全硅化而不会导致源/漏极区12的过度硅化。
当可了解的是，本发明的较佳实施例可以应用于锗化硅(SiGe)的硅化工艺，举例来说，用于p型金属氧化物半导体(PMOS)元件的锗化硅应激物(stressor)。另外，n型金属氧化物半导体(NMOS)和p型金属氧化物半导体(PMOS)的源/漏极区和栅极可具有不同的金属成分。因此可对NMOS元件和PMOS元件进行客制化的硅化工艺以符合不同设计上的需求。
本发明的较佳实施例具有多项优点。源/漏极区12典型地具有比栅极6更大的尺寸。因此，钴可用于形成源/漏极硅化物区16。由于钴的尺寸较大，即使利用65纳米(nm)或更小的工艺来制造MOS元件时，较不易发生下降效应。经由形成热稳定性高的源/漏极硅化物区16，其可容许例如形成高应力的接触孔蚀刻停止层18和/或层间介电质23等后续的高温工艺，而不致影响到已形成的源/漏极硅化物区。另一方面，形成的栅极硅化物区24较不需考虑为高温工艺所影响，在挑选金属时可有更多的选择，可选择具有较佳的电阻率下降性能表现的金属。
虽然本发明已以较佳实施例公开如上，然其并非用以限定本发明，任何本领域技术人员，在不脱离本发明的精神和范围内，当可做些许更动与润饰，因此本发明的保护范围当视后附的权利要求所界定的为准。

Claims (16)

1.一种半导体元件，包括：
半导体基板；
栅极叠层，包括：
栅极介电质，位于该半导体基板的上方；以及
栅极，位于该栅极介电质的上方；
栅极硅化物区，位于该栅极上；
源/漏极区，邻接于该栅极；以及
源/漏极硅化物区，位于该源/漏极区上，其中该源/漏极硅化物区和该栅极硅化物区具有不同的金属成分。
2.如权利要求1所述的半导体元件，其中该源/漏极硅化物区和该栅极硅化物区的其中之一至少包含一金属。
3.如权利要求1所述的半导体元件，其中该源/漏极硅化物区具有较该栅极硅化物区高的热稳定性。
4.如权利要求1所述的半导体元件，其中该源/漏极硅化物区和该栅极硅化物区具有不同的厚度。
5.如权利要求1所述的半导体元件，其中该源/漏极硅化物区不含镍，以及该栅极硅化物区不含钴。
6.如权利要求5所述的半导体元件，其中该源/漏极硅化物区包含钴，其为唯一的金属成分，以及该栅极硅化物区包含镍，其为唯一的金属成分。
7.如权利要求1所述的半导体元件，其中该源/漏极硅化物区具有较该栅极硅化物区高的钴浓度。
8.如权利要求1所述的半导体元件，其中该源/漏极硅化物区具有较该栅极硅化物区低的镍浓度。
9.如权利要求1所述的半导体元件，其中该源/漏极硅化物区包含金属，其择自包括钴、铂、镍及其组合的族群，以及该栅极硅化物区包含金属材料，其择自包括镍、镍铂合金、钴及其组合的族群。
10.一种半导体元件，包括：
半导体基板，其具有沟道区；
栅极介电质，位于该半导体基板上以及该沟道区上方；
栅极硅化物区，位于该栅极介电质上方；
源/漏极区，邻接于该栅极介电质，且该沟道区位于该源/漏极区之间；
源/漏极硅化物区，位于该源/漏极区上，其中该源/漏极硅化物区大于该栅极硅化物区的尺寸，具有下降的电阻率。
11.如权利要求10所述的半导体元件，其中该源/漏极硅化物区包含硅化物，其具有较该栅极硅化物区高的热稳定性。
12.如权利要求10所述的半导体元件，其中该源/漏极硅化物区包含金属，其择自包括钴、铂、镍及其组合的族群，以及该栅极硅化物区包含金属，其择自包括镍、镍铂合金、钴及其组合的族群。
13.如权利要求12所述的半导体元件，其中该源/漏极硅化物区包含钴，以及其中该栅极硅化物区包含镍。
14.如权利要求10所述的半导体元件，其中该栅极硅化物区还包括锗。
15.如权利要求10所述的半导体元件，其中该栅极硅化物区直接位于该栅极介电质上。
16.如权利要求10所述的半导体元件，其中还包括多晶硅区，其位于该栅极硅化物区和该栅极介电质之间。
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