CN101091240A - 半导体装置及制造方法 - Google Patents

半导体装置及制造方法 Download PDF

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CN101091240A
CN101091240A CNA2004800447503A CN200480044750A CN101091240A CN 101091240 A CN101091240 A CN 101091240A CN A2004800447503 A CNA2004800447503 A CN A2004800447503A CN 200480044750 A CN200480044750 A CN 200480044750A CN 101091240 A CN101091240 A CN 101091240A
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weld pad
semiconductor device
void area
film
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CN100530577C (zh
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铃木清市
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Sbanson Japan Co Ltd
Spansion LLC
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Sbanson Japan Co Ltd
Spansion LLC
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Abstract

本发明的目的在于提供一种半导体装置及其制造方法，在包围接合用开口(108)的焊垫(101)各边设有缝隙状的空隙区域(107)，以空隙区域(107a)作为边界，分割为焊垫(101)的接合用开口(108)侧区域(101a)和相邻设置的配线层(102)侧区域(101b)。配线层(102)侧区域(101b)与接合用开口(108)侧区域(101a)分离达空隙区域(107a)的宽度，且因为在该部分有比金属材料更柔软材料的钝化膜(103)的一部分形成被埋入的状态，所以热应力是通过空隙区域(107a)吸收、分散，并且大幅地抑制金属原子从接合用开口(108)侧区域(101a)扩散到配线层(102)侧区域(101b)。

Description

半导体装置及制造方法
技术领域
本发明有关于一种半导体装置，更详细为有关于一种防止半导体装置的焊垫部和配线部间的电性短路的技术。
背景技术
已知在设置于半导体基板上的连接垫(焊垫(bonding pad))和电极为通过配线而电性连接的构造的半导体装置中，具有因配线和保护膜的热膨胀系数差造成热应力产生，导致配线或保护膜产生裂缝(crack)的问题。
在专利文献1中，为了解决像这样的问题，揭示一种在具有将设置于半导体基板上的连接垫及突起电极(bump electrode)包围的图案(pattern)而被设置的再配线设有缝隙，将突起电极被按压时产生的应力通过缝隙分散、缓和而抑制配线短路或切断不良的技术。
专利文献1：日本特开2004-22653号公报
发明内容
发明欲解决的课题
然而，近年来的半导体产品伴随设计方针的精细化，除了要求焊垫的大小，当焊垫和钝化膜的重叠幅度或相邻的金属配线彼此的间隔等被配置在焊垫周围的各要素被要求要尽可能地精细化时，使以往由于设计方针宽松而没有产生因作为配线材料使用的金属原子(例如金原子或铝原子)扩散而导致的裂缝的产生、电性短路的问题变得显而易见。
亦即，通过在半导体装置的组合步骤的金线配线后的树脂膜塑热处理或半导体装置实际使用中的热履历等，会产生例如金线配线的金原子扩散侵入至芯片内的铝配线部等，使铝配线部体积膨胀而在钝化膜中产生裂缝，更进一步产生让用于配线的金属原子侵入该裂缝而接触到相邻的配线等的现象。
第1图是了说明这种问题的图式，其中第1图(a)是显示相互邻接配置的焊垫11和配线层12的位置关系的平面概念图。此外，第1图(b)及第1图(c)是在第1图(a)中沿着C-C’线的剖面概要图，个别图标出将接合线(bonding wire)16连接于焊垫11之前(第1图(b))和之后(第1图(c))。此外，图式中的以组件符号13表示者是了保护表面的钝化膜、14为形成于半导体基板15上的绝缘膜、18为设置于焊垫11的接合用开口、然后17为产生在钝化膜13中的裂缝。
例如，在p型半导体基板15的主面以CVD法(化学气相沉积法)成膜的绝缘膜14上，通过微影技术(photolithography)形成焊垫11和配线层12，将预定部位以钝化膜13覆盖。于此，暂定焊垫11和配线层12中的任一个为以铝形成者，且连接于设置在焊垫11的接合用开口18的接合线16为金线。此外，该接合线16是将装设在芯片外侧的未图标的导线架(leadframe)和焊垫11予以电性连接者。
在连接接合线16后，使用膜塑树脂以进行芯片的封装，不过因应伴随于该封装添加的热或半导体装置实际运作温度等，在接合线16和焊垫11的连接处(接触处)中，接合线16的金原子扩散侵入至由铝构成的焊垫11。扩散侵入至铝中的金原子是在焊垫11内迅速扩散而引起因应其浓度的体积膨胀。
这种体积膨胀进行到焊垫11和配线层12的厚度差超过一定程度时，在钝化膜13会产生如第1图(c)中图标的裂缝17。此外，在这种裂缝17内会有从焊垫11体积膨胀的金或铝侵入，当此现象到达配线层12时，焊垫11和配线层12会电性短路。并且，亦会产生周遭气体中的水分经由裂缝17渗入而使配线层12腐蚀的问题。
于此，虽然金属原子侵入至上述裂缝的程度(侵入量及侵入深度)是依存于施加的温度或时间，但为了回避因这种金属原子扩散而导致的组件不良，有必要设定将朝向焊垫11的接合线16的连接处从焊垫端部分离设置(例如，使L1为8μm以上)，或使焊垫11和配线层12的间隔为一定值以上(例如，使L2为15μm以上)等的边限，而有使芯片大小不得不变大的问题。
本发明有鉴于上述问题而研创者，其目的在于提供一种适合半导体产品设计方针的精细化，并防止半导体装置的焊垫部和配线部间电性短路的技术。
解决课题的手段
为了解决上述问题，本发明的半导体装置具备有相邻设置的焊垫部和配线部，并且，具有在上述焊垫的上述配线部侧的区域设置有和该焊垫的外周缘往实际相同方向延伸的空隙区域的构造。
在该半导体装置中，可为于上述焊垫的上述配线部侧的区域，至少设有3个上述空隙区域，而该空隙区域被配置为有复数列的构造。此外，可为上述配线部和上述焊垫的一部分区域由单一的保护膜覆盖，而在设置于上述一部分区域的空隙区域充填有上述保护膜的一部分的构造。此时，可为在上述焊垫的内侧区域设有接合线连接用的开口，而上述至少3个的空隙区域中的任一个设置于上述开口的形成区域的构造。
上述保护膜是将相对软性的第1绝缘膜和相对硬性的第2绝缘膜依序叠层的多层膜，并可为上述空隙区域的充填物为上述第1绝缘膜的一部分的构造。此外，可为上述第1绝缘膜为SOG(Spin on Glass；旋涂玻璃)膜，且上述第2绝缘膜为氮化硅膜的构造。并且，可为在包围上述空隙区域的上述焊垫的侧壁设有侧面壁(side wall)的构造。上述侧面壁可由钛或含钛的合金所形成。上述焊垫部和配线部是可装设在以覆盖埋入配线图案的方式形成在氧化硅膜上的构造。
本发明包含有一种半导体装置的制造方法，该制造方法是在绝缘层上形成导电层.将该导电层图案化成焊垫部和配线部，并通过上述焊垫的图案化，在上述焊垫的上述配线部侧的区域，形成有和该焊垫的外周缘往实际相同方向延伸的空隙区域。此时，可具备在上述焊垫的内侧区域形成有接合线连接用的开口的步骤。
本发明还包含有一种半导体装置的制造方法，该制造方法是形成通过绝缘层覆盖埋入配线图案，并在上述绝缘层上形成导电层，将该导电层图案化成焊垫部和配线部，通过上述焊垫的图案化，在上述焊垫的上述配线部侧的区域，形成有和上述焊垫的外周缘往实际相同方向延伸的空隙区域。
发明的效果
本发明中，由于将空隙区域设在焊垫的一部分区域，故可提供一种适合半导体产品设计方针的精细化，并防止半导体装置的焊垫部和配线部间电性短路的技术。
附图说明
第1图是用以说明习知技术的问题的图式，其中(a)是显示相互邻接配置的焊垫和配线层的位置关系的平面概念图。(b)及(c)是在(a)中沿着C-C’线的剖面概要图，个别图标出将接合线连接于焊垫之前(b)和之后(c)。
第2图是用以说明装设于本发明的半导体装置的焊垫以及与焊垫相邻的配线层的配置的图式，其中(a)是显示相互邻接配置的焊垫和配线层的位置关系的平面概念图。(b)及(c)是在(a)中沿着A-A’线的剖面概要图。
第3图是加速实验后的半导体装置的剖面SEM像((a)：本发明的半导体装置，(b)：习知配置的半导体装置)。
第4图是用以说明在接合用开口内设置空隙区域的范例的图式。
第5图是用以说明装设于本发明的半导体装置的焊垫以及与焊垫相邻的配线层配置的其它范例的图式，其中(a)是显示相互邻接配置的焊垫和配线层的位置关系的平面概念图。(b)是在(a)中沿着B-B’线的剖面概要图。
具体实施方式
以下参照图式，针对用以实施本发明的形态进行说明。
实施例1
第2图是用以说明装设于本发明的半导体装置的焊垫以及与焊垫相邻的配线层配置的一例的图式，其中第2图(a)是显示相互邻接配置的焊垫101和配线层102的位置关系的平面概念图。第2图(b)是在第2图(a)中沿着A-A’线的剖面概要图。此外，图式中的以组件符号103表示者是用以保护表面的钝化膜、104为形成于半导体基板105上的绝缘膜、108为设置于焊垫101的接合用开口、组件符号106为连接在接合用开口108的接合线。
在本发明的半导体装置中，于包围接合用开口108的焊垫101各边设有缝隙状的空隙区域107。此外，在此揭示的例中，由于假定为在焊垫101的上侧和下侧以及右侧皆设有未图标的配线层者而在全部的4个边设置空隙区域107，但一般而言，该空隙区域107仅设置在设有相邻的配线层的边即可。因此，在相邻配置于焊垫101的配线层仅为102的情形下，空隙区域仅为107a即可。
观察设有这种空隙区域107的焊垫101沿着A-A’线的剖面时，如第2图(b)所示，以空隙区域107a作为边界，分割为焊垫101的接合用开口108侧区域101a和相邻设置的配线层102侧区域101b。该配线层102侧区域101b中，和接合用开口108侧区域101a是分离达空隙区域107a的宽度，且因为在该部分有钝化膜103的一部分形成被埋入的状态，所以实际上不会产生因应伴随在接合线106连接后进行的使用膜塑树脂的封装而施加的热(例如，200℃、5小时)或半导体装置实际使用环境温度等而产生的接合线106的金属分子朝向101b的扩散通过会因空隙区域107a而截断。通过此外，因体积膨胀所产生的裂缝虽产生于空隙区域107a，但通过该裂缝的产生使体积膨胀的应力被缓和，而不会产生朝向配线层102的裂缝。
这种配置可使用精细加工技术，如以下方式实现。亦即，例如在电阻系数(specific resistance)为20Ω/cm的p型半导体基板105主面以CVD法成膜的氧化硅膜(膜厚800nm左右)的绝缘膜104上，通过微影技术形成焊垫101和配线层102。于此，焊垫101和配线层102是例如将膜厚500nm左右的AlCu合金(Cu：0.5wt％)膜以PVD法(物理气相沉积法)成膜，并通过微影技术对该AlCu合金膜进行图案化(patterning)而形成。此外，在该图案化的过程中，使焊垫101的期望位置(例如，在包围接合用开口108的4个边全部)的金属被去除而形成空隙区域107。
接着，使膜厚1000nm左右的氮化硅膜以CVD成长，将预定部位以钝化膜103覆盖，并将该膜的一部分以蚀刻(etching)去除而在焊垫101的内侧区域形成接合用开口108。然后，将接合线106连接在设置于焊垫101内侧区域的接合用开口108。在焊垫101连接有直径30nm金线的接合线106。
此外，在第2图所示的例中，接合用开口108是单边约90μm的矩形，而焊垫101的接合用开口108侧区域101a的宽W1为2μm，空隙区域107a的宽W2为1μm，且焊垫101的配线层102侧区域101b的宽W3为2μm。
此外，如第2图所示，亦可根据期望而在焊垫101的接合用开口108侧区域101a的侧壁以及焊垫101的配线层102侧区域101b的侧壁，形成由钛或含钛的合金所构成的侧面壁109、110。
在有关于这种配置的本发明的半导体装置中，进行加速实验(150℃、1000小时)以和习知配置的半导体装置进行信赖性比较。
第3图是显示将这种加速实验后的半导体装置的剖面SEM像修整的图式(第3图(a)：本发明的半导体装置，第3图(b)：习知配置的半导体装置)。从这些SEM(scanning electron microscope；扫描式电子显微镜)像是明了，在习知构造的半导体装置中，通过加热而使裂缝产生，且相对于在该裂缝部分从焊垫扩散侵入的金属到达相邻的配线层而产生电性短路的情形，在本发明的半导体装置中，由于含有空隙区域107的应力的吸收、分散效果，而在焊垫101的配线层102侧区域101b产生异种金属的连接，故能将以往原子等级的扩散，由该连接面以物理方式限制移动，结果可作为金属原子的扩散障壁而进行作用，且确认未产生到达配线层102的裂缝。
上述的空隙区域亦可设置在形成于焊垫101内侧区域的接合用开口108内。
第4图是用以说明在接合用开口108内设置空隙区域107的范例的图式，在该图所示的例中，空隙区域107a至107d的宽为1μm，长为20μm。
实施例2
第5图是显示装设于本发明的半导体装置的焊垫以及与焊垫相邻的配线层的配置，并用以说明其它范例的图式。第5图(a)是显示相互邻接配置的焊垫101和配线层102的位置关系的平面概念图。第5图(b)是在第5图(a)中沿着B-B’线的剖面概要图。此外，在该图中，组件符号111是通过热氧化法成长的氧化硅膜，112是在以CVD法成长的氧化硅膜104上形成的配线图案，113是以CVD法成长的氧化硅膜，并且有关于其它和实施例1相同的构成要素是标示相同的组件符号。
如第5图(a)所示，在本实施例的半导体装置中，以于焊垫101的各边包围接合用开口108的方式，形成相互以预定间隔设置的一对的缝隙状空隙区域(107a至107h)，再于对应这些一对的空隙区域107a至107h的分离区域的接合用开口108内的位置亦设置各1个的空隙区域(107i至107l)。亦即，空隙区域(107a至107h)和空隙区域(107i至107l)是设置于相互锯齿形配置的位置。通过这种锯齿形配置的方式，本案作为问题提出的将金线的接合线连接到焊垫101，并加上预定的热履历时产生的来自接合线的金原子扩散以及伴随于此产生的铝分子扩散，在用以到达配线层102所必要的实际有效扩散距离变长，而可将焊垫101和配线层102的间隔设计变狭窄。结果可提供满足精细化的要求，并且防止半导体装置的焊垫部和配线部间的的电性短路的技术。
此外，于此揭示的例中，由于假定为在焊垫101的上侧和下侧以及右侧皆设有未图标的配线层者，故虽在焊垫101的4个外侧附近区域全部设置一对的空隙区域，但一般而言，该成对的空隙区域只要仅设置在设有相邻的配线层的边即可。因此，在相邻配置于焊垫101的配线层仅有102的情形下，亦可将一对的空隙区域仅设为107a和107b，而使对应于此设置的接合用开口108内的空隙区域仅设为107i。
这种配置亦可使用精细加工技术而如以下方式实现。亦即，例如在电阻系数为20Ω/cm的p型半导体基板105主面以热氧化法成膜为氧化硅膜111(膜厚300nm左右)，在氧化硅膜111上设置以CVD法成膜为氧化硅膜(膜厚700nm左右)的绝缘膜104，并在该绝缘膜104上形成期望的配线图案112。该配线图案112是例如将膜厚500nm左右的AlCu合金(Cu：0.5wt％)膜以PVD法成膜，并通过微影技术对AlCu合金膜进行图案化而形成。
接着，以CVD法使覆盖配线图案112的氧化硅膜113(膜厚900nm左右)成膜，在该氧化硅膜113上通过微影技术形成焊垫101和配线层102。于此，焊垫101和配线层102是以例如将膜厚500nm左右的AlCu合金(Cu：0.5wt％)膜以PVD法成膜，并通过微影技术对AlCu合金膜进行图案化而形成。此外，在该图案化的过程中，形成有焊垫101的空隙区域107a至107l。此外，在第5图所示的例中，各空隙区域是宽2μm，长20μm的缝隙状者。
接着，作为钝化膜103将SOG(膜厚500nm左右)和氮化硅膜(膜厚700nm左右)依此顺序成膜。在该SOG成膜过程中于上述的空隙区域充填有SOG。此外，钝化膜103为2层构造是了在空隙区域充填较为柔软的SOG，且为了使被预测在的后步骤中产生的体积膨胀应力于SOG有效地被吸收从而抑制裂缝产生。然后，通过微影技术将钝化膜103的一部分予以蚀刻去除，在焊垫101的内侧区域形成接合用开口108。
伴随于接合用开口108形成的蚀刻步骤中，由于在焊垫101的配线层102侧区域形成的空隙区域107a至107h虽以钝化膜103覆盖着，使充填于其中的SOG不会被蚀刻而残留下来，但由于在焊垫101的接合用开口108区域所形成的空隙区域107i至107l没有以钝化膜103覆盖，故使充填于其中的SOG被蚀刻而去除。
最后，于设置在焊垫101内侧区域的接合用开口108连接未图标的接合线。
当设置这种空隙区域时，伴随在接合线连接后进行的使用膜塑树脂的封装而施加的热(例如，200℃、5小时)或半导体装置的实际使用环境温度等而产生的体积膨胀会通过空隙区域107a至107l而被吸收、分散，尤其因为在空隙区域107i至107l的内部为没有充填SOG的「空区域」和成为实际分子移动产生地点的与接合线间的连接部距离近，所以大部分的体积膨胀部分都在这些空隙区域107i至107l被吸收。此外，由于大幅地抑制金属原子从接合用开口108侧区域扩散到配线层102侧区域，故裂缝的产生频率亦显著地降低。因此，即使作为在设有焊垫101和配线层102的面的下方埋入配线图案112的装置(device)构造，亦不会因为应力而产生裂缝。
此外，虽然上述都以缝隙状作为空隙区域的形状来说明，但并非限定于该形状。由于空隙区域只要为用以将体积膨胀造成的应力缓和、分散，且作为从焊垫侧到配线层侧的金属原子的扩散障壁而进行作用者即可，故明了可根据设置像这样的空隙区域的场所，而将该形状、配列或数量进行适当变更。
如以上的说明，依据本发明，可提供一种适合半导体产品设计方针的精细化，并防止半导体装置的焊垫部和配线部间短路的技术。
以上虽详述有关于本发明较佳的实施形态，但本发明非限定于相关的特定的实施形态者，在记载于权利要求的本发明要旨的范围内，可进行各种的变形、变更。

Claims (12)

1.一种半导体装置，具备有相邻设置的焊垫部和配线部，并且在上述焊垫的上述配线部侧的区域，设有和该焊垫的外周缘往实际相同方向延伸的空隙区域。
2.如权利要求1所述的半导体装置，其中，在上述焊垫的上述配线部侧的区域至少设有3个上述空隙区域，且该空隙区域配置有数列。
3.如权利要求1或2所述的半导体装置，其中，上述配线部和上述焊垫的一部分区域由单一的保护膜覆盖，而在设置于上述一部分区域的空隙区域充填有上述保护膜的一部分。
4.如权利要求2或3所述的半导体装置，其中，在上述焊垫的内侧区域设有接合线连接用的开口，且上述至少3个空隙区域中的任一个设置于上述开口的形成区域。
5.如权利要求3或4所述的半导体装置，其中，上述保护膜是将相对软性的第1绝缘膜和相对硬性的第2绝缘膜依序叠层的多层膜，而上述空隙区域的充填物为上述第1绝缘膜的一部分。
6.如权利要求5所述的半导体装置，其中，上述第1绝缘膜为SOG膜，上述第2绝缘膜为氮化硅膜。
7.如权利要求1至6中任一项所述的半导体装置，其中，在包围上述空隙区域的上述焊垫的侧壁设有侧面壁。
8.如权利要求7所述的半导体装置，其中，上述侧面壁由钛或含钛的合金所形成。
9.如权利要求1至8中任一项所述的半导体装置，其中，上述焊垫部和配线部装设在以覆盖埋入配线图案的方式所形成的氧化硅膜上。
10.一种半导体装置制造方法，包括：
在绝缘层上形成导电层，
并将该导电层图案化成焊垫部和配线部，通过上述焊垫的图案化，在上述焊垫的上述配线部侧的区域，形成有和上述焊垫的外周缘往实际相同方向延伸的空隙区域。
11.如权利要求10所述的半导体装置制造方法，其中，在上述焊垫的内侧区域形成有接合线连接用的开口。
12.一种半导体装置制造方法，包括：
形成通过绝缘层覆盖的埋入配线图案，
并在上述绝缘层上形成导电层，
将该导电层图案化成焊垫部和配线部，通过上述焊垫的图案化，在上述焊垫的上述配线部侧的区域，形成有和上述焊垫的外周缘往实际相同方向延伸的空隙区域。
CNB2004800447503A 2004-10-29 2004-10-29 半导体装置及制造方法 Expired - Fee Related CN100530577C (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107256856A (zh) * 2012-03-08 2017-10-17 瑞萨电子株式会社 半导体装置

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5192163B2 (ja) * 2007-03-23 2013-05-08 住友電工デバイス・イノベーション株式会社 半導体装置
JP5452064B2 (ja) * 2009-04-16 2014-03-26 ルネサスエレクトロニクス株式会社 半導体集積回路装置
US8836150B2 (en) * 2010-11-29 2014-09-16 Toyota Jidosha Kabushiki Kaisha Semiconductor device
US9331019B2 (en) 2012-11-29 2016-05-03 Infineon Technologies Ag Device comprising a ductile layer and method of making the same
JP2016092061A (ja) * 2014-10-30 2016-05-23 株式会社東芝 半導体装置および固体撮像装置
US9484307B2 (en) * 2015-01-26 2016-11-01 Advanced Semiconductor Engineering, Inc. Fan-out wafer level packaging structure
JP2020155659A (ja) * 2019-03-22 2020-09-24 ソニーセミコンダクタソリューションズ株式会社 半導体装置および半導体装置の製造方法
CN111638625B (zh) * 2020-06-04 2023-03-14 厦门通富微电子有限公司 一种掩膜版、制备半导体器件的方法和半导体器件

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63141330A (ja) * 1986-12-03 1988-06-13 Nec Corp 半導体集積回路装置
US5565378A (en) * 1992-02-17 1996-10-15 Mitsubishi Denki Kabushiki Kaisha Process of passivating a semiconductor device bonding pad by immersion in O2 or O3 solution
KR0170316B1 (ko) * 1995-07-13 1999-02-01 김광호 반도체 장치의 패드 설계 방법
JP2000012604A (ja) * 1998-06-22 2000-01-14 Toshiba Corp 半導体装置およびその製造方法
US6165886A (en) * 1998-11-17 2000-12-26 Winbond Electronics Corp. Advanced IC bonding pad design for preventing stress induced passivation cracking and pad delimitation through stress bumper pattern and dielectric pin-on effect
JP3383236B2 (ja) * 1998-12-01 2003-03-04 株式会社日立製作所 エッチング終点判定方法及びエッチング終点判定装置
US6355576B1 (en) * 1999-04-26 2002-03-12 Vlsi Technology Inc. Method for cleaning integrated circuit bonding pads
US6803302B2 (en) * 1999-11-22 2004-10-12 Freescale Semiconductor, Inc. Method for forming a semiconductor device having a mechanically robust pad interface

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107256856A (zh) * 2012-03-08 2017-10-17 瑞萨电子株式会社 半导体装置
CN107256856B (zh) * 2012-03-08 2020-03-31 瑞萨电子株式会社 半导体装置

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