CN101009264A - 配线基板和半导体器件 - Google Patents
配线基板和半导体器件 Download PDFInfo
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Abstract
本发明提供一种配线基板,在配线基板的用于搭载半导体芯片的半导体芯片搭载区域配置有假线,该假线所包含的所有的配线的末端在上述半导体芯片搭载区域内呈开放的形状。由此,能够以简单的结构并不导致成本升高地防止半导体器件因水分膨胀而出现不佳的情况。
Description
技术领域
本发明涉及一种外部端子呈面阵列(area-array)状排列的面安装型半导体器件和用于该半导体器件的配线基板。
背景技术
近年来,为了顺应电子设备小型化的倾向并迎合安装工序自动化的要求,半导体封装广泛地采用了QFP(quad flat package:四方扁平封装)型和BGA(ball grid array:球栅阵列封装)型的CSP(chip sizepackage/chip scale package:芯片级封装)形状的半导体器件。由于上述半导体器件所配置的半导体元件的信号处理高速化和多功能化,就需要配置更多的外部端子。因此,较多地采用了在半导体器件的底面上二维地配置有外部连接端子的BGA型封装形状的半导体器件。例如,在专利文献1(日本国专利申请公开特开平9-121002,1997年5月6日公开)中就揭示了上述BGA型封装形状的半导体器件的一个示例,即:在半导体器件中,半导体芯片的电路形成面朝上,利用引线键合方式连接上述半导体芯片和配线基板,并通过配线图形和外部连接端子导通。
图5表示上述BGA型封装形状的树脂密封型半导体器件(BGA型半导体封装、BGA型半导体器件)的一个示例的剖面结构图,是现在的BGA型半导体封装的主流结构。这种BGA型半导体器件的结构在半导体器件的小型化和电气特性方面均优于其它半导体器件,所以,诸如便携式电话、便携式游戏机等的便携式电子设备大多采用这种BGA型半导体器件。
以下,参照图5来说明BGA型半导体器件100。如图5所示,BGA型半导体器件100主要由半导体芯片(半导体元件)1、配线基板80、连接半导体芯片1和配线基板80的金属丝(引线)7、导电性的外部端子9构成,并被树脂10密封。另外,配线基板80在绝缘性内层基板的两面具有配线图形,该配线图形由铜箔形成。借助于通孔来确保配线基板80的上、下两面的配线图形之间的导通,其中,该通孔是通过在由穿孔器等开口的贯通孔内部实施镀铜而得到的通孔。并且,除已形成电路的配线图案上的用于引线键合的端子部和用于形成外部端子的焊盘部之外,配线基板80被绝缘性阻焊层(solder resist)所覆盖。
近年来,电子设备实现了小型化和薄型化,这就要求所搭载的半导体器件也需实现小型化和薄型化,因此,上述半导体器件100所使用的配线基板80的厚度也需满足薄型化的要求。具体而言,厚度为200μm以下的绝缘性内层基板已成为主流,厚度为40μm~60μm的绝缘性内层基板也得到了较多的应用。关于采用了厚度为40μm~60μm的内层基板的配线基板的厚度,包括阻焊层的厚度在内达到100μm左右。
在BGA型半导体器件100中,在半导体芯片1的与电路形成面相反一侧的面上使用粘合材料将该半导体芯片1搭载于上述配线基板80上,并通过导电性的金属丝7连接半导体芯片1的焊盘部和配线基板80的引线键合端子部。近年来,随着电子设备多功能化的发展,也存在着层叠多个半导体芯片1的情况。半导体芯片1的厚度也取决于搭载数量等,但一般情况下为70μm~400μm。作为用于粘合半导体芯片1的粘合剂,采用银膏、绝缘膏、片状的粘合剂等。近年来,为了提高半导体芯片1和配线基板80之间的密合性而较多地采用片状的粘合剂。作为上述片状粘合剂的供给方法,有下述两种方法,即:预先在配线基板80的半导体芯片搭载区贴附片状粘合剂的方法;以及在半导体芯片1的背面侧贴附片状粘合剂的方法。作为在半导体芯片1的背面侧贴附片状粘合剂的方法,有这样一种方法,即:在晶圆状态的阶段,将片状粘合剂贴附于晶圆的背面侧,然后将其切割为芯片状。另外,还有一种将切片的粘结材料成分转印至半导体芯片1的背面侧从而实现供给的方法。
半导体芯片1和配线基板80之间借助于金属丝7实现导通,金属丝7采用金、铜等材料。具体而言,目前,较多采用剖面直径为20μm~30μm的金丝等。
半导体器件100被树脂10密封以使得覆盖半导体芯片1和金属丝7。上述密封是通过转移成型(Transfer Molding)法来实现的,其中,在该转移成型法中使用了树脂。用于实施密封的树脂10大多采用环氧系或联苯系的热硬化性树脂。
进而,借助于回流焊技术将焊球等金属制的外部端子9连接至半导体器件100的与配线基板80相反一侧的面。焊球的直径因外部端子的节距等而不同。近年来,出于对环境保护的考虑,上述焊球的焊料从共晶焊发展到了无铅焊。由于无铅焊焊料的熔点高于共晶焊焊料的熔点,因此,如果采用无铅焊焊接,在连接时就需要温度设定得高于共晶焊焊接的温度。另外,还有这样一种结构的半导体器件,即:在焊球端子的中心部具备铜等的金属球或树脂等的树脂球,在半导体器件被搭载至安装基板后,半导体器件与安装基板之间保持一定值以上的间隙。
以上是BGA型封装形状的半导体器件的结构。即使是尺寸比较接近所谓CSP的半导体芯片尺寸的半导体器件有时也采用与上述相同的结构。此外,还有下述的半导体器件,即:在涂敷焊膏后使其熔化并形成0.1mm以下的外部端子,而并非用钎焊等的金属球来形成外部端子的半导体器件;不进行钎焊,仅形成基板的金属焊盘的LGA(平面栅格阵列)型封装形状的半导体器件。
在将上述半导体器件搭载至安装基板时,一般采用下述的方法,即:在对安装基板供给焊膏和焊剂后,载置上述半导体器件(封装),并利用回流炉等的加热装置来熔化由焊料形成的外部端子,从而连接上述半导体器件和安装基板。如上所述,近年来,出于对环境保护的考虑,上述焊球的焊料从共晶焊发展到了无铅焊。因此,在将上述半导体器件搭载至安装基板时的温度存在上升的倾向。具体而言,由于焊料从共晶焊发展为无铅焊,因此,基板安装时的回流焊温度存在上升20~30度的倾向。
如上所述,在制造BGA型封装形状的半导体器件时,大多采用借助于回流炉等的加热炉来熔化用于外部端子的焊料从而形成外部端子的方法。另外,如上所述,在将BGA、LGA型封装形状的半导体器件搭载至安装基板时也较多地采用在回流炉等的加热炉中一并熔化其他部件和焊料从而进行搭载的方法。近年来,出于对环境保护的考虑,焊料从共晶焊变更为无铅焊的情况较多,与此相应地,由加热炉加温的温度存在升高的倾向。
因此,就要求半导体器件不会因所赋予的热量而出现不佳状况。具体而言,如图5中的下图所示,半导体器件(半导体封装)内部所吸收的水分固所赋予的热量而发生膨胀,由此,封装内部鼓起从而导致上述“因所赋予的热量而出现的不佳状况”。通过将半导体芯片搭载于配线基板上并利用树脂实施密封所得到的半导体器件存在这样一种倾向,即:组装后所吸收的水分将会积存在以半导体芯片与配线基板之间的粘合部分为中心的各材料间的界面附近。其中,上述所吸收的水分大多将积存在半导体芯片与配线基板之间的界面部分。因此,半导体芯片搭载部分之下的配线基板部分最容易因在焊球搭载时或将半导体芯片安装至安装基板时所赋予的回流炉的热量而发生膨胀。使用较薄的配线基板制成的半导体器件更容易出现上述倾向。如果在半导体芯片的搭载部分之下的配线图形中存在堵塞的部分,那么,就大多以该堵塞部分为起点发生上述基板膨胀现象。
如上所述,半导体器件因内部所吸收的水分发生膨胀而出现下述不佳情况,即:半导体器件的外观发生变形而成为劣品,或者不能实施安装,或者内部配线断裂。因此,就要求半导体器件不会出现上述不佳状况。
特别是在配线基板较薄的半导体器件(半导体封装)中,配线基板的半导体芯片搭载区域发生膨胀的区域更为严重,这不利于实现半导体器件的薄型化和小型化。
为了解决上述问题,例如,在专利文献2(日本国专利申请公开特开2001-15628,2001年1月19日公开)中揭示了一种具有下述结构的半导体器件101,即:如图6所示,在半导体芯片搭载区域20所对应的配线基板81的一部分中设置排气用通孔(排气孔)11,封装内积存的水分可由此排出。
但是,在上述可借助于排气用通孔11排出积存于封装内的水分的半导体器件101中,由于设置排气用通孔11,因此,需要确保用于在配线基板81中设置通孔11的区域。所以,这将影响半导体器件所必需的配线布置等。以具体数字表示如下,就目前可实现量产的水平而言,如果通孔11的直径为0.1mm,通孔11与附近的配线之间的距离就需要可确保下述三者的余量,即:通孔的位置精度、阻焊层不会覆盖通孔的距离、阻焊层能可靠地覆盖附近的配线的距离。因此,大约0.3mm的区域成为不能实施配线的区域。如果过于苛刻地要求上述余量,那么,配线基板81的制造成本就会上升,反之,不能实施配线的区域就会增大。
另外,由于在形成配线基板81后还要追加设置上述通孔11,所以,这也将导致配线基板81的制造成本上升。
此外,也可以考虑将半导体芯片搭载区域的金属形成为全图形,或者,也可以不形成金属图形,但是,在这种情况下,半导体芯片与配线基板之间的密合性就会变得过高。所以,封装内积存的水分就会积存在半导体芯片搭载区域之外的部分,因此,就会以上述积存水分的部分为起点发生膨胀。
另外,作为另一方法,有时也会采用这样的方式,即:在用片式粘合剂将半导体芯片粘合到配线基板的结构的半导体器件中,为了提高半导体芯片和配线基板之间的密合性而需要减少配线基板侧的凹凸,为此,通过反复涂敷阻焊层来减小其下面的配线图形的凹凸所带来的影响。但是,在这种情况下,在配线基板的制造工序中要反复实施阻焊层涂布工序,这将导致增加配线基板的制造工序从而造成成本的上升。
此外,还有人提出了诸如在由配线基板组装至半导体封装之前对积存的水分进行加热或减压从而除去该水分等的方法,但是,均会导致配线基板制造成本或安装成本的升高。
发明内容
本发明是鉴于上述问题而进行开发的,其目的在于提供一种以简单的结构而不导致成本升高就能够地防止半导体器件内部的水分的气化膨胀的配线基板以及半导体器件。
为了实现上述目的,本发明的配线基板为,在配线基板的和具备用于搭载半导体芯片的搭载区域的面相反一侧的面上设置有外部连接端子,其特征在于,在上述搭载区域配置有假线,该假线所包含的配线的末端在上述搭载区域内呈开放的形状。
根据上述结构,在搭载半导体芯片的搭载区域内形成的假线所包含的配线的末端在搭载区域内开放,因此,在上述配线基板上搭载了半导体芯片的情况下,上述假线不会在所搭载的半导体芯片下形成堵塞的部分。如果存在堵塞的部分,水分就会发生积存。但是,本发明采用了不会形成堵塞的部分的结构,即,水分不会集中地积存于半导体芯片和配线基板之间的结构。基于此,即使在被加热时,也可以防止半导体器件因水分膨胀而出现不佳的情况。这样,通过配置上数形状的假线,以简单的结构而不导致成本升高就能够地防止半导体器件因水分膨胀而发生不佳情况。具体而言,可以防止发生下述不佳的情况,即:半导体器件的外观发生变形而成为劣品,或者不能安装至安装基板,或者内部配线图形出现断线。因此,通过采用上述结构的配线基板,就能得到可靠的高品质的半导体器件。另外,只要上述搭载区域中的假线形成为所包含的所有配线的末端在搭载区域内开放的形状,就能可靠地防止因水分膨胀而发生的不佳情况。
本发明的其他目的、特征和优点在以下的描述中会变得十分明了。此外,以下参照附图来明确本发明的优点。
附图说明
图1是本发明的一个实施方式的配线基板的平面图。
图2是本发明的一个实施方式的半导体器件的剖面图。
图3(a)、图3(b)、图3(c)分别是本发明的一个实施方式所用的配线基板的平面图。
图4(a)、图4(b)、图4(c)、图4(d)分别是本发明的另一实施方式所用的配线基板的平面图。
图5是现有技术的半导体器件的剖面图,用于说明现有技术的半导体器件中所存在的问题。
图6是设置有排气用通孔的现有技术的半导体器件的剖面图。
具体实施方式
下面,根据图1至图4来说明本发明的一个实施方式。如图1所示,在本实施方式中,在配线基板8的内层基板上配置有信号配线图形(信号配线),并且,在半导体芯片搭载区域(搭载区域、半导体芯片搭载下部)2中设置有假线(dummy wiring)(假线图形)6。信号配线图形由信号配线图形4、信号配线图形5和信号配线图形3构成,其中,信号配线图形4是用于配置通孔的金属焊盘部,该通孔用于导通配线基板的上、下面,信号配线图形5是引线键合连接部,信号配线图形3连接信号配线图形5和信号配线图形4。另外,在图1中,未图示配线基板8的与半导体芯片搭载面(具备半导体芯片搭载区域2的面)相反一侧的面(外部连接端子搭载面)。在该外部连接端子搭载面上形成有作为外部连接端子搭载区域的信号配线图形。以下,在未区分上述信号配线图形和假线时,仅称之为配线图形。另外,信号配线图形4和上述外部连接端子搭载面的上述外部连接端子搭载区域通过后述的通孔(未图示)进行电连接。在上述外部连接端子搭载面上,可以使上述外部连接端子搭载区域堵塞上述通孔,在上述通孔和上述外部连接端子搭载区域之间也可以是通过实施配线所形成的配线图形。
作为配线基板8的内层基材,只要是绝缘材料即可,例如,可以举出在玻璃纤维中浸润环氧树脂所得到的绝缘材料。另外,厚度在0.2mm以下的内层基板为主流基板,但是,内层基板的厚度并不限于此。另外,作为配线基板8的内层基材,例如,可以举出聚酰亚胺、由浸润环氧树脂的玻璃纤维布制成的环氧树脂基板、芳族聚酰胺树脂基板等。在本实施方式中,配线基板8是在其内层基材的两面贴合铜箔所得到的两面覆铜的配线基板。
如上所述,在本实施方式中,用于上、下面实现电导通的通孔开口在配线基板8上。该通孔被设置在信号配线图形4之下,其中,信号配线图形4是用于配置通孔的金属焊盘部。作为通孔的开口方法,可以举出穿孔器加工和激光加工。关于通孔的直径,例如,可以为直径0.2mm以下,但是,本发明不限于此。在通孔的内周部实施镀铜,由此,可以实现配线基板8的上、下面的由铜箔构成的配线图形的电导通。
接着,说明配线图形的形成。首先,在上述设置有通孔的配线基板8的上、下两面贴合铜箔,并在该上、下两面的铜箔上贴附用于形成图形的干膜。然后,借助于掩膜图形实施定位并曝光,通过腐蚀来形成干膜的图形。之后,根据干膜的图形,对配线基板8的基材的上、下两面的铜箔进行腐蚀加工从而形成配线图形。
以上,说明了通过金属面腐蚀法(subtractive method)由铜箔形成配线图形的图形形成方法,其中,该配线图形包括信号配线图形3、4、5和假线6。但是,包括信号配线图形3、4、5和假线6的配线图形的形成方法并不限于此,例如,也可以采用下述添加法(additivemethod)或半添加法(semiadditive method),即:对上、下两面残留有薄层的铜箔的基板或完全不存在铜箔的基板实施通孔加工,然后,通过实施镀铜来确保信号配线图形和通孔内部的电导通。
另外,关于信号配线图形3、4、5和假线6的厚度,基本上为10μm~20μm,但是,根据信号配线图形3、4、5和假线6的密度,有时会变得更薄或者更厚。
在本实施方式中,除半导体器件实际使用的配线部分(信号配线图形3、4、5)外还配置有假线6。具体而言,如图1所示,假线6分别从半导体芯片搭载区域2的中央部分朝向配线基板8的周围的四个边,形成为配线与间隔交替排列的图形。由此,在半导体芯片1之下形成非堵塞的图形。另外,以与半导体器件实际上使用的(信号配线图形3的)配线宽度、配线间隔相同的配线密度引出均匀的配线。这样,在将半导体芯片1搭载于配线基板8时,由于假线6的形状,在半导体芯片1之下的区域中不会形成容易积存水分的部分。并且,也不会出现半导体芯片1和配线基板8极端密合的部分。因此,在半导体芯片搭载区域2中水分均匀地分布。由此,能够分散水分因在焊球搭载时或在将半导体器件搭载至安装基板时赋予的热量发生气化膨胀所形成的力。从而能够抑制下述发生在半导体器件内的膨胀。
如上所述,在配线基板8上,形成于半导体芯片搭载区域2的假线6的形状为:在半导体芯片搭载区域2内,所包括的所有配线的末端均为开放状态。因此,在搭载了半导体芯片1后,在半导体芯片1之下不会形成堵塞的部分。如果存在堵塞的部分,水分就会发生积存,但是,由于没有形成堵塞的部分,所以,水分不会集中地积存于半导体芯片1和配线基板8之间。基于此,即使在被加热时,由于未发生水分的积存或者说水分已经被排出,所以,可以防止半导体器件因水分膨胀而出现不佳的情况。具体而言,可以防止发生下述不佳的情况,即:半导体器件的外观发生变形而成为劣品,或者不能安装至安装基板,或者内部配线图形出现断线。通过形成上述形状的假线6,能够以简单的结构并不导致成本升高地防止止半导体器件因水分膨胀而出现不佳的情况。另外,在本实施方式中,假线6所包括的所有配线的末端在半导体芯片搭载区域2内呈开放的形状,因此,能够更可靠地防止发生因水分膨胀所导致的不佳情况。
因此,使用上述配线基板8,可以制造高可靠性、高品质的半导体器件。
另外,在半导体芯片搭载区域2中具有信号配线图形3(的一部分)并且具有信号配线图形4的情况下,优选均匀地配置半导体芯片搭载区域2的信号配线图形4。其中,信号配线图形4是用于配置通孔的金属焊盘部,该通孔用于导通配线基板的上下面。并且,如果在信号配线图形4之外的部分中配置假线6,就能更好地防止热膨胀。
另外,在半导体芯片搭载区域2中未配置作为半导体器件实际使用的配线的信号配线图形3、4的情况下,优选配置为:假线6自半导体芯片搭载区域2朝配线基板8的周围的四个方向延伸。
另外,由于假线6邻接作为金属焊盘部的信号配线图形4,因此,可增加水分在加热时排出的路径,能防止发生加热时发生膨胀。能够更好地防止加热所导致的不佳状况的发生。
此外,在上述配线基板8的两面设置有配线图形,但是,也可以仅在半导体搭载面上设置配线图形。在这种情况下,设置有配线图形的半导体搭载面的金属焊盘部通过其下方的通孔来连接外部连接端子。
接着,说明图2所示的封装形状的半导体器件20的制造方法,该半导体器件20使用了上述配线基板8。另外,在本实施方式中,用图2所示的BGA型封装形状的半导体器件20进行阐述。如果在与具有半导体芯片搭载区域20的面相反一侧的面上设置有外部连接端子,那么,也可以是其他形状的半导体器件。
如上所述形成配线基板8,然后,在上、下面的信号配线图形上涂布阻焊层,但是,作为引线键合连接部的信号配线图形8以及配线基板8的与半导体芯片搭载面1相反一侧的面上的外部连接端子用的金属焊盘部除外。可以采用丝网印刷法来涂布上述阻焊层,也可以采用滚涂器法来涂布上述阻焊层。
接着,将半导体芯片1搭载至配线基板8的半导体芯片搭载区域2,其中,在半导体芯片1的与电路形成面相反一侧的面上具有片式粘合材料。这里,半导体芯片1的厚度并无特别限制,例如,可以是0.33mm。另外,在半导体芯片的电路形成面上设置的焊盘部和配线基板8的作为引线键合端子部的信号配线图形5通过金属丝(引线)7来连接。接着,为了保护半导体芯片1和金属丝7,通过传送模法用树脂10对其进行树脂密封。进而,对配线基板8的与实施了树脂密封的半导体芯片搭载面相反一侧的面上的作为外部连接端子用金属焊盘部的信号配线图形涂布焊剂,然后,分别在上述作为外部连接端子用金属焊盘部的信号配线图形上配置并搭载焊球,用回流炉进行加热,熔化并固定焊球,从而形成外部连接端子9。焊球采用无铅的焊球,但是并不限于此。最后,进行切割,并完成半导体器件的组装。
根据上述半导体器件20,由于在半导体芯片1下不积存水分或者水分被排出,所以,即使在形成外部端子9以及安装至安装基板时被赋予热量,也能够防止半导体器件因水分膨胀而发生的不佳状况。在无铅焊的情况下,由于其熔点高于共晶焊的熔点,因此,连接时的温度也要高于共晶焊,但是,半导体器件不会出现因水分膨胀所导致的不佳状况。所以,可得到可靠的高品质的半导体器件。
(实施例)
制成上述具有图1所示形状的假线6的配线基板8,并对其进行验证。
为了确认上述具有图1所示形状的假线6的配线基板8的效果,将其和具有其他形状的假线的配线基板进行了比较。图3(a)~图3(c)表示具备其他形状的假线的配线基板。图3(a)所示的配线基板的半导体芯片搭载区域2中的假线形状为块状。图3(b)所示的配线基板的半导体芯片搭载区域2中的假线形成为实配线(solid wiring),在该实配线中形成有孔洞。图3(c)所示的配线基板的半导体芯片搭载区域2中的假线形状为网格状。
即,在图3(b)和图3(c)所示的配线基板上,假线形成为在半导体芯片下堵塞的形状。
制成分别在实际信号配线图形(使信号通过的配线图形)之外的区域中配置了图1、图3(a)~图3(c)所示的假线的配线基板。另外,在本实施例中,以相同的条件制成所有的配线基板。在本实施例中,配线基板的内层基材采用了0.06mm的内层基材。此外,用金属面腐蚀法对信号配线图形和假线进行配线加工,使其形成15μm左右的膜厚。用穿孔加工法形成用于电导通的通孔,通孔的直径为0.1mm。另外,图1所示的形状的假线的线宽为50μm,配线之间的间隔为50μm。
然后,分别使用上述形成的配线基板来组装图2所示的封装形状的半导体器件。另外,在本实施例中,在组装半导体器件时,在涂布阻焊层时,采用了丝网印刷法。半导体芯片1采用了厚度为0.33mm的半导体芯片。金属丝7采用了直径为25μm的金丝。密封树脂10采用了环氧系的树脂。作为外部连接端子9的焊球采用了无铅焊球。除配线基板之外,所有半导体器件的上述组装条件均相同。
将上述组装完毕的半导体器件置于高温高湿条件下保管,然后,用回流炉对其进行加热。在本实施例中,加热是在260~300度(最大)的条件下进行的。反复实施上述步骤,并比较上述具备假线互不相同的配线基板的半导体器件之间的优劣。另外,上述半导体器件的保管、加热条件完全相同,并且上述步骤的反复次数相同(对于发生了不佳情况的半导体器件就不再反复实施上述步骤)等。其结果,其配线基板具备图1所示的假线的半导体器件即使被反复实施了三次回流加热,也并没有出现不佳的情况。也就是说,该半导体器件并没有因内部所吸收的水分发生膨胀而出现下述不佳情况,即:半导体器件的外观发生变形而成为劣品,或者不能实施安装,或者内部配线断裂。
与上述半导体器件不同的是,在其配线基板具备别的形状的假线的半导体器件被确认发生了不佳的情况。较之于其配线基板具备图3(b)所示的假线的半导体器件和其配线基板具备图3(c)所示的假线的半导体器件,在其配线基板具备图3(a)所示的假线的半导体器件中发生的不佳情况比较轻微。
这里,关于具备图1所示假线的配线基板和具备图3(a)所示的假线的配线基板,两者的假线均为下述形状:所包含的所有假线的末端开放的形状。即,假线在半导体芯片下未被堵塞的形状。另一方面,在图3(b)和图3(c)所示的配线基板晌,假线在半导体芯片下形成被堵塞的形状。由此可知,通过配置所包括的所有配线末端开放的形状的假线,就可以避免发生或者减轻因半导体器件内部吸收的水分发生膨胀所导致的不佳情况。具体而言,可以避免发生或者减轻下述不佳情况,即:半导体器件的外观发生变形而成为劣品,或者不能实施安装,或者内部配线断裂。
根据其配线基板具备图1所示假线的半导体器件和其配线基板具备图3(a)所示假线的半导体器件的上述保管、加热结果,可知:当假线及信号配线图形在半导体芯片搭载区域内所占据的区域和未配置该假线及信号配线图形的区域之比大致相等时,就不会上述不佳情况。
另外,例如,图4中表示一种能够取得与具备图1所示的假线的配线基板8相同的效果的配线基板,即,不会发生不佳情况的配线基板。图4(a)所示的配线基板的半导体芯片搭载区域2中的假线组合了字母“X”和“V”的形状,图4(b)所示的配线基板的半导体芯片搭载区域2中的假线呈放射状。图4(a)及图4(b)所示的假线形成为下述的图形,即:按照与器件实际使用的配线线宽、配线间隔相同的配线密度,从半导体芯片搭载区域2的中央部分朝左上、左下、右上、右下方向引出配线。图4(c)所示的配线基板的半导体芯片搭载区域2中的假线呈漩涡状,图4(d)所示的配线基板的半导体芯片搭载区域2中的假线形成为沿着相同方向排列的条纹状。当然,上述只是单纯的示例,只要在配线基板上假线6被配制成所包括的所有配线的末端在半导体芯片搭载区域内开放的形状,就能够取得和上述图1所示的配线基板相同的效果。
如上所述,在本发明的配线基板的和具备用于搭载半导体芯片的搭载区域的面相反一侧的面上设置有外部连接端子,本发明的配线基板的特征在于,在上述搭载区域配置有假线,上述搭载区域所包含的配线的末端在上述搭载区域内呈开放的形状。
另外,在上述配线基板中,可均等地设置上述假线的配线线宽和配线间隔。
根据上述结构,搭载半导体芯片的搭载区域中的假线的配线线宽和配线间隔均等。在半导体芯片的搭载区域中,形成配线线宽和配线间隔均等的假线,不配置大面积的配线图形,由此,在搭载了半导体芯片的情况下,能够使得假线与半导体芯片的粘合性分布均匀。如果配置有大面积的配线图形,该部分的粘合性增强,因此,与其他部分之间的平衡就会恶化,从而容易在其他部分发生基板膨胀。但是,根据本发明的上述结构,假线容易均匀地与半导体芯片粘合。因此,能够制造一种高稳定性的半导体器件。
另外,在上述配线基板中,上述假线可以形成为从上述搭载区域的至少一点朝上述搭载区域外的方向延伸的形状。
根据上述结构,假线被配置成从半导体芯片搭载区域内的至少一点朝该搭载区域外的方向延伸的形状。因此,在半导体芯片搭载区域中,能够使假线形成为下述的图形,即:半导体芯片与基板之间的粘合力不会过强,并且,水分在半导体芯片之下均匀地分布而不会集中在某一位置。
另外,在上述配线基板中,在上述搭载区域内,包括上述假线在内的全配线所占据的区域和未配置上述全配线的配线间隔所占据的区域之比可以是40∶60~60∶40。
根据上述结构,在半导体芯片搭载区域内,全配线所占据的区域和配线间隔所占据的区域之比是40∶60~60∶40。即,比例大致相等。这样,在半导体芯片搭载区域内,存在配线的区域和不存在配线的区域之比大致相等,由此,可以均匀地粘合半导体芯片和配线,并且,不使其粘合力变得过强。
另外,上述全配线所占据的区域和上述配线间隔所占据的区域之比是指,在半导体芯片搭载区域内不存在信号配线(信号实际通过的配线)的情况下,仅由假线所占据的区域和未配置有假线的配线间隔所占据的区域之比。
另外,如上所述,在本发明的半导体器件中,在上述任一配线基板的搭载区域搭载半导体芯片,并在该配线基板的与具备搭载区域的面相反一侧的面上形成有外部连接端子。
根据上述结构,使用在半导体芯片搭载区域内形成了所包含的所有的配线的末端开放的形状的假线的配线基板来形成半导体器件。因此,在形成外部端子时,以及在将安装至安装基板时,即使被赋予了热量,由于水分未积存在半导体芯片下或者已被排出,因此,能够防止半导体器件发生因水分膨胀所导致的不佳情况。具体而言,能够防止发生这样的不佳情况,即:半导体器件的外观发生变形而成为劣品,或者不能实施安装,或者内部配线断裂。进而,作为外部连接端子,用无铅焊进行连接时的温度即使被设定得高于共晶焊时的温度,半导体器件也不会出现因水分膨胀所导致的不佳状况。所以,可得到可靠的高品质的半导体器件。
另外,本发明的配线基板可以是这样一种半导体封装用配线基板,在配线基板的上面侧具备用于搭载一个以上的半导体芯片的区域和用于实施引线键合连接的连接电极,在配线基板的下面侧具备用于外部连接用端子的焊盘,在搭载了半导体芯片的情况下,半导体芯片搭载部之下的信号配线之外的配线在半导体芯片搭载部之下未堵塞。
另外,还可以为:在上述配线基板上,半导体芯片搭载区域的信号线之外的配线从半导体芯片搭载部之下的至少一点或多个点朝半导体芯片外侧方向延伸。
另外,还可以为:在上述配线基板上,在半导体芯片搭载区域内的信号线之外的配线和配线间隔所占据的区域之比是40~60∶60~40。
另外,本发明的半导体器件可以是这样一种半导体封装,在上述任一配线基板的上面侧搭载半导体芯片,通过导电性的细丝来导通半导体芯片和配线基板,用树脂实施密封以覆盖半导体芯片和导电性细丝,在配线基板的下面侧形成有外部连接用端子。
本发明不限于上述具体实施方式,不应对本发明进行狭义的解释,可在本发明的精神和权利要求的范围内进行各种变更来实施之。通过组合在权利要求范围内适当变更的技术手段所得到的实施方式也包含在本发明的技术范围内。
本发明可应用于诸如电子设备所搭载、内置的半导体器件,并对薄型化的半导体器件以及基于环保需要外部端子采用了无铅焊的半导体器件特别有效。
Claims (6)
1.一种配线基板,在和具备用于搭载半导体芯片的搭载区域的面相反一侧的面上设置有外部连接端于,其特征在于:
在上述搭载区域配置有假线,该假线所包含的配线的末端在上述搭载区域内呈开放的形状。
2.根据权利要求1所述的配线基板,其特征在于:
均等地设置上述假线的配线线宽和配线间隔。
3.根据权利要求1所述的配线基板,其特征在于:
上述假线形成为从上述搭载区域内的至少一点朝上述搭载区域外的方向延伸的形状。
4.根据权利要求1所述的配线基板,其特征在于:
在上述搭载区域内,包括上述假线在内的全配线所占据的区域和未配置上述全配线的配线间隔所占据的区域之比为40∶60~60∶40。
5.一种配线基板,在和具备半导体芯片搭载区域的面相反一侧的面上设置有外部连接端子,其特征在于:
在上述半导体芯片搭载区域配置有假线,上述假线形成为在搭载上述半导体芯片后不会在半导体芯片下发生堵塞的形状。
6.一种半导体器件,在搭载有半导体芯片的配线基板的和具备半导体芯片搭载区域的面相反一侧的面上形成有外部连接端子,其特征在于:
在上述配线基板的上述半导体芯片搭载区域配置有假线,该假线所包含的配线的末端在上述半导体芯片搭载区域内呈开放的形状。
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JP2006019078A JP4312766B2 (ja) | 2006-01-27 | 2006-01-27 | 半導体装置 |
JP2006019078 | 2006-01-27 |
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US (1) | US7876572B2 (zh) |
JP (1) | JP4312766B2 (zh) |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101740709A (zh) * | 2008-11-18 | 2010-06-16 | 斯坦雷电气株式会社 | 光半导体装置及其制造方法 |
Families Citing this family (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7426780B2 (en) * | 2004-11-10 | 2008-09-23 | Enpirion, Inc. | Method of manufacturing a power module |
US8701272B2 (en) | 2005-10-05 | 2014-04-22 | Enpirion, Inc. | Method of forming a power module with a magnetic device having a conductive clip |
US8631560B2 (en) * | 2005-10-05 | 2014-01-21 | Enpirion, Inc. | Method of forming a magnetic device having a conductive clip |
US7688172B2 (en) * | 2005-10-05 | 2010-03-30 | Enpirion, Inc. | Magnetic device having a conductive clip |
US8139362B2 (en) * | 2005-10-05 | 2012-03-20 | Enpirion, Inc. | Power module with a magnetic device having a conductive clip |
US8133529B2 (en) * | 2007-09-10 | 2012-03-13 | Enpirion, Inc. | Method of forming a micromagnetic device |
US7920042B2 (en) | 2007-09-10 | 2011-04-05 | Enpirion, Inc. | Micromagnetic device and method of forming the same |
JP5071035B2 (ja) * | 2007-10-19 | 2012-11-14 | セイコーエプソン株式会社 | 圧電デバイス |
US8541991B2 (en) | 2008-04-16 | 2013-09-24 | Enpirion, Inc. | Power converter with controller operable in selected modes of operation |
US9246390B2 (en) | 2008-04-16 | 2016-01-26 | Enpirion, Inc. | Power converter with controller operable in selected modes of operation |
US8686698B2 (en) | 2008-04-16 | 2014-04-01 | Enpirion, Inc. | Power converter with controller operable in selected modes of operation |
US8692532B2 (en) | 2008-04-16 | 2014-04-08 | Enpirion, Inc. | Power converter with controller operable in selected modes of operation |
US9054086B2 (en) * | 2008-10-02 | 2015-06-09 | Enpirion, Inc. | Module having a stacked passive element and method of forming the same |
US8266793B2 (en) * | 2008-10-02 | 2012-09-18 | Enpirion, Inc. | Module having a stacked magnetic device and semiconductor device and method of forming the same |
US8339802B2 (en) * | 2008-10-02 | 2012-12-25 | Enpirion, Inc. | Module having a stacked magnetic device and semiconductor device and method of forming the same |
US8153473B2 (en) | 2008-10-02 | 2012-04-10 | Empirion, Inc. | Module having a stacked passive element and method of forming the same |
US8698463B2 (en) * | 2008-12-29 | 2014-04-15 | Enpirion, Inc. | Power converter with a dynamically configurable controller based on a power conversion mode |
US9548714B2 (en) * | 2008-12-29 | 2017-01-17 | Altera Corporation | Power converter with a dynamically configurable controller and output filter |
US20100263914A1 (en) * | 2009-04-16 | 2010-10-21 | Qualcomm Incorporated | Floating Metal Elements in a Package Substrate |
US20100270061A1 (en) * | 2009-04-22 | 2010-10-28 | Qualcomm Incorporated | Floating Metal Elements in a Package Substrate |
JP4864126B2 (ja) * | 2009-08-26 | 2012-02-01 | ルネサスエレクトロニクス株式会社 | Tcp型半導体装置 |
US8531014B2 (en) * | 2010-09-27 | 2013-09-10 | Infineon Technologies Ag | Method and system for minimizing carrier stress of a semiconductor device |
US8867295B2 (en) | 2010-12-17 | 2014-10-21 | Enpirion, Inc. | Power converter for a memory module |
JP2012124479A (ja) * | 2011-11-24 | 2012-06-28 | Hitachi Chem Co Ltd | 半導体パッケージ |
KR101892689B1 (ko) | 2014-10-14 | 2018-08-28 | 삼성전기주식회사 | 칩 전자부품 및 칩 전자부품의 실장 기판 |
US9509217B2 (en) | 2015-04-20 | 2016-11-29 | Altera Corporation | Asymmetric power flow controller for a power converter and method of operating the same |
CN210519104U (zh) * | 2017-06-05 | 2020-05-12 | 株式会社村田制作所 | 线圈内置陶瓷基板 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08153824A (ja) | 1994-11-29 | 1996-06-11 | Nec Kyushu Ltd | ボール・グリッド・アレイ・パッケージ |
JP3176542B2 (ja) | 1995-10-25 | 2001-06-18 | シャープ株式会社 | 半導体装置及びその製造方法 |
JPH10214914A (ja) | 1997-01-28 | 1998-08-11 | Sony Corp | Bgaパッケージ及びその製造方法 |
JP4045648B2 (ja) | 1998-06-10 | 2008-02-13 | ソニー株式会社 | 半導体装置 |
JP3613098B2 (ja) | 1998-12-21 | 2005-01-26 | セイコーエプソン株式会社 | 回路基板ならびにそれを用いた表示装置および電子機器 |
JP3494593B2 (ja) | 1999-06-29 | 2004-02-09 | シャープ株式会社 | 半導体装置及び半導体装置用基板 |
TW468363B (en) | 2000-06-01 | 2001-12-11 | Siliconware Precision Industries Co Ltd | Substrate circuit layout structure |
JP4934915B2 (ja) | 2001-06-19 | 2012-05-23 | 富士通セミコンダクター株式会社 | 半導体装置 |
JP2003188306A (ja) | 2001-12-17 | 2003-07-04 | Sony Corp | 回路配線基板、その製造方法及びその回路配線基板を用いた半導体装置 |
JP2003188210A (ja) * | 2001-12-18 | 2003-07-04 | Mitsubishi Electric Corp | 半導体装置 |
JP4972306B2 (ja) * | 2004-12-21 | 2012-07-11 | オンセミコンダクター・トレーディング・リミテッド | 半導体装置及び回路装置 |
-
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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US20070176300A1 (en) | 2007-08-02 |
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