CN101002313A - 半导体装置 - Google Patents
半导体装置 Download PDFInfo
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- CN101002313A CN101002313A CNA2005800267666A CN200580026766A CN101002313A CN 101002313 A CN101002313 A CN 101002313A CN A2005800267666 A CNA2005800267666 A CN A2005800267666A CN 200580026766 A CN200580026766 A CN 200580026766A CN 101002313 A CN101002313 A CN 101002313A
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- electrode
- semiconductor chip
- face
- projected electrode
- semiconductor device
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Abstract
本发明提供一种半导体装置(1、21、31、31A),具备:固体装置(2、33),该固体装置具有连接面(2a、33a),在该连接面上突出形成有由金属制成的连接电极(13、46);半导体芯片(3、34),该半导体芯片具有功能面(3a、34a),在该功能面上突出形成有由金属制成的突起电极(13、46),使该功能面与所述固体装置的所述连接面相面对,并在所述功能面与所述连接面之间保持规定间隔(D3、D6、D9)而接合;连接部件(15、22、47),该连接部件含有具有比所述连接电极及所述突起电极的固相线温度更低的低熔点的金属,并连接所述固体装置的所述连接电极和所述半导体芯片的所述突起电极。在所述功能面与所述连接面的对置方向上,所述连接电极的高度(D1、D4、D7)与所述突起电极的高度(D2、D5、D8)之和为所述规定间隔的二分之一以上。
Description
技术领域
本发明涉及一种具有被倒装连接了的半导体芯片的半导体装置。
背景技术
为了实现半导体装置的小型化及高密度安装,将半导体芯片的形成了功能元件的功能面与固体装置相面对地将半导体芯片与固体装置连接的倒装芯片连接构造受到关注。
图7是表示具有倒装芯片连接构造的以往的半导体装置的构造的图解性剖面图。该半导体装置51包括:具有连接面52a的配线基板52;具有形成了功能元件的功能面53a,将该功能面53a与连接面52a相面对地连接了的半导体芯片53。
在配线基板52的连接面52a上,形成有由铜(Cu)制成的连接焊盘58。
在半导体芯片53的功能面53a上,形成有与功能元件连接的电极焊盘54。功能面53a由表面保护膜55覆盖,在该表面保护膜55上,形成有使电极焊盘54露出的开口55a。此外,在开口55a上,将电极焊盘54的从开口55a中的露出面覆盖地形成有扩散防止膜56。该扩散防止膜56的厚度如图7所示,比表面保护膜55的厚度更薄,扩散防止膜56实际上不会从电极焊盘54或扩散防止膜56的表面突出。
在配线基板52的连接焊盘58与半导体芯片53的扩散防止膜56之间,夹设有由锡(Sn)-铅(Pb)焊锡材料制成的球状的连接构件57。利用该连接构件57的夹设,就可以在与配线基板52保持规定间隔的状态下支承半导体芯片53,并且可以实现配线基板52与半导体芯片53的电连接。
由此,连接构件57通常来说在配线基板52与半导体芯片53的对置方向上,具有与连接焊盘58及扩散防止膜56相比相当大的厚度。
非专利文献1:J.D.Wu et al.,“Electromigration Reliability ofSnAgXCuX Flip Chip Interconnects”,54th.Electron.Components andTechnol.Conf.,2004,p.961
但是,在20℃下,锡的电阻率为12.8×10-8Ω·cm,铅的电阻率为20.6×10-8Ω·cm。所以,由锡一铅焊锡制成的连接构件57的电阻率就达到作为构成连接焊盘58的铜的电阻率的1.673×10-8Ω·cm的十倍左右。
由此,在如图7所示的半导体装置51那样,在连接焊盘58与电极焊盘54之间,夹设有与它们相比具有相当大的厚度的连接构件57的构成中,配线基板52与半导体芯片53之间的电阻就会变得很大。此种具有大电阻的半导体装置51由于动作速度慢,因此不适于应用到高速设备中。特别是,在配线基板52或半导体芯片53中形成有微细图案的配线(包括连接焊盘58或电极焊盘54。)的情况下,将无法忽视连接构件57的电阻。
发明内容
本发明的目的在于,提供一种可以降低固体装置与半导体芯片之间的电阻的半导体装置。
本发明的半导体装置具备:具有由金属制成的连接电极突出而形成的连接面的固体装置;具有由金属制成的突起电极突出而形成的功能面,使该功能面与所述固体装置的所述连接面相面对,在所述功能面与所述连接面之间保持规定间隔地接合的半导体芯片;含有比所述连接电极及所述突起电极的固相线温度更低的低熔点金属,将所述固体装置的所述连接电极与所述半导体芯片的所述突起电极连接的连接构件。在所述功能面与所述连接面的对置方向上,所述连接电极的高度与所述突起电极的高度的和为所述规定间隔的二分之一以上。
连接电极或突起电极例如可以设为由金(Au)、铜(Cu)、镍(Ni)等金属制成。另一方面,作为构成连接构件的金属材料,即,作为与连接电极及突起电极相比固相线温度更低的低熔点金属,例如可以举出锡、铅、铟或它们的合金,然而这些金属材料的电阻率都高于金、铜及镍的电阻率。
但是,根据本发明,通过在功能面与连接面的对置方向上,将连接电极的高度与突起电极的高度的和设为功能面与连接面的规定间隔的二分之一以上,就可以缩短由电阻率高的材料制成的连接构件的长度(厚度)。由此,就可以减少固体装置与半导体芯片之间的电阻。其结果是,可以使该半导体装置适用于高速设备中。
所述连接构件也可以含有所述低熔点金属与构成所述连接电极或所述突起电极的金属的合金(反应物)。
构成连接构件的金属材料的固相线温度例如优选60℃至370℃。
固体装置的连接面与半导体芯片的功能面之间最好被树脂材料密封。利用该树脂材料,可以保护功能面或连接构件与连接电极及突起电极的连接部,并且可以减少沿着连接面或功能面的面内方向的剪切应力。
该半导体装置可以通过在固体装置的连接电极与半导体芯片的突起电极之间,夹设了低熔点金属的状态下,将固体装置及半导体芯片以规定时间加热为低熔点金属的固相线温度以上(优选液相线温度以上)的温度来获得。通过将低熔点金属加热为其固相线温度(液相线温度)以上的温度,就会产生低熔点金属的熔液,通过将该熔液固化,就可以获得连接构件。
这里,连接电极的高度例如也可以设为5μm~100μm,比以往的半导体装置(参照图7)的连接焊盘的高度(例如0.5μm~5μm)更大,突起电极的高度例如也可以设为5μm~100μm,比以往的半导体装置的扩散防止膜的高度(例如0.5μm~5μm)更大。另外,相对于表面积例如为0.0001mm2~0.25mm2的连接电极或突起电极,低熔点金属的体积例如在连接电极与突起电极相面对的区域中,被设为1×10-7mm3~0.08mm3(以往的半导体装置的连接构件的体积的一千分之一到四分之一左右)。这样,在功能面与连接面的对置方向上,就可以使得连接电极的高度与突起电极的高度的和在功能面与连接面的规定间隔的二分之一以上。
所述连接电极也可以具有与所述半导体芯片相面对的上面、基本上沿着所述固体装置与所述半导体芯片的对置方向的侧面,该情况下,所述突起电极也可以具有与所述固体装置相面对的上面、基本上沿着所述固体装置与所述半导体芯片的对置方向的侧面,该情况下,所述连接电极的上面及侧面以及所述突起电极的上面及侧面的大致全部区域也可以被所述连接构件覆盖。
根据该构成,可以提高该半导体装置的可靠性,并且可以提高连接电极与突起电极之间的连接强度。
另外,在连接电极或突起电极具有上面及侧面的情况下,在该半导体装置的制造工序中,通过将连接电极或突起电极的上面及侧面设为由低熔点金属的熔液覆盖的状态,就可以有效地利用该熔液的表面张力,相对于固体装置将半导体芯片沿与对置方向正交的方向进行自对准。
所述连接构件也可以被配置为将所述连接电极和所述突起电极之间填充,含有由构成所述连接电极或所述突起电极的金属与所述低熔点金属的合金制成的反应层。
锡、铅、铟或它们的合金比金、铜或镍更为柔软。所以,当在连接电极与突起电极之间,存在仅由连接构件当中的低熔点金属构成的部分时,由于该部分比连接电极或突起电极更为柔软,因此应力很容易集中于该部分而使连接构件断裂。
另一方面,根据该构成,连接电极与突起电极之间被由构成连接电极或突起电极的金属和低熔点金属的合金构成的反应层填充。此种合金比低熔点金属更硬,连接电极及突起电极与存在于它们之间的连接构件(反应层)的硬度的差很小。所以,就可以避免应力集中于连接电极与突起电极之间的情况,使得连接构件难以断裂。
当所述连接电极具有上面及侧面时,或所述突起电极具有上面及侧面时,除了所述连接电极及所述突起电极的上面以外,也可以将所述连接电极及所述突起电极的侧面用所述反应层覆盖。
在所述的制造方法中,通过控制加热固体装置及半导体芯片的温度及时间,就可以在低熔点金属的熔液固化后,形成连接电极与突起电极之间由反应层填充的状态。
所述连接电极与所述突起电极最好由相同的材料制成。该情况下,对于连接构件,连接电极侧和突起电极侧的材料构成形成对称,可以提高连接可靠性。
固体装置也可以是配线基板,该情况下,连接电极也可以是与配线基板上的配线连接的连接焊盘。
另外,所述固体装置也可以是与所述半导体芯片不同的半导体芯片。即,该半导体装置也可以具有chip-on-chip构造。该情况下,连接面也可以是形成了功能元件的功能面,连接电极也可以是突起电极。
所述连接电极及所述突起电极也可以使各自的高度不同地形成,使得所述连接电极与所述突起电极的连接部分的位置靠近所述半导体芯片侧或所述固体装置侧。
该半导体装置中,也可以在半导体芯片的功能面与固体装置的连接面(其他的半导体芯片的功能面)之间,设置底部填充胶层(underfill)。当对此种半导体装置施加温度循环时,因连接电极、突起电极及连接构件(以下将它们总称为「导电构件」。)的热膨胀系数与底部填充胶层的热膨胀系数的差,就会对导电构件施加应力。该应力在与功能面及连接面垂直的方向上,在相面对的功能面与连接面的中间部达到最大。
另一方面,突起电极与连接电极(其他的半导体芯片的突起电极)的连接部分(连接构件)处于从对导电构件施加的应力达到最大的位置(相面对的功能面与连接面的中间部)向固体装置侧或半导体芯片侧靠近(偏移)的位置。所以,即使设置此种底部填充胶层,也很难引起由温度循环造成的突起电极与连接电极的连接部的破坏。
本发明的所述的或者其他的目的、特征及效果将参照附图由下述的实施方式的说明来阐明。
附图说明
图1是表示本发明的第一实施方式的半导体装置的构造的图解性剖面图。
图2是将图1所示的半导体装置的导电构件附近放大表示的图解性剖面图。
图3是表示本发明的第二实施方式的半导体装置的构造的图解性剖面图。
图4是表示本发明的第三实施方式的半导体装置的构造的图解性剖面图。
图5是将图4所示的半导体装置的导电构件附近放大表示的图解性剖面图。
图6是将图4所示的半导体装置的变形例的半导体装置的导电构件附近放大表示的图解性剖面图。
图7是表示具有倒装连接构造的以往的半导体装置的构造的图解性剖面图。
具体实施方式
图1是表示本发明的第一实施方式的半导体装置的构造的图解性剖面图。
该半导体装置1包括:具有连接面2a的配线基板2;具有形成了功能元件的功能面3a,使该功能面3a与连接面2a相面对地连接(倒装连接)的半导体芯片3。配线基板2与半导体芯片3由导电构件5保持规定间隔地相互机械地连接。另外,配线基板2与半导体芯片3被借助导电构件5电连接。
在配线基板2与半导体芯片3的间隙中,设有由树脂材料构成的底部填充胶层7。利用底部填充胶层7,可以保护功能面3a或导电构件5,并且可以减少沿着连接面2a或功能面3a的面内方向的剪切应力。
在配线基板2中与连接面2a相反一侧的外部连接面2b上,设有金属球4。金属球4在配线基板2的内部及/或表面被再次配线,与连接面2a侧的导电构件5电连接。该半导体装置1可以借助金属球4与安装基板连接。
图2是将半导体装置1的导电构件5附近放大表示的图解性剖面图。
在配线基板2的连接面2a上,形成有连接焊盘10。连接焊盘10例如由金(Au)、铜(Cu)、镍(Ni)或它们的合金制成,利用未图示的配线与金属球4(参照图1)连接。
在半导体芯片3的功能面3a上,形成有与功能元件连接的电极焊盘11。电极焊盘11例如由铝、铜、金或它们的合金制成。另外,功能面3a由表面保护膜12覆盖,在该表面保护膜12上,形成有使电极焊盘11露出的开口12a。表面保护膜12例如由硅氮化膜、硅氧化膜、聚酰亚氨制成。
在电极焊盘11从开口12a中的露出面上,形成有从表面保护膜12的表面中突出的突起电极13。突起电极13例如由金、铜、镍或它们的合金制成。
连接焊盘10具有与半导体芯片3(突起电极13)相面对的上面10a及大致上沿着配线基板2与半导体芯片3的对置方向的侧面10b。同样地,突起电极13具有与配线基板(连接焊盘10)相面对的上面13a及大致上沿着配线基板2与半导体芯片3的对置方向的侧面13b。突起电极13具有与连接焊盘10大致相同的大小及形状。在垂直地向下俯视连接面2a时,连接焊盘10与突起电极13被大致重合地配置。
连接焊盘10和突起电极13由连接构件15连接。连接构件15包括:作为与连接焊盘10、突起电极13等半导体装置1的其他的构件相比固相线温度更低的低熔点金属的锡(Sn)、铅(Pb)、铟(In)或它们的合金。连接构件15在与连接焊盘10或突起电极13的界面附近,包括由低熔点金属和构成连接焊盘10和突起电极13的金属的合金制成的反应层(未图示)。连接构件15除了反应层以外的部分,实质上仅由低熔点金属制成。
连接焊盘10的上面10a及侧面10b以及突起电极13的上面13a及侧面13b的大致全部区域由连接构件15覆盖。这样,就可以提高半导体装置1的可靠性,并且可以提高连接焊盘10与突起电极13之间的连接强度。
从连接面2a起的连接焊盘10的高度D1与从功能面3a起的突起电极13的高度D2的和为连接面2a与功能面3a的间隔D3的二分之一以上(参照下述数学式(1))。
D1+D2≥(1/2)·D3(1)
高度D1例如可以设为1μm~250μm,高度D2例如可以设为1μm~250μm。间隔D3例如可以设为2μm~500μm。
由低熔点金属,即,由锡、铅、铟或它们的合金制成的连接构件15与由金、铜或镍制成的连接焊盘10或突起电极13相比,电阻率更高。但是,根据所述数学式(1)的关系,在连接面2a与功能面3a的对置方向上,电阻率高的连接构件15的长度(厚度)小。所以,该半导体装置1的配线基板2与半导体芯片3之间的电阻低。由此,该半导体装置1适用于高速设备中。
连接焊盘10和突起电极13最好由相同的材料(例如铜)制成。该情况下,对于连接构件15,连接焊盘10侧与突起电极13侧的材料构成形成对称,从而可以提高连接可靠性。
该半导体装置1可以通过在配线基板2的连接焊盘10与半导体芯片3的突起电极13之间,夹设了低熔点金属的状态下,将配线基板2及半导体芯片3以规定时间加热为低熔点金属的固相线温度以上(优选液相线温度以上)的温度来获得。通过将低熔点金属加热为其固相线温度(液相线温度)以上的温度,就会产生低熔点金属的熔液,通过将该熔液固化,就可以获得连接构件15。
这里,通过适当地设定高度D1、D2或低熔点金属的体积,就可以获得具有所述(1)式的关系的半导体装置1。
另外,通过将连接焊盘10或突起电极13的上面10a、13a及侧面10b、13b设为以低熔点金属的熔液覆盖的状态,就可以有效地利用该熔液的表面张力,进行半导体芯片3相对于配线基板2的自对准。
图3是表示本发明的第二实施方式的半导体装置的构造的图解性剖面图。图3中,对于与图2所示的各部对应的部分,使用与图2相同的参照符号。
该半导体装置21具备连接构件22,而不是图2所示的半导体装置1的连接构件15。连接构件22包括:将连接焊盘10与突起电极13之间填充(充满),并将连接焊盘10的侧面10b与突起电极13的侧面13b覆盖地形成的反应层22a;将该反应层22a的侧方覆盖的未反应层22b。
未反应层22b实质上仅由与连接焊盘10、突起电极13等半导体装置21的其他的构件相比固相线温度更低的低熔点金属(锡、铅、铟或它们的合金)构成。另一方面,反应层22a由构成连接焊盘10或突起电极13的金属和低熔点金属的合金构成。
参照图2,作为锡、铅、铟或它们的合金的低熔点金属与金、铜及镍相比更为柔软。所以,当像半导体装置1那样,在连接焊盘10与突起电极13之间,存在连接构件15当中的实质上仅由低熔点金属构成的部分时,由于该部分比连接焊盘10或突起电极13更为柔软,因此应力容易集中于该部分而发生断裂。
针对于此,图3所示的半导体装置21中,连接焊盘10与突起电极13之间被反应层22a填充。由构成连接焊盘10或突起电极13的金属与低熔点金属的合金(既可以是共晶,也可以是固溶体,还可以是金属间化合物,还可以是它们当中的2种以上。)构成的反应层22a比低熔点金属更硬,连接焊盘10及突起电极13与存在于它们之间的反应层22a的硬度的差很小。所以,由于可以避免应力集中于连接焊盘10与突起电极13之间的情况,因此连接构件22就难以断裂。
该半导体装置21可以利用与图1及图2所示的半导体装置1相同的制造方法来制造。该制造方法中,通过控制加热配线基板2及半导体芯片3的温度及时间,就可以在低熔点金属的熔液固化后,将连接焊盘10与突起电极13之间设为用反应层22a填充了的状态。
图4是表示本发明的第三实施方式的半导体装置的构造的图解性剖面图。
该半导体装置31是所谓的多芯片模块,具备配线基板32、层叠于其上的第一半导体芯片33及层叠于第一半导体芯片33之上的第二半导体芯片34。第一及第二半导体芯片33、34分别具有各自形成了功能元件的功能面33a、34a。第一半导体芯片33在将功能面33a朝向了与配线基板32相反一侧的所谓面朝上(face up)的状态下,接合于配线基板32之上。
第二半导体芯片34以将功能面34a与第一半导体芯片33的功能面33a相面对的面朝下(face down)姿势,与第一半导体芯片33连接。即,该半导体装置31具有chip-on-chip构造。第一半导体芯片33与第二半导体芯片34被利用导电构件38保持规定间隔地相互机械地连接。另外,第一半导体芯片33与第二半导体芯片34被借助导电构件38电连接。在第一半导体芯片33与第二半导体芯片34的间隙中,设有底部填充胶层36。
从垂直于功能面33a、34a的方向看,第一半导体芯片33大于第二半导体芯片34,在第一半导体芯片33中连接了第二半导体芯片34的面(功能面33a)的周缘部,存在有不与第二半导体芯片34相面对的区域。在该区域中,形成有与功能面33a的功能元件连接了的电极焊盘33b。
从垂直于配线基板32的方向看,配线基板32大于第一半导体芯片33,在配线基板32中接合了第一半导体芯片33的面的周缘部,存在有不与第一半导体芯片33相面对的区域。在该区域中,设有未图示的电极焊盘,配线基板32的该电极焊盘与第一半导体芯片33的电极焊盘33b被借助焊丝37连接。
第一及第二半导体芯片33、34以及焊丝37被填充树脂39密封。
在配线基板32中与接合了第一半导体芯片33的一面相反一侧的面上,设有作为外部连接构件的焊锡球35。连接了配线基板32的焊丝37的电极焊盘在配线基板32的表面或内部被再次配线,与焊锡球35连接。
该半导体装置31可以通过将焊锡球35与形成于安装基板上的电极焊盘连接,来安装于安装基板上。
图5是将半导体装置31的导电构件38附近放大表示的图解性剖面图。
在第一半导体芯片33的功能面33a上,形成有与功能元件连接的电极焊盘41。另外,功能面33a被表面保护膜42覆盖,在该表面保护膜42上,形成有使电极焊盘41露出的开口42a。在电极焊盘41从开口42a中的露出面上,形成有从表面保护膜42的表面中突出的突起电极43。
同样地,在第二半导体芯片34的功能面34a上,形成有与功能元件连接的电极焊盘44。另外,功能面34a被表面保护膜45覆盖,在该表面保护膜45上,形成有使电极焊盘44露出的开口45a。在电极焊盘44从开口45a中的露出面上,形成有从表面保护膜45的表面中突出的突起电极46。
电极焊盘41、44由与图2所示的半导体装置1的电极焊盘11相同的材料制成。表面保护膜42、45由与图2所示的半导体装置1的表面保护膜12相同的材料制成。突起电极43、46由与图2所示的半导体装置1的突起电极13相同的材料制成。
突起电极43具有与第二半导体芯片34(突起电极43)相面对的上面43a及大致上沿着第一半导体芯片33和第二半导体芯片34的对置方向的侧面43b。同样地,突起电极46具有与第一半导体芯片33(突起电极43)相面对的上面46a及大致上沿着第一半导体芯片33和第二半导体芯片34的对置方向的侧面46b。突起电极43和突起电极46具有大致相同的大小及形状。在垂直向下的俯视时,突起电极43与突起电极46被大致重合地配置。
突起电极43与突起电极46由连接构件47连接。连接构件47由与图2所示的半导体装置1的连接构件15相同的材料制成。
突起电极43的上面43a及侧面43b以及突起电极46的上面46a及侧面46b的大致全部区域被连接构件47覆盖。这样,就可以提高半导体装置31的可靠性,并且可以提高突起电极43与突起电极46之间的连接强度。
从功能面33a起的突起电极43的高度D4与从功能面34a起的突起电极46的高度D5的和为功能面33a与功能面34a的间隔D6的二分之一以上(参照下述数学式(2))。
D4+D5≥(1/2)·D6(1)
即,在功能面33a与功能面34a的对置方向上,电阻率高的连接构件47的长度(厚度)小。所以,该半导体装置31的第一半导体芯片33与第二半导体芯片34之间的电阻低。
图6是表示图4及图5所示的半导体装置31的变形例的半导体装置的构造的图解性剖面图。图6中,对于与图5所示的各部对应的部分,使用与图5相同的参照符号。图6中,将导电构件38附近放大表示。
在该半导体装置31A中,从功能面33a起的突起电极43的高度D7与从功能面34a起的突起电极46的高度D8的和为功能面33a与功能面34a的间隔D9的二分之一以上(参照下述数学式(3))。
D7+D8≥(1/2)·D9(1)
另外,该半导体装置31A中,从功能面34a起的突起电极46的高度D8被设为大于从功能面33a起的突起电极43的高度D7(D7<D8)。
当对该半导体装置31A施加温度循环时,因导电构件38的热膨胀系数与底部填充胶层36的热膨胀系数的差,就会对导电构件38施加应力。该应力在与功能面33a、34a垂直的方向上,在相面对的功能面33a与功能面34a的中间部C(图6中以单点划线表示。)达到最大。
另一方面,突起电极43与突起电极46的连接部分(由连接构件47形成的突起电极43、46间的界面)处于从施加在导电构件38上的应力达到最大的位置(相面对的功能面33a与功能面34a的中间部C)向第一半导体芯片33侧靠近(偏移)的位置。所以,即使设置此种底部填充胶层36,也很难引起由温度循环造成的突起电极43与突起电极46的连接部的破坏。
虽然本发明的实施方式的说明如上所示,然而本发明也可以用别的方式来实施。例如,在图5所示的半导体装置31中,也可以将突起电极43与突起电极46之间填充地形成由构成突起电极43、46的金属和低熔点金属的合金构成的反应层。
在图6所示的半导体装置31A中,只要从功能面33a起的突起电极43的高度D7与从功能面34a起的突起电极46的高度D8不同即可,从功能面33a起的突起电极43的高度D7也可以被设为大于从功能面34a起的突起电极46的高度D8(D7>D8)。
虽然对于本发明的实施方式进行了详细说明,然而它们只不过是为了阐明本发明的技术的内容而使用的具体例,本发明不应当理解为限定于这些具体例,本发明的精神及范围仅由附加的技术方案的范围限定。
该申请对应于2004年11月25日向日本国专利局提出的特愿2004-341029,该申请的全部公布内容在这里被利用引用而加入。
Claims (6)
1.一种半导体装置,具备:
固体装置,该固体装置具有连接面,在该连接面上突出形成有由金属制成的连接电极;
半导体芯片,该半导体芯片具有功能面,在该功能面上突出形成有由金属制成的突起电极,使该功能面与所述固体装置的所述连接面相面对,并在所述功能面与所述连接面之间保持规定间隔而接合;
连接部件,该连接部件含有具有比所述连接电极及所述突起电极的固相线温度更低的低熔点的金属,并连接所述固体装置的所述连接电极和所述半导体芯片的所述突起电极,
在所述功能面与所述连接面的对置方向上,所述连接电极的高度与所述突起电极的高度之和为所述规定间隔的二分之一以上。
2.根据权利要求1所述的半导体装置,其中,
所述连接电极具有与所述半导体芯片相面对的上面、和大致沿着所述固体装置与所述半导体芯片的对置方向的侧面,
所述突起电极具有与所述固体装置相面对的上面、和大致沿着所述固体装置与所述半导体芯片的对置方向的侧面,
所述连接电极的上面及侧面以及所述突起电极的上面及侧面的大致整个区域被所述连接构件覆盖。
3.根据权利要求1所述的半导体装置,其中,
所述连接构件被配置成将所述连接电极和所述突起电极之间填充,并包括由构成所述连接电极或所述突起电极的金属与所述低熔点金属的合金制成的反应层。
4.根据权利要求1所述的半导体装置,其中,所述连接电极与所述突起电极由相同材料制成。
5.根据权利要求1所述的半导体装置,其中,所述固体装置是与所述半导体芯片不同的半导体芯片。
6.根据权利要求5所述的半导体装置,其中,所述连接电极和所述突起电极形成为各自的高度不同,使得所述连接电极与所述突起电极的连接部分的位置靠近所述半导体芯片侧或所述固体装置侧。
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JP2004341029A JP4908750B2 (ja) | 2004-11-25 | 2004-11-25 | 半導体装置 |
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JP (1) | JP4908750B2 (zh) |
KR (1) | KR101151542B1 (zh) |
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Cited By (7)
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---|---|---|---|---|
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Publication number | Priority date | Publication date | Assignee | Title |
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Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59218744A (ja) * | 1983-05-27 | 1984-12-10 | Hitachi Ltd | ボンデイング方法 |
JP3378334B2 (ja) * | 1994-01-26 | 2003-02-17 | 株式会社東芝 | 半導体装置実装構造体 |
JPH0997791A (ja) * | 1995-09-27 | 1997-04-08 | Internatl Business Mach Corp <Ibm> | バンプ構造、バンプの形成方法、実装接続体 |
JP4387548B2 (ja) * | 2000-03-28 | 2009-12-16 | 株式会社東芝 | 半導体装置及びその製造方法 |
JP2002289768A (ja) * | 2000-07-17 | 2002-10-04 | Rohm Co Ltd | 半導体装置およびその製法 |
JP3735526B2 (ja) * | 2000-10-04 | 2006-01-18 | 日本電気株式会社 | 半導体装置及びその製造方法 |
JP4284867B2 (ja) * | 2001-01-18 | 2009-06-24 | 株式会社日立製作所 | 標準モデル上で適応的選択暗号文攻撃に対して安全な公開鍵暗号方法 |
TWI273667B (en) * | 2005-08-30 | 2007-02-11 | Via Tech Inc | Chip package and bump connecting structure thereof |
TWI286829B (en) * | 2006-01-17 | 2007-09-11 | Via Tech Inc | Chip package |
-
2004
- 2004-11-25 JP JP2004341029A patent/JP4908750B2/ja active Active
-
2005
- 2005-09-01 CN CNA2005800267666A patent/CN101002313A/zh active Pending
- 2005-09-01 US US11/597,422 patent/US7598613B2/en active Active
- 2005-09-01 WO PCT/JP2005/015979 patent/WO2006057097A1/ja not_active Application Discontinuation
- 2005-09-01 KR KR1020077001900A patent/KR101151542B1/ko active IP Right Grant
- 2005-09-13 TW TW094131392A patent/TW200618142A/zh unknown
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KR20070083470A (ko) | 2007-08-24 |
TW200618142A (en) | 2006-06-01 |
US7598613B2 (en) | 2009-10-06 |
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US20070230153A1 (en) | 2007-10-04 |
WO2006057097A1 (ja) | 2006-06-01 |
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