CN1007186B - 数据处理系统主存机分布控制设备和方法 - Google Patents

数据处理系统主存机分布控制设备和方法

Info

Publication number
CN1007186B
CN1007186B CN87102176A CN87102176A CN1007186B CN 1007186 B CN1007186 B CN 1007186B CN 87102176 A CN87102176 A CN 87102176A CN 87102176 A CN87102176 A CN 87102176A CN 1007186 B CN1007186 B CN 1007186B
Authority
CN
China
Prior art keywords
memory
signal
array
data
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CN87102176A
Other languages
English (en)
Chinese (zh)
Other versions
CN87102176A (zh
Inventor
保罗·J·纳塔施
尤金·L·余
戴维·C·塞纳奇亚
小约翰·F·亨利
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Publication of CN87102176A publication Critical patent/CN87102176A/zh
Publication of CN1007186B publication Critical patent/CN1007186B/zh
Expired legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1615—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using a concurrent pipeline structrure

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Multi Processors (AREA)
  • Dram (AREA)
CN87102176A 1986-01-29 1987-01-29 数据处理系统主存机分布控制设备和方法 Expired CN1007186B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US82368786A 1986-01-29 1986-01-29
US823,687 1986-01-29

Publications (2)

Publication Number Publication Date
CN87102176A CN87102176A (zh) 1987-09-02
CN1007186B true CN1007186B (zh) 1990-03-14

Family

ID=25239418

Family Applications (1)

Application Number Title Priority Date Filing Date
CN87102176A Expired CN1007186B (zh) 1986-01-29 1987-01-29 数据处理系统主存机分布控制设备和方法

Country Status (12)

Country Link
EP (1) EP0288479B1 (en:Method)
JP (1) JPH01501346A (en:Method)
KR (1) KR910005379B1 (en:Method)
CN (1) CN1007186B (en:Method)
AU (1) AU6931087A (en:Method)
CA (1) CA1286412C (en:Method)
DE (1) DE3785191D1 (en:Method)
ES (1) ES2004078A6 (en:Method)
IL (1) IL81427A (en:Method)
IN (1) IN170464B (en:Method)
MX (1) MX168581B (en:Method)
WO (1) WO1987004825A1 (en:Method)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1324679C (en) * 1989-02-03 1993-11-23 Michael A. Gagliardo Method and means for interfacing a system control unit for a multi-processor system with the system main memory

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3343140A (en) * 1964-10-27 1967-09-19 Hughes Aircraft Co Banked memory system
DE2537787A1 (de) * 1975-08-25 1977-03-03 Computer Ges Konstanz Modularer arbeitsspeicher fuer eine datenverarbeitungsanlage und verfahren zum durchfuehren von speicherzugriffen an diesem speicher
US4245303A (en) * 1978-10-25 1981-01-13 Digital Equipment Corporation Memory for data processing system with command and data buffering
US4451880A (en) * 1980-10-31 1984-05-29 Honeywell Information Systems Inc. Memory controller with interleaved queuing apparatus
JPS58215777A (ja) * 1982-06-07 1983-12-15 Hitachi Ltd 記憶制御方式

Also Published As

Publication number Publication date
WO1987004825A1 (en) 1987-08-13
JPH01501346A (ja) 1989-05-11
IL81427A (en) 1991-06-10
AU6931087A (en) 1987-08-25
KR910005379B1 (ko) 1991-07-29
ES2004078A6 (es) 1988-12-01
CA1286412C (en) 1991-07-16
CN87102176A (zh) 1987-09-02
MX168581B (es) 1993-06-01
KR880700973A (ko) 1988-04-13
EP0288479B1 (en) 1993-03-31
IL81427A0 (en) 1987-08-31
EP0288479A1 (en) 1988-11-02
DE3785191D1 (de) 1993-05-06
IN170464B (en:Method) 1992-03-28

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