MX168581B - Aparato y metodo para proporcionar un control distribuido en una unidad de memoria principal de un sistema procesador de datos - Google Patents

Aparato y metodo para proporcionar un control distribuido en una unidad de memoria principal de un sistema procesador de datos

Info

Publication number
MX168581B
MX168581B MX005085A MX508587A MX168581B MX 168581 B MX168581 B MX 168581B MX 005085 A MX005085 A MX 005085A MX 508587 A MX508587 A MX 508587A MX 168581 B MX168581 B MX 168581B
Authority
MX
Mexico
Prior art keywords
data processing
processing system
memory unit
main memory
providing control
Prior art date
Application number
MX005085A
Other languages
English (en)
Inventor
David C Senerchia
John F Henry Jr
Paul J Natusch
Eugene L Yu
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Publication of MX168581B publication Critical patent/MX168581B/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1615—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using a concurrent pipeline structrure

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Multi Processors (AREA)
  • Dram (AREA)

Abstract

La presente invención se refiere a un sistema procesador de datos, caracterizado porque comprende: una barra de distribución del sistema, cuando menos, una unidad procesador de datos que se acopla con la barra de distribución del sistema, my un subsistema de memoria que se acopla con la barra de distribución del sistema; el subsistema de memoria incluye: una unidad de interfaz de los arreglos de memoria, que se acopla con la barra de distribución del sistema y múltiples unidades de arreglos de celdas de almacenamiento, cada una de las cuales incluye una serie de unidades de almacenamiento, y un aparato para controlar la operación de dicha serie de unidades de almacenamiento; una multiplicidad de las unidades de arreglos puede procesar simultáneamente grupos de señales de datos.
MX005085A 1986-01-29 1987-01-29 Aparato y metodo para proporcionar un control distribuido en una unidad de memoria principal de un sistema procesador de datos MX168581B (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US82368786A 1986-01-29 1986-01-29

Publications (1)

Publication Number Publication Date
MX168581B true MX168581B (es) 1993-06-01

Family

ID=25239418

Family Applications (1)

Application Number Title Priority Date Filing Date
MX005085A MX168581B (es) 1986-01-29 1987-01-29 Aparato y metodo para proporcionar un control distribuido en una unidad de memoria principal de un sistema procesador de datos

Country Status (12)

Country Link
EP (1) EP0288479B1 (es)
JP (1) JPH01501346A (es)
KR (1) KR910005379B1 (es)
CN (1) CN1007186B (es)
AU (1) AU6931087A (es)
CA (1) CA1286412C (es)
DE (1) DE3785191D1 (es)
ES (1) ES2004078A6 (es)
IL (1) IL81427A (es)
IN (1) IN170464B (es)
MX (1) MX168581B (es)
WO (1) WO1987004825A1 (es)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1324679C (en) * 1989-02-03 1993-11-23 Michael A. Gagliardo Method and means for interfacing a system control unit for a multi-processor system with the system main memory

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3343140A (en) * 1964-10-27 1967-09-19 Hughes Aircraft Co Banked memory system
DE2537787A1 (de) * 1975-08-25 1977-03-03 Computer Ges Konstanz Modularer arbeitsspeicher fuer eine datenverarbeitungsanlage und verfahren zum durchfuehren von speicherzugriffen an diesem speicher
US4245303A (en) * 1978-10-25 1981-01-13 Digital Equipment Corporation Memory for data processing system with command and data buffering
US4451880A (en) * 1980-10-31 1984-05-29 Honeywell Information Systems Inc. Memory controller with interleaved queuing apparatus
JPS58215777A (ja) * 1982-06-07 1983-12-15 Hitachi Ltd 記憶制御方式

Also Published As

Publication number Publication date
EP0288479B1 (en) 1993-03-31
CN87102176A (zh) 1987-09-02
IL81427A0 (en) 1987-08-31
EP0288479A1 (en) 1988-11-02
IN170464B (es) 1992-03-28
CA1286412C (en) 1991-07-16
WO1987004825A1 (en) 1987-08-13
ES2004078A6 (es) 1988-12-01
DE3785191D1 (de) 1993-05-06
KR880700973A (ko) 1988-04-13
CN1007186B (zh) 1990-03-14
IL81427A (en) 1991-06-10
JPH01501346A (ja) 1989-05-11
KR910005379B1 (ko) 1991-07-29
AU6931087A (en) 1987-08-25

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