ZA847566B - Multi-processor computer central control units - Google Patents

Multi-processor computer central control units

Info

Publication number
ZA847566B
ZA847566B ZA847566A ZA847566A ZA847566B ZA 847566 B ZA847566 B ZA 847566B ZA 847566 A ZA847566 A ZA 847566A ZA 847566 A ZA847566 A ZA 847566A ZA 847566 B ZA847566 B ZA 847566B
Authority
ZA
South Africa
Prior art keywords
cmy
memory
processors
bus system
ioc
Prior art date
Application number
ZA847566A
Inventor
Rudolf Bitzinger
Walter Engl
Siegfried Humml
Klaus Schreier
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Publication of ZA847566B publication Critical patent/ZA847566B/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54508—Configuration, initialisation
    • H04Q3/54516—Initialization, software or data downloading
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems
    • H04Q3/5455—Multi-processor, parallelism, distributed systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/1305—Software aspects
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13109—Initializing, personal profile
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13376—Information service, downloading of information, 0800/0900 services

Abstract

Multiprocessor controller, especially a multiprocessor central control unit of a telephone switching unit, having a bus system (B:CMY) to which there are connected the processors (CP, IOC), which have a separate local memory (LMY) or no separate local memory (LMY), and which is allocated alternately to different processors of the group (e.g. CP1, CPx, IOC0). The multiprocessor controller has a main memory (CMY), which is connected to the bus system (B:CMY) and to which the processors (CP, IOC) can alternately have access in accordance with the allocations of the bus system (B:CMY) via the bus system (B:CMY), and via which processors (CP, IOC) can communicate with one another if required. The main memory (CMY) comprises a plurality of memory banks (MB) each having its own memory control which controls its own memory bank (MB) independently of the memory control of the remaining memory banks (MB). Time frames having time slots or time channels are set up in accordance with the time-division multiplex principle on the bus or busses of the bus system (B:CMY). One or more of the time channels are respectively firmly allocated to each memory control. For the purpose of quasi-simultaneous access to the different memory banks (MB), time slots or time channels can be allocated in each case to a plurality of the processors (CP, IOC). <IMAGE>
ZA847566A 1983-09-26 1984-09-26 Multi-processor computer central control units ZA847566B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19833334797 DE3334797A1 (en) 1983-09-26 1983-09-26 MULTIPROCESSOR COMPUTER, ESPECIALLY MULTIPROCESSOR CENTRAL CONTROL UNIT OF A TELEPHONE SWITCHING SYSTEM

Publications (1)

Publication Number Publication Date
ZA847566B true ZA847566B (en) 1985-05-29

Family

ID=6210098

Family Applications (1)

Application Number Title Priority Date Filing Date
ZA847566A ZA847566B (en) 1983-09-26 1984-09-26 Multi-processor computer central control units

Country Status (6)

Country Link
EP (1) EP0141247B1 (en)
JP (1) JPH0797874B2 (en)
AT (1) ATE63189T1 (en)
DE (2) DE3334797A1 (en)
FI (1) FI88220C (en)
ZA (1) ZA847566B (en)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3334797A1 (en) * 1983-09-26 1985-01-03 Siemens AG, 1000 Berlin und 8000 München MULTIPROCESSOR COMPUTER, ESPECIALLY MULTIPROCESSOR CENTRAL CONTROL UNIT OF A TELEPHONE SWITCHING SYSTEM
JPS61150059A (en) * 1984-12-24 1986-07-08 Sony Corp Data processor
DE3629399A1 (en) * 1986-08-29 1988-03-03 Siemens Ag Method for operating the central memory of a multiprocessor-type common control unit of a switching system
US4816990A (en) * 1986-11-05 1989-03-28 Stratus Computer, Inc. Method and apparatus for fault-tolerant computer system having expandable processor section
US4933846A (en) * 1987-04-24 1990-06-12 Network Systems Corporation Network communications adapter with dual interleaved memory banks servicing multiple processors
DE3716633A1 (en) * 1987-05-18 1988-12-08 Siemens Ag Circuit arrangement for telecommunications systems, in particular telephone switching systems, in each case with a plurality of processors and memories
JPH02274197A (en) * 1989-04-17 1990-11-08 Nec Corp Load distribution processing system
EP0428938A3 (en) * 1989-11-17 1991-12-11 Siemens Aktiengesellschaft Multiprocessor system
US5471607A (en) * 1993-04-22 1995-11-28 Analog Devices, Inc. Multi-phase multi-access pipeline memory system
DE69819927D1 (en) 1997-09-05 2003-12-24 Sun Microsystems Inc TABLE OF CONSIDERATION AND METHOD OF DATA STORAGE THEREIN
US8175458B2 (en) 2007-07-17 2012-05-08 Vello Systems, Inc. Optical ring networks having node-to-node optical communication channels for carrying data traffic
US9054832B2 (en) 2009-12-08 2015-06-09 Treq Labs, Inc. Management, monitoring and performance optimization of optical networks
US8705741B2 (en) 2010-02-22 2014-04-22 Vello Systems, Inc. Subchannel security at the optical layer
US8542999B2 (en) 2011-02-01 2013-09-24 Vello Systems, Inc. Minimizing bandwidth narrowing penalties in a wavelength selective switch optical network
CN116662228B (en) * 2023-06-16 2024-01-30 深圳市东方聚成科技有限公司 Access method for time-division multiplexing local memory

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3931613A (en) * 1974-09-25 1976-01-06 Data General Corporation Data processing system
US4164787A (en) * 1977-11-09 1979-08-14 Bell Telephone Laboratories, Incorporated Multiple microprocessor intercommunication arrangement
US4363094A (en) * 1977-12-29 1982-12-07 M/A-COM DDC, Inc. Communications processor
CA1179069A (en) * 1981-04-10 1984-12-04 Yasushi Fukunaga Data transmission apparatus for a multiprocessor system
US4394726A (en) * 1981-04-29 1983-07-19 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Distributed multiport memory architecture
JPS5819973A (en) * 1981-07-30 1983-02-05 Nec Corp Multiprocessor computer of time division bus system
DE3334797A1 (en) * 1983-09-26 1985-01-03 Siemens AG, 1000 Berlin und 8000 München MULTIPROCESSOR COMPUTER, ESPECIALLY MULTIPROCESSOR CENTRAL CONTROL UNIT OF A TELEPHONE SWITCHING SYSTEM

Also Published As

Publication number Publication date
FI88220B (en) 1992-12-31
JPS60102088A (en) 1985-06-06
EP0141247A3 (en) 1988-02-10
DE3484530D1 (en) 1991-06-06
DE3334797A1 (en) 1985-01-03
ATE63189T1 (en) 1991-05-15
EP0141247A2 (en) 1985-05-15
FI88220C (en) 1993-04-13
JPH0797874B2 (en) 1995-10-18
FI843760A0 (en) 1984-09-25
FI843760L (en) 1985-03-27
EP0141247B1 (en) 1991-05-02

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