DE3716633A1 - Circuit arrangement for telecommunications systems, in particular telephone switching systems, in each case with a plurality of processors and memories - Google Patents

Abstract

Circuit arrangement for telecommunications systems, in particular telephone switching systems, in each case with a plurality of processors and memories. In a system with a plurality of parallel-operating processors and a plurality of parallel-operating memories and with a common data bus, the processors are connected in each case via an assigned input-output device to the data bus. A common input-output device is assigned to the memories, via which the memories are connected to the data bus. The latter input-output device operates individually for the individual memories by being assigned to them in a cyclical sequence using a time division multiplexing technique. <IMAGE>

Description

The invention relates to a circuit arrangement for telecommunications systems, in particular telephone switching systems, in which a plurality of processors working in parallel with one A plurality of parallel memories over a common data bus works together, and in which each of the processors as well the memory via input-output facilities with the data bus connected.

In a system with several processors working in parallel as well as several memories working in parallel and with a ge The processors are assigned to a common data bus via one each nete input-output device in connection with the data bus. The same applies to the multiple memories.

A circuit arrangement of the type specified is already through the German patent application 33 34 797 (VPA 83 P 1725). There is a main memory in four memory Banks each with its own memory controller divided. This own memory controller controls its memory bank independent of the memory controls of the other memory banks ken. So these memory banks can be operated simultaneously, thereby reducing the waiting times of the pro working with them cessors decrease significantly.

The already known subdivision of a main memory into multiple memory banks increases the amount of memory Not. However, dividing the main memory into several memory banks an increase in effort in terms of memory control individually assigned to the memory banks gene.

For the invention there is the task in the circuit arrangement Solutions of the known type mentioned at the outset wall for the memory controllers, with the help of which a letter and reading information in the respective memory bank possible is to reduce.

The invention solves the problem that the several memories have a common input-output device is assigned that this works in time-division multiplex operation and time-multiplexing the individual memories in this regard is individually assigned.

In the drawing, an embodiment of the invention is in components that contribute to their understanding provided, to which the same is by no means limited.

The description is based on an arrangement as it already is in the above-mentioned German patent application 33 34 797 (VPA 83 P 1725 DE) is known. Here is a central tax described computer for a telephone exchange, at which also has a number of processors working in parallel ren with a plurality of parallel memories over a ge common data bus works together. Each of the processors, as well as the memories are, as in the known case, via input Output devices in connection with the data bus. While however, in the known case, the individual, in the mentioned open each referred to as "memory banks" because with its own memory control (input-output Facility) is, in contrast, he provided according to the invention that the multiple memories a ge shared memory control, i.e. a common input Output device is assigned; this works in time multiplex operation and is time-multiplexed in this regard the individual memories (memory banks) individually assigned.  

The division of the main memory into four memory banks BK 1 to BK 4 is indicated in the drawing. Furthermore, an address buffer AP , a data input buffer DEP and a data output buffer DAP are provided. With the help of the address buffer AP , memory addresses are temporarily stored. The data input buffer DEP also temporarily stores data to be stored. With the help of the data output buffer DAP , data read from the memories are temporarily stored. The address buffer, the data input buffer and the data output buffer can each be set up for storing a plurality of addresses and a plurality of useful data words assigned to them, which are to be ascribed or read in succession.

There is also a timing device serving a control sequence T , from which clock lines tx, ty and tz proceed, and further clock lines t 1 to t 4 . The buffers mentioned and the memory banks are activated via these clock lines. With the help of the clock device T , the four different memory banks can be activated individually one after the other, both for write cycles and for read cycles. In this way, it is possible that the control device, which, among other things, consists of the three buffers and the clock device, can operate in time-division multiplexing virtually simultaneously for all four memory banks BK 1 to BK 4 . This time-division multiplex operation is essentially accomplished with the aid of clock signals which the clock generator device T delivers via the clock lines t 1 to t 4 to the four memory banks BK 1 to BK 4 . In temporal relation to the four different time slots, which are marked via the clock lines t 1 to t 4 , addressing takes place via the addressing line ad for each write cycle or for each read cycle, which leads from the address buffer to each of the four memory banks . A transferred addressing applies in each case to the memory bank that is marked with respect to the time position via the assigned clock line. Together with the addressing, additional information can also be transmitted to the memory bank in question, which indicates whether the process to be started is a write cycle or a read cycle.

In order to carry out a write cycle, the transfer of the user data word to be written in each case takes place via an information line u , ie from the data input buffer DEP, to the memory bank designated by the respective time mark after the respective address has been given. In a manner known per se, addressing always takes place first and the data to be written in each case is supplied thereafter. This time sequence is accomplished by corresponding time signals, which are emitted by the clock device T via the clock lines tx and ty .

The same applies to reading processes. First there is always an addressing, as well as information that the process to be subsequently carried out should be a read cycle. The memory bank in question then outputs the user data word read in each case via the read line v to the data output buffer DAP on the basis of the addressing and the read cycle signal.

It can also read cycles and write cycles in alternating Order to be processed. This is done in together with each addressing signaling that that it is a write cycle or a Read cycle should act.

Claims (1)

Circuit arrangement for telecommunication systems, in particular telephony switching systems, in which a plurality of processors working in parallel with a plurality of parallel memories cooperate via a common data bus, and in which each of the processors and the memories are connected to the data bus via input / output devices, characterized in that a common input-output device is assigned to the plurality of memories, that this works in time-division multiplexing and, in this regard, is individually assigned to the individual memories in terms of time-division multiplexing.