CN100539059C - 电子元件封装件及其制造方法 - Google Patents
电子元件封装件及其制造方法 Download PDFInfo
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Abstract
本发明公开了一种电子元件封装件及其制造方法。制造电子元件封装件的方法包括:在第一载板上形成突部;在第一载板上堆叠绝缘层以及在绝缘层的表面上形成包括焊垫和焊球垫的电路图案;将电子元件安装在绝缘层的表面上并且将电子元件和焊垫电连接;以及移除第一载板和突部,以仅通过单个电路图案层来安装电子元件。
Description
相关申请的交叉参考
本发明要求于2006年6月2日向韩国知识产权局递交的第10-2006-0050015号韩国专利申请的优先权,其全部内容结合于此作为参考。
技术领域
本发明涉及电子元件封装件及其制造方法。
背景技术
随着电子工业的进步,对电子元件封装件(其是配备有电子元件的电子器件)的使用快速增加。因此,制造和供应这些电子元件封装件的公司以及扩展电子元件封装件相关业务的公司的数量增加了。这些市场条件加剧了电子元件封装件的价格方面的竞争,因此电子元件封装件的价格逐步下降,并提出了许多有关降低成本的方法的建议。
目前,如图1a和图1b所示,大多数电子元件封装件都是通过使用导线结合法将电子元件(存储器芯片)连接到衬底上以提供封装件的方法来实现的,该板被称作BOC(Board-on-chip)。BOC是适应于电子元件的特性而特别开发的板,其中,该板具有位于中心的电子元件的焊盘并且允许从焊盘直接连接到该板以增加信号处理速度的结构。为了在板的底部连接电子元件并直接将焊盘连接到该板上,在放置焊盘的部分形成槽,从而可以实现导线结合。因此,该板上仅需要一层金属层,这可以降低制造成本以及提供电子元件封装件的价格竞争力方面的优势。
然而,随着半导体制造技术的高速发展,电子元件封装件的容量也增加了。由于技术方面的这些发展,在使用传统的BOC时会有在导线上丢失信号的情况。
发明内容
本发明一方面提供了一种电子元件封装件及其制造方法,通过本发明可以将高容量电子元件安装在单个金属层上。
本发明一方面提供了一种制造电子元件封装件的方法,该方法包括:在第一载板上形成突部;在第一载板上堆叠绝缘层,并在绝缘层的表面上形成包括焊垫和焊球垫的电路图案;在绝缘层的表面上安装电子元件,并电连接电子元件与焊垫;以及移除第一载板和突部。该电子元件封装件允许仅通过单个电路图案层来安装电子元件。
该方法进一步包括:在移除第一载板和突部的操作之后,移除绝缘层的部分以露出焊球垫。该焊球垫是将要连接焊球的部分,因此需要将它露在外部。
形成突部的操作优选地包括:在第一载板上堆叠种子层;在种子层上堆叠干膜;以及移除干膜的部分,以形成突部。
另外,形成突部的操作可以包括连接两个第一载板以使第一载板面朝相反的方向,以及移除干膜的部分的操作可以包括在两个第一载板的每个载板上形成突部。通过使用两个第一载板,可以提高处理的效率。
堆叠绝缘层和形成电路图案的操作可以包括:在第二载板上堆叠种子层;在种子层上形成电路图案;在绝缘层上堆叠第二载板,以使电路图案面朝绝缘层;移除第二载板;以及移除种子层。
另外,该方法可以进一步包括以下操作:在种子层上堆叠干膜以及移除干膜的部分以露出在焊垫侧的种子层;移除焊垫周围的种子层;以及在移除第二载板的操作和移除种子层的操作之间,通过向剩余的种子层施加电压来对焊垫进行表面处理。这是使用种子层作为导线来进行表面处理的方法。
本发明另一方面提供了一种电子元件封装件,其包括:绝缘层;单层电路图案,埋在绝缘层中,具有露在绝缘层一侧的表面并包括焊垫和焊球垫;以及电子元件,安装在绝缘层一侧并且与焊垫电连接。在该封装件中,仅通过单个电路图案层来安装电子元件。
同时,希望对应于焊球垫的位置移除绝缘层的一部分,使得焊球垫在绝缘层的另外一侧露出。焊球垫变为连接焊球的位置。
本发明的其它方面及优点将通过下面的包括附图和权利要求的描述变得明显和更容易理解,或通过本发明的实施来了解。
附图说明
图1a是根据现有技术的电子元件封装件的透视图;
图1b是根据现有技术的电子元件封装件的截面图;
图2是根据本发明的第一公开实施例的制造电子元件封装件的方法的流程图;
图3是根据本发明的第一公开实施例的制造电子元件封装件的方法的过程图;
图4是根据本发明的第二公开实施例的制造电子元件封装件的方法的过程图;
图5是根据本发明的第三公开实施例的制造电子元件封装件的方法的过程图;
图6是根据本发明的第四公开实施例的制造电子元件封装件的方法的过程图;
图7是根据本发明的第四公开实施例的电子元件封装件的截面图。
具体实施方式
下面将参考附图更加详细地描述本发明的实施例。在参考附图的描述中,不考虑附图的编号,赋予相同或相应的元件相同的参考标号,并且省略冗余的解释。
图2是根据本发明的第一公开实施例的制造电子元件封装件的方法的流程图,图3是根据本发明的第一公开实施例的制造电子元件封装件的方法的过程图。在图3中,示出了电子元件封装件30、第一载板31a、第二载板31b、种子层32a、32b、突部33、绝缘层34、孔35、焊球垫36a、电路图案36、焊垫36c、阻焊层37、电子元件38、芯片板38a、以及模具材料39。
图2中的S21是在第一载板上形成突部的操作,其对应处理过程在图3(a)中示出。在第一载板31a上形成突部33的操作可以分为以下步骤:准备平坦的第一载板31a;通过非电解镀在第一载板31a上堆叠种子层32a;以及相应于焊球垫36a,在种子层32a的表面上形成突部33。通过在种子层32a的表面上堆叠干膜,然后通过曝光和显影处理移除突部33之外的剩余干膜来形成突部33。同时,形成种子层32a使得第一载板31a可以被轻易拆除。因此,如果第一载板31a可以在没有插入种子层32a的情况下被轻易地移除,则堆叠种子层32a的过程是不必要的。
图2中的S22是在第一载板31a上堆叠绝缘层34以及在绝缘层34的表面上形成包括焊垫36c和焊球垫36a的电路图案36的操作,其对应处理在图3(b)至图3(e)中示出。如图3(b)所示,将其上形成有包括焊垫36c和焊球垫36a的电路图案36的第二载板31b与在图3的处理过程(a)中预先形成的第一载板31a对齐,并与插入其间的绝缘层34对齐。该对齐使得第一载板31a的突部33与第二载板31b的电路图案36相对。
同时,使用半加成法在第二载板31b的表面上制造图3(b)中所示的电路图案36。具体地,在第二载板31b的表面上顺序堆叠种子层32b和干膜。然后,执行曝光和显影处理以移除将形成电路图案36的位置处的干膜部分。然后,电镀(plate)所移除的部分并移除剩余的干膜,从而如图3(b)中所示,在第二载板31b的表面上形成电路图案36。
图3(c)示出了堆叠在一起的第一载板31a和第二载板31b,其中,突部33和包括焊球垫36a以及焊垫36b的电路图案36嵌在绝缘层34中。
这里,在与焊球垫36a对应的位置处堆叠突部33。因此,希望在处理过程(a)中,在与焊球垫36a对应的位置处预先形成突部33。另外,希望所形成的突部33具有不允许绝缘层34插在突部33和焊球垫36a之间的厚度。同时,用于绝缘层34的材料是低硬度的,因此可以将突部33嵌入其中。这种材料的实例是纯树脂。
图3(d)示出了移除第二载板31b和种子层32b的过程。通过快速蚀刻来移除种子层32b。快速蚀刻是以低于常规蚀刻的密度来执行的蚀刻处理,用于移除种子层的薄膜。该蚀刻过程完成后的结果在图3(d)中示出。如图3(d)所示,将包括焊球垫36a和焊垫36c的电路图案36嵌在绝缘层34中。
图3(e)示出了表面处理焊垫36c的过程,其中,将阻焊层37应用于除了焊垫36c部分之外的部分。然后,通过非电解镀将Ni层堆叠到焊垫36c上,并通过电镀在Ni层的表面上执行镀金。
图2的S23是将电子元件38安装在绝缘层34的表面上并且将电子元件38与焊垫36c电连接的操作。将焊垫36c形成在与电子元件38的芯片板38a对应的位置处,并在将芯片板38a放置在焊垫36c的表面上之后,通过地板(flooring)连接它们。另外,为了保护电子元件38,使用模具材料39在电子元件38和绝缘层34周围进行修整(finishing)。
图2的S24是移除第一载板31a和突部33的操作,其对应处理过程在图3(g)和图3(h)中示出。
图3(g)示出了移除第一载板31a和移除种子层32a的过程。第一载板31a是一种支撑物,在安装电子元件38之后被移除。在移除第一载板31a之后,移除种子层32a。当移除种子层32a时,露出突部33。通过湿处理将露出的突部33移除。
图3(h)示出了在移除突部33之后电子元件封装件30的形态。当移除突部33时形成孔35,并且将焊球垫36a露在孔35内侧的外部。因为绝缘层34的部分可能会留在焊球垫36a上,因此进一步执行去胶渣过程(desmearing process)以移除它们。
图4是根据本发明的第二公开实施例的制造电子元件封装件的方法的过程图。在图4中,示出了电子元件封装件40、第一载板41、种子层42a、42b、突部43、绝缘层44、焊球垫46a、电路图案46、焊垫46c、阻焊层47、电子元件48、芯片板48a、以及模具材料49。在此实施例中,通过执行将两个第一载板41连接在一起的工序,来提高制造电子元件封装件40的效率。
虽然此实施例大体上与图3的第一公开实施例相同,但是通过进行将两个第一载板41a连接在一起的处理而以更高的效率制造存储封装件(memory package)40。下面参考图4的过程,对此实施例进行描述。
图4(a)示出了与图3(a)相同的过程,其是在第一载板41a上形成突部43的过程。
在图4(b)中,面朝相反方向连接两个第一载板41a,从而使得突部43露在外面,基于此,对称排列绝缘层44和具有包括焊球垫46a和焊垫46c的电路图案46的第二载板41b。因此使用连接到一起的两个第二载板41a允许同时执行此过程。
图4(c)示出了相对于连接到一起的两个第一载板41a对称堆叠绝缘层44和第二载板41b。第一载板41a的突部43和第二载板41b的电路图案46嵌在绝缘层44中。希望将低硬度的材料用于绝缘层44,在此实施例中,使用纯树脂。
图4(d)示出了移除第二载板41b和种子层42b的过程。当移除第二载板41b和种子层42b时,在绝缘层44的表面处露出电路图案46。
图4(e)示出了将阻焊层47应用于除了焊垫46c之外的部分上,然后对焊垫46c进行表面处理的过程。焊垫46c是随后将被连接到电子元件48的芯片板48a的部分。
图4(f)示出了分离两个第一载板41a以及将电子元件48安装在每个第一载板41a的焊垫46c上的处理过程。尽管在图4的处理过程(e)之前将使用的两个第一载板41a连接到了一起,但从图4的处理过程(f)开始,通过分离的第一载板41a执行这些处理过程。图4(f)示出了连接芯片板48a和相应的焊垫46c以及将电子元件48安装在焊垫46c的表面上的处理过程。为了保护电子元件48,在电子元件48的周围填充模具材料49。使用环氧树脂作为模具材料49。
因为在图3中的第一公开实施例中已经做了充分的描述,所以省略对图4(g)和图4(h)的描述。
图5是根据本发明的第三公开实施例的制造电子元件封装件的方法的过程图。在图5中,示出了电子元件封装件50、第一载板51a、第二载板51b、种子层52a、52b、突部53、绝缘层54、焊球垫56a、电路图案56、焊垫56c、保护层(resist)57、电子元件58、芯片板58a、以及模具材料59。
此实施例示出了使用种子层52b作为导线在焊垫56c上执行表面处理的处理过程。图5的处理过程(a)到处理过程(c)与图3的处理过程(a)到处理过程(c)一样。图5(d)示出了移除第二载板52b的处理过程。当移除第二载板51b时,露出种子层52b。
图5(e)示出了在将应用表面处理的焊垫56c的表面及周围移除种子层52b以及将保护层57堆叠到剩余的种子层52b的表面上的处理过程。将干膜用作保护层57。没有被移除的种子层52b的部分用作向焊垫56c提供电流的导线。这个处理过程将种子层52b作为导线使用,代替了形成独立的导线。保护层57防止了对焊垫56c以外的部分的表面处理。
图5(f)示出了安装电子元件58的处理过程。为了安装电子元件58,在图5(e)中,移除种子层52b和保护层57。剩余的种子层52b可能会导致电路图案56电连接到不希望的部分,因此优选移除种子层52b。在移除种子层52b之后安装电子元件58的处理过程与图3的过程一样,因此将不再提供关于这方面的详细描述。
图6是根据本发明的第四公开实施例的制造电子元件封装件的方法的过程图。在图6中,示出了电子元件封装件60、第一载板61a、种子层62a、铜箔62b、突部63、敷铜箔叠层板64、焊球垫66a、电路图案66、焊垫66c、阻焊层67、电子元件68、芯片板68a、以及模具材料69。
此实施例示出了将敷铜箔叠层板64堆叠到第一载板61a上以及之后移除铜箔62b以形成电路图案66的处理过程。参考图6考虑此实施例,图6(a)示出了与图3(a)相同的处理过程,即在第一载板61a上形成突部63的过程。
图6(b)示出了连接两个第一载板61a从而使得突部63面向外边以及对称排列敷铜箔叠层板64的处理过程。在图6(c)中,将敷铜箔叠层板64以及第一载板61a堆叠在一起。这里,考虑到两个第一载板61a将在后续过程中被分离而连接它们。
图6(d)示出了移除铜箔62b的一部分以形成包括焊球垫66a和焊垫66c的电路图案66的处理过程。图6(e)示出了在焊垫66c上执行表面处理的过程,图6(f)示出了分离两个第一载板61a然后安装电子元件68的过程。下面的过程是如对于图3的实施例已经描述过的移除第一载板61a、种子层62a、以及突部63的过程。
图7是根据本发明的第四公开实施例的电子元件封装件的截面图。在图7中,示出了电子元件封装件70、绝缘层74、焊球垫76a、电路图案76、焊垫76c、阻焊层77、电子元件78、芯片板78a、以及模具材料79。
在此实施例中,将与电子元件78电连接的焊垫76c形成在单层电路图案76的一侧,并且将与焊球连接的焊球垫76a形成在另外一侧。这些焊球垫76a和焊垫76c是电路图案76的一部分,并且在形成电路图案76的同时形成。
电子元件78具有倒装芯片的形式,多个芯片板78a形成在底面上。这些芯片板78a形成在对应于焊垫76c的位置并且相互电连接。同时,通过模具材料79保护电子元件78。焊球垫76a具有露在外部的表面,其中,对露出的部分进行表面处理。表面处理用于增强焊球的粘合力。
根据以上提出的实施例,与传统的电子元件封装件的情况相比,信号线的长度变短了,从而允许更快的信号处理。同时,可以通过半加成法形成高密度的电路。另外,由于不存在与现有技术中相同的导线接合,所以不必要处理孔,以及由于电路图案是单层的,所以可得到极好的放热效果。
虽然参考特定的实施例对本发明进行了描述,但是所属技术领域人员将明白的是,在不超出所附权利要求及其等价物限定的本发明的精神和范围的条件下,可以作出各种变化和修改。
Claims (5)
1.一种制造电子元件封装件的方法,所述方法包括:
在第一载板上形成突部;
在所述第一载板上堆叠绝缘层并在所述绝缘层的表面上形成电路图案,所述电路图案包括焊垫和焊球垫;
将电子元件安装在所述绝缘层的所述表面上并且将所述电子元件与所述焊垫电连接;
移除所述第一载板和所述突部;以及
在移除所述第一载板和所述突部的操作之后,移除所述绝缘层的一部分,以露出所述焊球垫。
3.根据权利要求1所述的方法,其中,所述形成突部的操作包括:
在所述第一载板上堆叠种子层;
在所述种子层上堆叠干膜;以及
移除所述干膜的一部分,以形成所述突部。
4.根据权利要求3所述的方法,其中,所述形成突部的操作包括:
连接两个所述第一载板,使得所述第一载板面朝相反的方向,
以及在所述两个第一载板的每个上形成所述突部。
5.根据权利要求1所述的方法,其中,所述形成电路图案和移除所述第二载板和所述种子层的操作包括:
在第二载板上堆叠种子层;
在所述种子层上形成所述电路图案;
在所述绝缘层上堆叠所述第二载板,使得所述电路图案面朝所述绝缘层;
移除所述第二载板;以及
移除所述种子层。
6.根据权利要求5所述的方法,进一步包括:
在所述种子层上堆叠干膜,并且移除所述干膜的一部分,以使所述种子层露出;
移除在所述焊垫表面上的所述种子层;以及
在所述移除所述第二载板的操作和所述移除所述种子层的操作之间,通过将电压施加到剩余的种子层来对所述焊垫进行表面处理。
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2007
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- 2007-03-13 CN CNB2007100867401A patent/CN100539059C/zh not_active Expired - Fee Related
- 2007-03-27 JP JP2007080461A patent/JP4763639B2/ja not_active Expired - Fee Related
-
2009
- 2009-09-16 US US12/585,509 patent/US20100108372A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US20070278651A1 (en) | 2007-12-06 |
US7607222B2 (en) | 2009-10-27 |
US20100108372A1 (en) | 2010-05-06 |
KR100734403B1 (ko) | 2007-07-02 |
JP2007324569A (ja) | 2007-12-13 |
JP4763639B2 (ja) | 2011-08-31 |
CN101083215A (zh) | 2007-12-05 |
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