CN100511670C - 半导体装置 - Google Patents
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- CN100511670C CN100511670C CNB2007100028492A CN200710002849A CN100511670C CN 100511670 C CN100511670 C CN 100511670C CN B2007100028492 A CNB2007100028492 A CN B2007100028492A CN 200710002849 A CN200710002849 A CN 200710002849A CN 100511670 C CN100511670 C CN 100511670C
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Abstract
提供一种能够简单且廉价地制造、并能够以低功耗进行通信的半导体装置。在硅中介层(101)的表面(102)上形成通信芯片(105)和平板(121-1)。在硅中介层(201)中也同样地在其表面(202)上形成通信芯片(205)和平板(221-1)。将两个硅中介层(101、201)配置成使背面(103、203)相对,通过平板(121-1、221-1)的静电感应在通信芯片(105、205)间进行通信。
Description
技术领域
本发明涉及一种半导体装置,特别是涉及能够简单且廉价地制造、能够以低功耗进行通信的半导体装置。
背景技术
伴随着电子设备的普及,提出了以低成本实现层叠了多芯片模块(MCM)的多芯片封装、或者系统级封装(SIP)的层叠技术、芯片间布线技术等。
图1示出了现有多芯片模块的结构的例子。在该多芯片模块中,组合了硅中介层1和硅中介层21。在硅中介层1的表面2上通过凸块4安装有芯片5。同样地,在硅中介层21的表面22上,通过凸块24安装了芯片25。而且,在硅中介层1的表面2和背面3之间形成有贯通孔6,在硅中介层21的表面22和背面23之间形成有贯通孔26。并且,贯通孔6和贯通孔26通过凸块7相互连接。通过形成在硅中介层1上的图案、硅中介层1的贯通孔6、凸块7、硅中介层21的贯通孔26、以及硅中介层21上的图案,进行硅中介层1上的芯片5和硅中介层21上的芯片25之间的通信。
然而,为了形成贯通孔,不仅需要开发新的工序,而且需要在硅中介层的背面形成电极,还存在难以形成微小的贯通孔等的问题。
因此,已知例如图2的A所示,利用静电电容耦合进行通信的技术(例如非专利文献1)。在图2的A的例子中,在硅中介层1的表面2(安装有芯片5的面)上形成电极41,同样在硅中介层21的表面22(安装有芯片25的面)上形成电极51,使电极41和电极51相对地配置硅中介层1的表面2和硅中介层21的表面22。硅中介层1的表面2上的芯片5、以及硅中介层21的表面22上的芯片25,分别通过利用了电极41和电极51的静电感应的通信路径进行通信。
非专利文献1:“日ェレクトロニクス”2005年10月10日发行,p.92-99
发明内容
发明要解决的问题
然而,如果如图2的A所示,将电极41、51相对配置而进行无线通信,则如下的方法更廉价且容易制造,即例如如图2的B所示,在硅中介层1的表面2和硅中介层21的表面22之间配置凸块61,通过该凸块61进行通信。
本发明是鉴于这种状况而作出的发明,实现可简单且廉价地制造、能够以低功耗进行通信的半导体装置。
用于解决问题的手段
本发明提供一种半导体装置,其具备:第1板状部件,其是由高电阻的原材料构成的板状部件,在一个面上形成有电路;第2板状部件,其是由高电阻的原材料构成的板状部件,在一个面上形成有电路;在上述第1板状部件的形成有上述电路的面上配置的作为通信用天线的多个第1平板;第1通信部,其配置在上述第1板状部件的形成有上述电路的面上,通过上述第1平板进行通信;在上述第2板状部件的形成有上述电路的面上配置的作为通信用天线的多个第2平板;以及第2通信部,其配置在上述第2板状部件的形成有上述电路的面上,通过上述第2平板进行通信,上述第1板状部件和上述第2板状部件配置成使各自的没有形成上述电路的面相对。
上述第1板状部件可具有接受电力供给的接合线,上述第2板状部件可具有接受电力供给的凸块。
上述第1板状部件和上述第2板状部件可以是硅中介层,其体积电阻率是1kΩcm以上。
至少具备两组由上述第1板状部件和上述第2板状部件构成的组合,一个组的上述第1板状部件和上述第2板状部件中的一个板状部件的形成有上述电路的面、与另一个组的上述第1板状部件和上述第2板状部件中的一个板状部件的形成有上述电路的面,被配置成相互相对,可以在两者之间设置通信用凸块和电力供给用凸块。
在本发明中,在形成有电路的面上配置了作为通信用天线的多个第1平板的第1板状部件、与在形成有电路的面上配置了作为通信用天线的多个第2平板的第2板状部件,被配置成使各自的没有形成电路的一面相对。在第1板状部件和第2板状部件夹在第1平板和第2平板之间的状态下,利用第1平板和第2平板的静电感应,在第1板状部件的第1通信部和第2板状部件的第2通信部之间进行通信。
发明的效果
如上所述,根据本发明,能够实现半导体装置。特别是可实现能够简单且廉价地制造、能够以低功耗进行通信的半导体装置。
附图说明
图1是表示现有多芯片模块的结构的剖视图。
图2是说明现有硅中介层间的通信的图。
图3是说明在应用本发明的多芯片模块中应用的硅中介层的结构的侧剖视图。
图4是表示应用本发明的多芯片模块的截面结构的侧剖视图。
图5是表示硅中介层的平面结构的平面图。
图6是表示通信芯片的结构的平面图。
图7是表示通信芯片附近的结构的侧剖视图。
图8是表示组合了硅中介层的状态的结构的侧剖视图。
图9是说明体积电阻率的图。
图10是表示通信部的结构的电路图。
图11是说明图10的电路图动作的时序图。
图12是表示其他通信部的结构的电路图。
图13是说明图12的通信部的动作的时序图。
图14是表示硅中介层的平面结构的平面图。
图15是说明组合了硅中介层的状态的侧剖视图。
图16是表示硅中介层的内部结构的侧剖视图。
附图标记说明
101:硅中介层;102:表面;103:背面;104:凸块;105:通信芯片;106、107、108:芯片;201:硅中介层;202:表面;203:背面;204:凸块;205:通信芯片;206、207、208:芯片;301:硅中介层;302:表面;303:背面;304:凸块;305:通信芯片;306、307:芯片;401:硅中介层;402:表面;403:背面;404:凸块;405:通信芯片;406、407:芯片。
具体实施方式
以下,说明本发明的实施方式,下面举例说明本发明的构成要件与说明书或者附图中记载的实施方式的对应关系。本记载是为了确认支持本发明的实施方式被记载在说明书或者附图中。因此,即使有虽然记载在说明书或者附图中,但是没有作为与本发明的构成要件对应的实施方式而记载在这里的实施方式,也不意味该实施方式不与该构成要件对应。相反,即使实施方式作为与构成要件对应的部分而记载于此,也不意味该实施方式不与该构成要件以外的构成要件对应。
本发明提供一种半导体装置,其具备:第1板状部件(例如,图4的硅中介层101),其是由高电阻的原材料构成的板状部件,在一个面上形成有电路(例如,图4的芯片106、107);第2板状部件(例如,图4的硅中介层201),其是由高电阻的原材料构成的板状部件,在一个面上形成有电路(例如,图4的芯片206、207);在上述第1板状部件的形成有上述电路的面(例如,图4的表面102)上配置的作为通信用天线的多个第1平板(例如,图8的平板121-1);第1通信部(例如,图10的发送部1001-1-1),其配置在上述第1板状部件的形成有上述电路的面上,通过上述第1平板进行通信;在上述第2板状部件的形成有上述电路的面上配置的作为通信用天线的多个第2平板(例如,图8的平板221-1);以及第2通信部(例如,图10的接收部2002-1-1),其配置在上述第2板状部件的形成有上述电路的面上,通过上述第2平板进行通信,上述第1板状部件和上述第2板状部件配置成使各自的没有形成上述电路的面(例如,图4的背面103、203)相对。
上述第1板状部件可具有接受电力供给的接合线(例如,图4的接合线504),上述第2板状部件可具有接受电力供给的凸块(例如,图4的凸块505)。
至少具备两组(例如,图4的硅中介层101、201的组、和硅中介层301、401的组)由上述第1板状部件和上述第2板状部件构成的组合,一个组(例如,图4的硅中介层101、201的组)的上述第1板状部件和上述第2板状部件中的一个板状部件的形成有上述电路的面(例如,图4的硅中介层201的表面202)、与另一个组(例如,图4的硅中介层301、401的组)的上述第1板状部件和上述第2板状部件中的一个板状部件的形成有上述电路的面(例如,图4的硅中介层301的表面302),被配置成相互相对,可以在两者之间设置通信用凸块和电力供给用凸块(例如,图4的凸块505)。
下面,参照附图说明本发明的实施方式。
图3示出了装入到应用本发明的多芯片模块中的作为由高电阻原材料构成的板状部件的硅中介层的结构。在硅中介层101中,在其表面102上通过多个凸块104配置有通信芯片105,并且配置有芯片106、107。通信芯片105的详细内容参照图6至图8在后面叙述,其与其他硅中介层进行通信。芯片106、107例如由CPU(Central Processing Unit:中央处理单元)、或者存储器等构成,分别执行与预先决定的规定功能相关的处理。在硅中介层101的表面102上,虽然未图示,但是形成有布线图案。与此相对,没有在表面102的相反侧的背面103上配置芯片。
硅中介层201也同样,在表面202上通过多个凸块204安装了通信芯片205、芯片206、207。没有在硅中介层201的背面203上安装芯片。
在硅中介层301的表面302上,通过多个凸块304配置有通信芯片305、芯片306、307。没有在硅中介层301的背面303上配置芯片。
同样地,在硅中介层401的表面402上,通过多个凸块404安装了通信芯片405、芯片406、407。没有在硅中介层401的背面403上安装芯片。
芯片206、207、306、307、406、407也与芯片106、107相同,是执行通信以外的规定功能的芯片。
图4示出了将硅中介层101至401组合而制造的多芯片模块的结构。在该多芯片模块501中,将硅中介层101和硅中介层201设为一组,将硅中介层301和硅中介层401设为一组。
即,硅中介层101和硅中介层201被配置成使分别作为通信芯片105和通信芯片205的天线的平板(参照图6在后面叙述)分别相对、且使各自的背面103和背面203相对。同样地,硅中介层301和硅中介层401被配置成使各个背面303和背面403相对、且使通信芯片305的平板和通信芯片405的平板分别相对。
在基板502的表面503上形成有布线图案,并且根据需要还安装了各种芯片(都没有图示)。另外,表面503通过接合线506与硅中介层301的表面302连接。硅中介层101的表面102也通过接合线504与基板502的表面503连接。硅中介层401的表面402通过多个凸块404与基板502的表面503连接。另外,硅中介层301的表面302和硅中介层201的表面202通过多个凸块505连接。
通过这样构成,从在基板502的表面503上形成的布线图案,通过凸块404中的规定部分向配置在硅中介层401的表面402上的通信芯片405、芯片406、407提供所需的电力。另外同样地,通过规定的其他凸块404,在基板502的表面503上形成的规定布线图案和硅中介层401上的通信芯片405、芯片406、407之间进行信号的交换。
从基板502的表面503的布线图案通过接合线506向硅中介层301上的通信芯片305、芯片306、307提供所需的电力。硅中介层301上的芯片306、307通过通信芯片305和通信芯片405,与硅中介层401上的芯片406、407进行通信。
从基板502的表面503的布线图案,通过接合线506、硅中介层301上的布线图案、规定的凸块505、硅中介层201的表面202的布线图案、规定的凸块204,向硅中介层201上的通信芯片205、芯片206、207提供电力。芯片206、207通过规定的凸块204、硅中介层201上的布线图案、规定的凸块505、硅中介层301上的布线图案、规定的凸块304,与硅中介层301上的芯片306、307进行通信。
从基板502的表面503上的布线图案,通过接合线504、硅中介层101上的布线图案、规定的凸块104,向硅中介层101的通信芯片105、芯片106、107提供所需的电力。通过通信芯片105、205进行芯片106、107与芯片206、207之间的通信。
通过依次经由直接相邻的硅中介层间的通信,进行没有直接相邻的硅中介层间的通信。例如,通过通信芯片105、通信芯片205、凸块505,进行芯片106、107和芯片306、307之间的通信。而且,通过通信芯片105、通信芯片205、凸块505、通信芯片305、通信芯片405,进行芯片106、107和芯片406、407之间的通信。通过通信芯片105、通信芯片205、凸块505、通信芯片305、通信芯片405、凸块404,进行芯片106、107与基板502的表面503上的未图示的芯片之间的通信。
图5示出了硅中介层101和硅中介层201的平面结构。硅中介层101如图5的A所示,在芯片106的左上配置有芯片108,在芯片106的左下侧配置有芯片107。在芯片106的右侧区域Q中形成有通信区域111。在该通信区域111中还配置有通信芯片105-1至105-4。
同样地,如图5B所示在硅中介层201上,在芯片206的左下侧配置有芯片207,在左上侧配置有芯片208。芯片206的右侧区域Q中形成有通信区域211,在通信区域211中还配置有通信芯片205-1至205-4。
虽然省略了图示,硅中介层301、401也同样地构成。
图6放大示出了通信芯片105-1至105-4的平面结构。通信芯片105-1在其上侧形成有由铝等金属构成的作为天线的平板121-1-1、122-1-1。平板121-1-1、122-1-1成组地进行发送或者接收的通信。同样地,通信芯片105-1从平板121-1-1、122-1-1的右起向左,按顺序还具有平板121-1-2、122-1-2至121-1-8、122-1-8。另外同样地,在下侧从右向左按顺序具有平板121-1-9、122-1-9至121-1-16、122-1-16(省略一部分号码的图示)。
同样地,通信芯片105-2具有平板121-2-1、122-2-1至121-2-16、122-2-16,通信芯片105-3具有平板121-3-1、122-3-1至121-3-16、122-3-16,通信芯片105-4具有平板121-4-1、122-4-1至121-4-16、122-4-16。
图7放大示出了通信芯片105-1的剖面结构。如该图所示,在通信芯片105-1的图中右侧和左侧,通过凸块104配置有平板121-1、121-9。另外,通信芯片105-1通过凸块104与硅中介层101上的焊盘(pad)131连接。该焊盘131进一步与未图示的布线图案连接。
如图8所示,硅中介层101的平板121-1(121-1-1至121-1-16)、与硅中介层201的平板221-1(221-1-1至221-1-16)被配置成使得所对应的部分相对。其结果,在相对配置的平板121-1和平板221-1之间,存在由高电阻材料构成的硅中介层101、201。硅中介层101、201由于是高电阻硅基板,因此介电常数高,由平板121-1、221-1构成的电容器的容量与如图2的A所示将电极41、51仅通过空气相对配置的情况相比,能够设为极大的值。其结果,即使将平板121-1、221-1面积设成较小,也能够实现足够大的静电耦合。
硅中介层101至401的体积电阻率,具体来说设为1kΩcm以上的值。体积电阻率例如如图9所示,当在宽度为W、厚度为t、长度为L的物质中流过电流I时,通过测定在距离为L的两端产生的电位差V,能够从下式求出。
体积电阻率=(V/I)×(W/L)×t...(1)
硅原本是非导电部件,因此能够通过不将杂质掺杂到硅中,从而实现高电阻的硅中介层。
通信芯片105、205、305、405分别具有通信部,该通信部是由对应于各平板的发送部和接收部中的至少一方构成的。即,对于发送用的平板设置有发送部,对于接收用的平板设置有接收部。在所对应的平板进行发送和接收两者的情况下,设置有发送部和接收部两者。通信芯片105和通信芯片205配置成分别使接收用的平板与发送用的平板相对。例如,在配置成使接收用的平板221-1-1、222-1-1与发送用的平板121-1-1、122-1-1相对的情况下,如图10所示连接与发送用的平板121-1-1、122-1-1对应的发送部1001-1-1、和与接收用的平板221-1-1、222-1-1对应的接收部2002-1-1。
发送部1001-1-1由反相器1011至1014构成。从端子IN输入的信号通过反相器1011、1012、1013,从端子N1提供给平板121-1-1,并且通过反相器1011、1014从端子N2提供给平板122-1-1。
在接收部2002-1-1的输入端子N3、N4上分别连接有平板221-1-1、222-1-1。输入端子N3、N4连接在放大器2013的输入端子上。在输入端子N3和N4之间连接有电阻2011、2012。在电阻2011和电阻2012之间提供基准电压VREF。放大器2013的输出,被提供给滞后比较器(Hysteresis Comparator)2014的非翻转输入端子、滞后比较器2016的翻转输入端子。在比较器2014的翻转输入端子上被提供基准电压VR1,在比较器2016的非翻转输入端子中被提供基准电压VR2。
比较器2014的输出(节点N5)通过反相器2015,连接在与NAND电路2019一起构成交叉锁定电路(クロスラツチ回路)的NAND电路2018的一个输入上。比较器2016的输出(节点N6),通过反相器2017连接在NAND电路2019的一个输入上。NAND电路2018的输出连接在NAND电路2019的另一个输入上,NAND电路2019的输出连接在NAND电路2018的另一个输入上。
当将信号(图11的A)输入到发送部1001-1-1的端子IN时,通过反相器1011、1012、1013在端子N1(平板121-1-1)中、以及通过反相器1011、1014在端子N2(平板122-1-1)中,分别产生相位相反的电压(图11的B的由虚线表示的电压和由实线表示的电压)。由于静电感应,在接收侧的平板221-1-1、222-1-1(输入端子N3、N4)中产生相位相反的电压(图11的C的由虚线表示的电压和由实线表示的电压)。放大器2013放大通过该静电感应提供的信号,输出到节点VA(图11的D)。
比较器2014将从放大器2013输入的信号水平与基准电压VR1进行比较,在大于基准电压VR1的情况下,向节点N5输出正脉冲(图11的E)。同样地,比较器2016将从放大器2013输出的信号水平与基准电压VR2进行比较,在小于基准电压VR2的情况下,向节点N6中输出正脉冲(图11的F)。节点N5、N6的输出分别通过反相器2015、2017翻转,每当输入负脉冲时通过将输出进行翻转的交叉锁定电路进行锁定并输出(图11的G)。
以上设为通过两组平板交换信号,但是在能够得到足够水平的信号的情况下,如图12所示,也能够通过一组平板121-1-1、221-1-1交换信号。在这种情况下,发送部1001-1-1由反相器1031、1032构成,输入到端子IN的信号通过反相器1031、1032提供给与端子N1连接的平板121-1-1。
接收部2002-1-1由反相器2031、2032、2033构成,通过反相器2031、2033从端子OUT输出来自与端子N2连接的平板221-1-1的信号。另外,反相器2031的输出通过反相器2032被反馈到反相器2031的输入。
当信号(图13的A)被输入到发送部1001-1-1的端子IN时,通过反相器1031、1032在端子N1(平板121-1-1)中产生电压(图13的B)。由于静电感应,在接收侧的平板221-1-1(输入端子N2)上也产生电压(图13的C)。当端子N2的电压大于反相器2031的阈值Vth时,反相器2031的输出进行翻转,反相器2032的输出也进行翻转,加速反相器2031的输入变化。反相器2031的输出进一步通过反相器2033进行翻转,从端子OUT输出(图13的D)。
以上,通过在硅中介层101至401上分别搭载通信芯片105至405、芯片106至406、107至407,从而形成所对应的电路,但是也可以通过直接装在各硅中介层101至401上而形成所对应的电路。
在图14所示的实施方式中,通过直接装在硅中介层101上而形成了通信电路151-1至151-4。同样地,通过直接装在硅中介层201上而形成了通信电路251-1至251-4。
在这种情况下,当组合硅中介层101和硅中介层201时成为如图15所示。在这种情况下,在硅中介层101的表面102上形成了与通信电路151-1至151-4对应的CMOS(Cosplementary Mental-Oxide Semiconductor:互补金属氧化物半导体)电路161。但是即使在该情况下,也与图8中的情况相同地形成了平板121-1。
另外,在硅中介层201上的表面202上,也形成了与通信电路251-1至251-4对应的CMOS电路261。在该情况下,也与图8中的情况相同,平板221-1形成在硅中介层201的表面202上。
因而,在该情况下也能够与图8中的情况相同地进行通信处理。
图16示出了硅中介层的通信区域111的内部截面结构的例子(图14、图15所示的实施方式中的CMOS结构没有图示)。在P型硅衬底1511上形成有场氧化膜1512。在场氧化膜1512上形成有多晶硅-金属硅化物(polycide)1513、和从多晶硅-金属硅化物1513隔有规定间隔的多晶硅-金属硅化物1514。多晶硅-金属硅化物1513、1514间的电容用于稳定电源。多晶硅-金属硅化物1513通过接点1515连接在金属层1516上。
通过通孔1517,连接金属层1516和在其上隔着氧化膜1518形成的金属层1519。通过通孔1522,连接金属层1519和在其上隔着氧化膜1520形成的金属层1521。在金属层1521上形成有氧化膜1523,进一步在其上形成有保护膜1524。在保护膜1524和氧化膜1523中形成有焊盘开口1525。
以上,以将本发明应用于多芯片模块的情况为例进行了说明,但是本发明也可以应用于其他的半导体装置。
此外,本发明的实施方式并不限于上述实施方式,在不超出本发明要领的范围内能够进行各种变更。
Claims (4)
1.一种半导体装置,其特征在于,具备:
第1板状部件,其是由高电阻的原材料构成的板状部件,在一个面上形成有电路;
第2板状部件,其是由高电阻的原材料构成的板状部件,在一个面上形成有电路;
在上述第1板状部件的形成有上述电路的面上配置的作为通信用天线的多个第1平板;
第1通信部,其配置在上述第1板状部件的形成有上述电路的面上,通过上述第1平板进行通信;
在上述第2板状部件的形成有上述电路的面上配置的作为通信用天线的多个第2平板;以及
第2通信部,其配置在上述第2板状部件的形成有上述电路的面上,通过上述第2平板进行通信,
上述第1板状部件和上述第2板状部件配置成使各自的没有形成上述电路的面相对。
2.根据权利要求1所述的半导体装置,其特征在于,
上述第1板状部件具有接受电力供给的接合线,
上述第2板状部件具有接受电力供给的凸块。
3.根据权利要求1所述的半导体装置,其特征在于,
上述第1板状部件和上述第2板状部件是硅中介层,其体积电阻率是1kΩcm以上。
4.根据权利要求1所述的半导体装置,其特征在于,
至少具备两组由上述第1板状部件和上述第2板状部件构成的组合,
一个组的上述第1板状部件和上述第2板状部件中的一个板状部件的形成有上述电路的面、与另一个组的上述第1板状部件和上述第2板状部件中一个板状部件的形成有上述电路的面,被配置成相互相对,在两者之间设置有通信用凸块和电力供给用凸块。
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JP2006031271A JP4725346B2 (ja) | 2006-02-08 | 2006-02-08 | 半導体装置 |
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EP (1) | EP1818986A3 (zh) |
JP (1) | JP4725346B2 (zh) |
KR (1) | KR101348742B1 (zh) |
CN (1) | CN100511670C (zh) |
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JP5578797B2 (ja) | 2009-03-13 | 2014-08-27 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP5801531B2 (ja) * | 2009-10-16 | 2015-10-28 | ルネサスエレクトロニクス株式会社 | 半導体パッケージ及びその製造方法 |
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US20110168784A1 (en) * | 2010-01-14 | 2011-07-14 | Rfmarq, Inc. | Wireless Communication Device for Remote Authenticity Verification of Semiconductor Chips, Multi-Chip Modules and Derivative Products |
ITTO20100697A1 (it) * | 2010-08-13 | 2012-02-14 | St Microelectronics Srl | Dispositivo elettronico con isolamento galvanico e procedimento per la fabbricazione di un dispositivo elettronico |
US8491315B1 (en) * | 2011-11-29 | 2013-07-23 | Plastronics Socket Partners, Ltd. | Micro via adapter socket |
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KR20130071884A (ko) | 2011-12-21 | 2013-07-01 | 삼성전자주식회사 | 다이 패키지 및 이를 포함하는 시스템 |
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CN101017813A (zh) | 2007-08-15 |
KR101348742B1 (ko) | 2014-01-08 |
EP1818986A3 (en) | 2011-02-02 |
US20080188096A1 (en) | 2008-08-07 |
TWI349359B (zh) | 2011-09-21 |
TW200805617A (en) | 2008-01-16 |
JP4725346B2 (ja) | 2011-07-13 |
JP2007214274A (ja) | 2007-08-23 |
EP1818986A2 (en) | 2007-08-15 |
US7351068B2 (en) | 2008-04-01 |
US7578676B2 (en) | 2009-08-25 |
KR20070080828A (ko) | 2007-08-13 |
US20070184677A1 (en) | 2007-08-09 |
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