CN100505275C - 双极晶体管和背栅晶体管的结构和方法 - Google Patents
双极晶体管和背栅晶体管的结构和方法 Download PDFInfo
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Abstract
本发明披露了一种包括衬底的结构，该衬底包括位于本体层上的绝缘体层，和位于衬底第一区域的双极晶体管，该双极晶体管包括位于绝缘体层内的发射区的至少一部分。被披露的另一种结构包括位于衬底第一区域的倒置双极晶体管，该衬底包括位于本体层上的绝缘体层，该倒置双极晶体管包括发射区和位于衬底第二区域的背栅晶体管，其中背栅晶体管的背栅导体和发射区的至少一部分位于材料的同一层。也披露了形成同时包括双极晶体管和背栅晶体管的结构的方法。
Description
技术领域
本发明从总体上涉及半导体制造，并且更具体地涉及一种结构和形成该结构的方法，包括双极晶体管和背栅晶体管，其中发射区和背栅导体处于材料的同一层。
背景技术
半导体制造行业一直在研究进一步缩小集成电路的方法。目前一个研究领域是使用背栅互补金属氧化物半导体(CMOS)晶体管(BGCMOS)来提供传统CMOS技术的进一步缩放比例。然而，这一领域的一个挑战是通过集成高性能双极晶体管来形成带有BGCMOS装置的双极CMOS装置(BiCMOS)。也就是说，传统的集成方案不能充分集成这两种技术。
鉴于以上所述，本技术领域需要一起产生双极晶体管和背栅晶体管的解决方案。
发明内容
在此披露了一种包括衬底的结构，该衬底包括处于本体层上的绝缘体层，和处于衬底第一区域的双极晶体管，该双极晶体管包括至少在绝缘体层内发射区的一部分。本发明披露的另一种结构包括位于衬底第一区域的反向双极晶体管，该衬底包括位于本体层上的绝缘体层，该反向双极晶体管包括发射区和位于衬底第二区域的背栅晶体管，其中背栅晶体管的背栅导体至少和发射区的一部分处于材料的同一层。同时也披露了包括双极晶体管和背栅晶体管的结构的形成方法。
本发明的第一方面提供了一种结构，该结构包括：包括位于本体层上的绝缘体层的衬底；和位于衬底第一区域的双极晶体管，该双极晶体管包括位于绝缘体层内的发射区的至少一部分。
本发明的第二方面提供了一种结构，该结构包括：位于衬底第一区域的反向双极晶体管，该衬底包括位于本体层上的绝缘体层，该反向双极晶体管包括发射区；和位于衬底第二区域的背栅晶体管，其中背栅晶体管的背栅导体和发射区的至少一部分处于材料的同一层。
本发明的第三方面提供了形成一种结构的方法，该方法包括以下步骤：在衬底上形成双极晶体管，该衬底包括位于本体层上的绝缘体层，该双极晶体管包括发射区；和在衬底上形成背栅晶体管，其中背栅晶体管的背栅导体和发射区位于材料的同一层。
本发明的示例性方面是设计来解决此处描述的问题的以及其他未讨论却能够被技术人员发现的问题。
附图说明
通过以下结合附图对本发明各方面详尽的描述可以更容易的理解本发明的这些和其他特征，这些附图描述了本发明的各种实施例，其中：
图1示出按照本发明结构的一个实施例。
图2-12示出按照本发明形成图1-2所示结构的方法的一个实施例。
应注意到本发明的附图不是按比例尺的。附图仅仅是用来描述本发明的典型方面的，因此不应理解为对本发明范围的限制。在这些附图中，类似的编号代表附图间类似的元件。
具体实施方式
参看附图，图1示出了按照本发明的一个实施例形成的结构100。结构100包括衬底102，该衬底包括位于本体层106(例如硅)上的绝缘体层104。绝缘体层104可以包括电介质材料，例如二氧化硅或者蓝宝石。(反向)双极晶体管108被提供在衬底102的第一区域110并且包括位于绝缘体层104的发射区112的至少一部分。图1示出了一个实施例，其中至少一部分，优选几乎全部发射区112位于绝缘体层104内。结构100还包括位于衬底102第二区域122的背栅(双栅极)晶体管120。背栅晶体管120包括在绝缘体层104内形成的背栅导体124。在一个实施例中，发射区112和背栅导体124位于可以包括在绝缘体层104内的材料126的同一层的各自部分，。发射区112和背栅导体124可以包括单晶硅和多晶硅中的一种，该单晶硅和多晶硅可以是掺杂的。发射区112和背栅导体124也可以分别包括硅化物部分128，例如硅化钨。关于双极晶体管108，其集电极区域130在非本征基极区132上(在本征基极区134的附近)上延伸并且由此处被该处电介质136的一部分部分隔离。集电极区域130可以是适当掺杂的单晶硅。
参看图2-12，现在将描述形成上述结构方法的一个说明性实施例。如图1所示，该方法总体上包括在衬底102上形成双极晶体管108，该衬底102包括位于本体层106b上的绝缘体层104，该双极晶体管包括发射区112，并且在衬底102上形成背栅晶体管120。如上所述，背栅晶体管120的背栅导体124和发射区112优选位于材料126的同一层。如下所述，形成步骤至少部分同时进行。
参看形成结构100(图1)的方法的说明性实施例，图2示出了执行本发明的初步结构200。在一个实施例中，提供了超薄绝缘体上硅(UTSOI)结构形式的衬底102。在这种情况下，超薄硅层202，(例如大约10-70nm)被提供在绝缘体层204上，该绝缘体层被提供在本体层106b(例如硅)上。绝缘体层204可以包括电介质材料，例如二氧化硅(SiO2)(氧化物)，或者可以是氢(H2)或者氦(He)注入的硅。栅极绝缘体层206，例如二氧化硅(SiO2)或者氮氧化硅(SiON)或者高电介质常数材料，例如硅酸铪也可以在这一阶段提供。(尽管没有示出，但在栅极绝缘体层206形成之前，可选地提供用来形成双极晶体管108的本征基极区134(图1)和背栅晶体管120的其他区域的硅层202适当的屏蔽掩模(block mask)和掺杂。本领域技术人员可以理解，这些区域也可以在本工艺的其他阶段形成)。图2也示出了包括用于刻蚀的开口210的掩模208，用于刻蚀穿过栅极绝缘体层206的开口。
如图3所示，下一步包括，通过例如沉积形成多晶硅层212，和在多晶硅层212上形成硅化物层214，例如硅化钨。多晶硅层212和硅化物层214最终成为发射区112(图1)和背栅导体124(图1)。如上所述，硅化物层214在有些情况下可以省略。作为另一种替代方法，多晶硅层212可以用单晶硅替代，例如通过外延生长形成。
下一步如图4所示，多晶硅层212(图3)和硅化物层214(图3)被构图和蚀刻，从而形成发射区112和背栅导体124。图5示出了通过传统方式的离子注入形成的非本征基极区132，例如使用掩模和离子注入。图6示出了掩模214(图5)去除之后绝缘体层104的形成。这一步骤可以包括例如沉积如二氧化硅(SiO2)的电介质材料和平面化。
图7示出了倒置部分形成的双极晶体管108(图1)和背栅晶体管120(图1)的结构的步骤。图7示出了倒置的并且重新粘接到新本体层106上(例如硅)的结构。正如本技术领域公知的那样，在有些情况下，本体层106可以包括其上面的电介质材料层，例如二氧化硅(SiO2)，从而确保电介质到电介质之间的接合。
如图8所示，下一步包括从目前是硅层202顶面的地方切割起始晶片。这一步骤可以包括任何目前公知的或者以后开发的切割工艺，例如“智能切割工艺(smart-cut process)”或者蚀刻本体层106和绝缘体层204。智能切割工艺包括使用氢的晶片注入，将该晶片的顶部接合到第二个晶片(硅上氧化物)，和对最初衬底进行退火、分裂。新暴露的硅层202表面可以被抛光和/或牺牲二氧化硅层被形成和剥离以提高表面质量。
图9示出了浅沟道隔离(STI)220的传统形成。图10示出了栅极电介质层222的形成，例如二氧化硅(SiO2)，然后是栅极电极材料224，例如多晶硅、铜等的形成。图11示出了经过此后大量的传统步骤之后的结构，这些步骤包括对栅极电介质层222和栅极电极材料224(图10)进行构图和蚀刻从而形成栅极电极226；为栅极电极226形成延伸和晕环(没有示出)；和沉积、构图和蚀刻电介质膜，例如二氧化硅(SiO2)和/或氮化硅(Si3N4)(未示出)，从而为栅极电极226形成电介质帽层230和隔离件232。至于后面的步骤，开口234被提供在位于基极区132和134上的电介质帽层230上。应该认识到在这一阶段，可以提供本领域技术人员公知的跟基极区132和134的形成和/或调整有关的多种不同技术。
图12示出了基极区132和134上集电极区域130的形成。依赖于上述的基极区132和134的形成/或调整，集电极区域130能够以多种方式形成。例如，集电极区域130可以是通过原位或通过注入而掺杂的选择性生长的硅。在集电极生长之前或者作为集电极生长的初始阶段，可以形成硅锗(SiGe)层从而用作本征基极区。这一硅锗基极生长可以有选择的包括蚀刻双极晶体管结构中的层202的全部或者一些部分(层124上的区域)。可替换地，集电极区域130可以通过多晶硅分级形成，从而在集电极区域130形成可变掺杂。在任何情况下，集电极区域130都可以被一次性全部注入，从而获得适当的掺杂。然而，注意的是，集电极区域130被形成以延伸到非本征基极区132上，并且在该处被电介质的一部分136，也就是电介质帽层230的一部分所部分地隔离。
回到图1，抛光步骤可以包括，例如，为集电极区域130形成隔离件240，例如，通过沉积和蚀刻氮化硅(Si3N4)并且定向蚀刻去除电介质帽层230的残余物。
应该认识到以上描述的方法仅仅是说明性的，也可以使用其他步骤来形成结构100。以上对本发明不同方面的描述仅是出于说明和描述的目的。以上描述不倾向于彻底详尽，或者将本发明限制为所披露的精确形式；明显地，许多变更和变化是可能的。对本领域技术人员来说，显而易见这样的变更和变化倾向于被包括在所附权利要求书限定的本发明的范围之内。
Claims (14)
1.一种结构，包括：
包括位于本体层上的绝缘体层的衬底；
衬底的第一区域中的倒置双极晶体管，该倒置双极晶体管包括绝缘体层中的发射区的至少一部分，该倒置双极晶体管的本征基极区位于发射区的上方，集电极区在本征基极区和本征基极区附近的非本征基极区上延伸并且在非本征基极区处被电介质的一部分部分地隔离；和
衬底的第二区域中的背栅晶体管，该背栅晶体管包括在绝缘体层中形成的背栅导体。
2.如权利要求1所述的结构，其中全部的所述发射区位于绝缘体层内。
3.如权利要求1中所述的结构，其中所述发射区和背栅导体分别处于绝缘体层内的材料的同一层的各自的部分。
4.如权利要求3所述的结构，其中所述发射区和背栅导体包括单晶硅和多晶硅的其中之一。
5.如权利要求1所述的方法，其中所述绝缘体层是电介质材料、氢(H2)注入硅和氦(He)注入硅中的一种。
6.一种结构，其包括：
衬底的第一区域中的倒置双极晶体管，该衬底包括位于本体层上的绝缘体层，该倒置双极晶体管包括发射区，倒置双极晶体管的本征基极区位于发射区的上方，集电极区在本征基极区和本征基极区附近的非本征基极区上延伸并且在非本征基极区处被电介质的一部分部分地隔离；以及
衬底的第二区域中的背栅晶体管，
其中背栅晶体管的背栅导体和发射区的至少一部分位于绝缘体层内的材料的同一层。
7.如权利要求6所述的结构，其中全部的所述发射区位于绝缘体层内。
8.如权利要求6所述的结构，其中所述发射区和背栅导体包括单晶硅和多晶硅的其中之一。
9.形成一种结构的方法，该方法包括以下步骤：
在衬底上形成双极晶体管，该衬底包括位于本体层上的绝缘体层，该双极晶体管包括发射区；
在衬底上形成背栅晶体管，其中背栅晶体管的背栅导体和该发射区位于绝缘体层内的材料的同一层；以及
将部分地形成的双极晶体管和背栅晶体管的结构倒置。
10.如权利要求9所述的方法，其中所述在衬底上形成双极晶体管的步骤和所述在衬底上形成背栅晶体管的步骤至少部分地同时发生。
11.如权利要求9所述的方法，其中所述发射区和背栅导体包括单晶硅和多晶硅其中之一。
12.如权利要求9所述的方法，其中所述双极晶体管的形成步骤包括形成绝缘体层中的发射区的至少一部分。
13.如权利要求12所述的方法，其中所述发射区的形成步骤包括在绝缘体层中形成全部发射区。
14.如权利要求9所述的方法，其中所述双极晶体管形成步骤包括形成集电极区，该集电极区在非本征基极区上延伸并且在非本征基极区处被电介质的一部分部分地隔离。
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/164,071 US20070102789A1 (en) | 2005-11-09 | 2005-11-09 | Bipolar transistor and back-gated transistor structure and method |
| US11/164,071 | 2005-11-09 |
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| CN100505275C true CN100505275C (zh) | 2009-06-24 |
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| US8552532B2 (en) * | 2012-01-04 | 2013-10-08 | International Business Machines Corporation | Self aligned structures and design structure thereof |
| US9209095B2 (en) * | 2014-04-04 | 2015-12-08 | International Business Machines Corporation | III-V, Ge, or SiGe fin base lateral bipolar transistor structure and method |
| US9859172B1 (en) * | 2016-09-29 | 2018-01-02 | International Business Machines Corporation | Bipolar transistor compatible with vertical FET fabrication |
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| US4860086A (en) * | 1983-08-30 | 1989-08-22 | Hitachi, Ltd. | Semiconductor device |
| US5315151A (en) * | 1991-06-14 | 1994-05-24 | International Business Machines Corporation | Transistor structure utilizing a deposited epitaxial base region |
| US5352624A (en) * | 1992-01-23 | 1994-10-04 | Sony Corporation | SOI type semiconductor device and manufacturing method therefor |
| US5736447A (en) * | 1994-06-13 | 1998-04-07 | Samsung Electronics Co., Ltd. | Method for manufacturing a bipolar junction transistor having a polysilicon emitter |
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|---|---|---|---|---|
| GB1392599A (en) * | 1971-07-28 | 1975-04-30 | Mullard Ltd | Semiconductor memory elements |
| TW328641B (en) * | 1995-12-04 | 1998-03-21 | Hitachi Ltd | Semiconductor integrated circuit device and process for producing the same |
| JP3810246B2 (ja) * | 2000-03-15 | 2006-08-16 | 株式会社ルネサステクノロジ | 半導体装置および半導体装置の製造方法 |
| DE10159414A1 (de) * | 2001-12-04 | 2003-06-18 | Infineon Technologies Ag | Bipolar-Transistor und Verfahren zum Herstellen desselben |
| JP2005005446A (ja) * | 2003-06-11 | 2005-01-06 | Renesas Technology Corp | 半導体装置およびその製造方法 |
| US7217988B2 (en) * | 2004-06-04 | 2007-05-15 | International Business Machines Corporation | Bipolar transistor with isolation and direct contacts |
-
2005
- 2005-11-09 US US11/164,071 patent/US20070102789A1/en not_active Abandoned
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2006
- 2006-11-08 CN CNB200610143976XA patent/CN100505275C/zh not_active Expired - Fee Related
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4860086A (en) * | 1983-08-30 | 1989-08-22 | Hitachi, Ltd. | Semiconductor device |
| US5315151A (en) * | 1991-06-14 | 1994-05-24 | International Business Machines Corporation | Transistor structure utilizing a deposited epitaxial base region |
| US5352624A (en) * | 1992-01-23 | 1994-10-04 | Sony Corporation | SOI type semiconductor device and manufacturing method therefor |
| US5736447A (en) * | 1994-06-13 | 1998-04-07 | Samsung Electronics Co., Ltd. | Method for manufacturing a bipolar junction transistor having a polysilicon emitter |
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| Publication number | Publication date |
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| US20090298250A1 (en) | 2009-12-03 |
| US20070102789A1 (en) | 2007-05-10 |
| CN1964057A (zh) | 2007-05-16 |
| US7939417B2 (en) | 2011-05-10 |
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