CN100505252C - 埋入式芯片封装结构 - Google Patents

埋入式芯片封装结构 Download PDF

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CN100505252C
CN100505252C CNB2005101184910A CN200510118491A CN100505252C CN 100505252 C CN100505252 C CN 100505252C CN B2005101184910 A CNB2005101184910 A CN B2005101184910A CN 200510118491 A CN200510118491 A CN 200510118491A CN 100505252 C CN100505252 C CN 100505252C
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许诗滨
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Quanmao Precision Science & Technology Co Ltd
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Abstract

一种埋入式芯片封装结构，包含有：一第一金属板；形成有至少一贯穿开口的一第二金属板，设于第一金属板的上表面且与第一金属板构成一散热基板；至少一个半导体芯片及至少一个芯片式电容元件分别连接设置于第一金属板而容纳于第二金属板的贯穿开口中；一无源元件层，设置于第二金属板的部分上表面；以及至少一个线路增层结构，设于散热基板表面并覆盖半导体芯片、芯片式电容元件与无源元件层。

Description

埋入式芯片封装结构
技术领域
本发明涉及一种埋入式芯片封装结构，具体而言，涉及一种将有源及无源元件连接设置于线路增层(build-up layer)结构与散热基板之间的埋入式芯片封装结构。
背景技术
近年来，随着信息家电产品以及通讯产品的蓬勃发展，信息传输的容量大为扩增，讯号传输的速度要求也大幅提高，同时在多功能手持式电子产品的驱动下，半导体工艺发展无可避免朝高容量、窄线宽的高密度化、高频、低耗能、多功能整合方向演进。
因此在IC封装技术方面，为配合高I/O数、高散热以及封装尺寸缩小化的高标要求下，使得芯片级封装(Chip Scale Package，CSP)、倒装片(FlipChip，FC)等高阶封装型态需求持续升高。另外，电路板的叠层(lamination)技术也就必须朝向厚度薄、多层数与高布线密度的特点发展，并为了更进一步能缩小电路板的空间需求，而发展出表面设置有倒装片芯片以及如电阻器、电容器与电感器等的无源元件的多层电路板。
然而，倒装片芯片与设置于多层电路板表面的无源元件仍需透过多层电路板中的线路层电性连接，故往往因为连接路径太长，而影响电性的表现。因此，多层电路板内部空间的运用以达到缩小体积、提高芯片的散热效率以及缩短与半导体芯片之间连接路径的距离，以达到轻薄短小、高效能的封装结构，皆是急需克服与发展的方向。
发明内容
有鉴于此，本发明的主要目的在于提供一种埋入有源及无源元件的埋入式芯片封装结构，以改善前述的缺点。
为达上述目的，根据本发明的优选实施例，本发明的结构包含有：一第一金属板；一第二金属板，设于该第一金属板的上表面，该第二金属板形成有至少一贯穿开口，且该第二金属板与该第一金属板构成一散热基板；至少一个半导体芯片及至少一个芯片式电容元件分别连接设置于该第一金属板表面，而容纳于该第二金属板所形成的该贯穿开口中；一无源元件层，设置于该第二金属板的部分上表面；以及至少一线路增层结构，设于该散热基板表面并覆盖该半导体芯片、该芯片式电容元件与该无源元件层。其中本发明结构中的该线路增层结构包含有：一介电层；至少一个形成于介电层上的线路层；以及至少一个穿过介电层以导接至线路层的导电盲孔，以使该线路增层结构得以透过该导电盲孔电性连接至该芯片式电容元件、半导体芯片及无源元件层；且该线路增层结构的外缘表面形成有一防焊层，且该防焊层形成有多个开孔以显露出部分该线路层作为多个电性连接垫。
由于本发明将有源元件与无源元件设置于一散热基板表面，因此具有以下优点：(1)可以提升电子元件的散热效果。(2)因布线距离的缩短，可以提升产品的性能。(3)因布线空间应用更佳，可以缩小产品的体积。(4)本发明的无源元件层形成一金属-绝缘层-金属间隔结构的电容。
为了使能更近一步了解本发明的特征及技术内容，请参阅以下有关本发明的详细说明与附图。然而附图仅供参考与辅助说明用，并非用来对本发明加以限制。
附图说明
图1为本发明的优选实施例中的埋入有源及无源元件的埋入式芯片封装结构剖视图。
图2为本发明的图1上设置倒装片元件的结构剖视图。
图3为本发明的图2上设置无源元件的结构剖视图。
附图标记说明
3 线路增层结构      4 线路增层结构
5 防焊层            6 锡球
7 倒装片元件        8 无源元件
10 第一金属板       12 第二金属板
14 散热基板         16 贯穿开口
17 贯穿开口         18 半导体芯片
19 芯片式电容元件   20 无源元件层
22 线路层            31 介电层
32 线路层            33 导电盲孔
34 开口              36 电性连接垫
41 介电层            42 线路层
43 导电盲孔          71 焊料凸块
81 焊料凸块          181 电极垫
191 电极垫
具体实施方式
请参考图1，图1为本发明的优选实施例中的埋入有源及无源元件的埋入式芯片封装结构剖视图。如图1所示，此结构的底部为一第一金属板10，然后，一第二金属板12设于第一金属板10的上表面且与第一金属板10构成一散热基板14。其中第二金属板12形成有至少一个贯穿开口，例如：贯穿开口16及17。本发明的第一金属板10与第二金属板12可由相同或不同的金属材料所构成。例如蚀刻一金属板，以在此金属板形成具有一预定深度的凹口，进而构成具有贯穿开口的第二金属板12以及第一金属板10。或者直接在一金属板表面形成一具有贯穿开口的另一金属层，以构成具有贯穿开口的第二金属板12并形成于第一金属板10表面的散热基板14结构。此外，本发明的图1所示的第一金属板10也可为单一金属层、多层的金属-金属或金属-绝缘材料-金属的叠层结构，而且凡具有良好的导热功能的金属材料皆为本发明应用涵盖的范畴。
随后将至少一个半导体芯片18及一芯片式电容元件19用粘结材料(图未示)分别接置于第一金属板10而容纳于第二金属板12所形成的贯穿开口16及17中。其中，半导体芯片18的有源面包含有多个电极垫181，而半导体芯片18可为有源元件，例如：内存、发光元件或集成电路芯片等，而芯片式电容元件19也如类似半导体芯片具有包含有多个电极垫191的有源面。将本发明的半导体芯片18应用一种粘结材料(图未示)固定于第一金属板10的上表面；同理，将芯片式电容元件19也应用一种粘结材料固定于第一金属板10的上表面，如此不但可使半导体芯片18与芯片式电容元件19的向外电性连接的距离缩短，进而提升电性效能；而连接设置于金属板表面更能有效提升各电子元件的散热效率，而有较好的电性表现。
然后在第二金属板12的部分上表面设置一无源元件层20。无源元件层20可为一具有高介电常数的介电材料层，且此介电材料层表面设置有至少一个由一金属层所构成的线路层22，其中线路层22、介电材料层及第二金属板12形成一金属-绝缘层-金属(Metal-Insulator-Metal，MIM)间隔结构的电容。接下来，形成一线路增层结构3及一线路增层结构4于散热基板14表面并覆盖在芯片式电容元件19、半导体芯片18与无源元件层20上方。其中，线路增层结构3、4分别包含有：介电层31、41；形成于介电层31、41上的线路层32、42；以及穿过介电层31、41以导接至线路层32，42的导电盲孔33、43，以使线路增层结构3、4得以透过导电盲孔33，43电性连接至半导体芯片18及芯片型电容元件19的各有源面上的多个电极垫181、191；无源元件层20上的线路层22与第二金属板12表面、用以导通半导体芯片18、芯片型电容元件19及无源元件层20上的线路层22，并可视实际产品设计的需求而选择性的电性连接散热基板14以制作成具有接地的功能。且线路增层结构4的外缘表面形成有一防焊层5，防焊层5形成有多个开孔34以显露出部分线路层42作为多个电性连接垫36。如此即完成本发明的埋入有源及无源元件的埋入式芯片封装结构。
值得注意的是，完成本发明的优选实施例之后，如图2所示，本发明更可结合倒装片封装技术，而在线路增层结构4外缘表面形成有一防焊层5，且防焊层5形成有多个开孔34以显露出部分线路层42作为电性连接垫36，并接置有多个锡球6与至少一个倒装片元件7，而倒装片元件7可例如内存、发光元件或集成电路芯片等；且倒装片元件7以多个焊料凸块71电性连接部分的电性连接垫36，使倒装片元件7与封装结构内部的半导体芯片18、芯片型电容元件19与无源元件层20作电性导接。其中倒装片元件7更可通过线路增层结构3、4而与散热基板14电性连接以达成接地功能。
另外值得注意的是，如图3所示，本发明也可在电性连接垫36上接置至少一个无源元件8，其中无源元件8可例如为电容、电感、电阻等；而无源元件8利用多个焊料凸块81电性连接部分的电性连接垫36，使无源元件8与封装结构内部的半导体芯片18、芯片型电容元件19与无源元件层20作电性导接。
此外，本发明的散热基板14未与线路增层结构相接合的表面另可设置有至少一个散热结构(图未示)，例如粗糙表面、凹槽、刻痕或是鳍状的立体散热结构，用以增加散热基板14的散热面积。
综合上述，本发明的埋入有源及无源元件的埋入式芯片封装结构相较现有技术至少包括以下的优点：
散热基板可以提升埋入电子元件的散热效果；
有源与无源元件连接到散热基板进行接地，故可大幅提升电性表现与减少噪声；
整合有源元件及无源元件埋入基板内，且无源元件层形成一金属-绝缘层-金属间隔结构的电容；
缩短布线的距离，可有效提升产品的性能，并达到高功能及高性能的目的并使布线空间应用更佳，可以缩小产品的体积；
埋入的有源元件及无源元件与线路增层结构表面的倒装片元件及无源元件可以达到模块化与多功能化的目的。
以上所述仅为本发明的优选实施例，凡依本发明的权利要求所做的等同变化与修饰，皆应属本发明的涵盖范围。

Claims (10)

1、一种埋入式芯片封装结构，包含有：
一第一金属板；
一第二金属板，设于所述第一金属板的上表面，所述第二金属板形成有至少一贯穿开口，且所述第二金属板与所述第一金属板构成一散热基板；
至少一个半导体芯片及至少一个芯片式电容元件，分别连接设置于所述第一金属板表面，而容纳于所述第二金属板所形成的所述贯穿开口中；
一无源元件层，为一高介电常数的介电材料层并设置于所述第二金属板的部分上表面；
至少一个线路层，由一金属层构成并设置在所述介电材料层的表面上；以及
至少一个线路增层结构，设于所述散热基板表面并覆盖所述半导体芯片、所述芯片式电容元件与所述无源元件层，
其中，所述金属层、所述介电材料层及所述第二金属板形成一金属-绝缘层-金属的间隔结构的电容。
2、如权利要求1所述的埋入式芯片封装结构，其中，所述半导体芯片与所述芯片式电容元件另分别包含有多个电极垫形成于一有源面。
3、如权利要求1所述的埋入式芯片封装结构，其中，所述半导体芯片为一有源元件，且所述有源元件包含发光元件及集成电路芯片的其中一者。
4、如权利要求1所述的埋入式芯片封装结构，其中，所述线路增层结构包含有：
一第一介电层；
至少一个形成于所述第一介电层上的第一线路层；以及
至少一个穿过所述第一介电层以导接至所述第一线路层的导电盲孔，以使所述线路增层结构得以透过所述导电盲孔电性连接至所述芯片式电容元件、半导体芯片及无源元件层。
5、如权利要求4所述的埋入式芯片封装结构，另包含有一防焊层，且所述防焊层形成于所述线路增层结构的外缘表面，并形成有多个开孔以显露出部分所述第一线路层作为多个电性连接垫。
6、如权利要求4所述的埋入式芯片封装结构，其中，所述线路增层结构可电性连接所述散热基板以达成接地功能。
7、如权利要求5所述的埋入式芯片封装结构，另包含有至少一倒装片芯片，设置于所述线路增层结构的外缘表面，并电性连接部分的所述多个电性连接垫。
8、如权利要求5所述的埋入式芯片封装结构，另包含有至少一个无源元件，设置于所述线路增层结构的外缘表面，并电性连接部分的所述多个电性连接垫。
9、如权利要求1所述的埋入式芯片封装结构，其中，所述散热基板未与所述线路增层结构相接合的表面另设置有至少一个散热结构。
10、如权利要求1所述的埋入式芯片封装结构，其中，所述半导体芯片及所述芯片式电容元件可通过线路增层结构电性连接所述散热基板以达成接地功能。
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