CN100466212C - Semiconductor package and its making method - Google Patents

Semiconductor package and its making method Download PDF

Info

Publication number
CN100466212C
CN100466212C CNB2005100753331A CN200510075333A CN100466212C CN 100466212 C CN100466212 C CN 100466212C CN B2005100753331 A CNB2005100753331 A CN B2005100753331A CN 200510075333 A CN200510075333 A CN 200510075333A CN 100466212 C CN100466212 C CN 100466212C
Authority
CN
China
Prior art keywords
base board
board unit
semiconductor
chip
heat sink
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB2005100753331A
Other languages
Chinese (zh)
Other versions
CN1877802A (en
Inventor
蔡和易
黄建屏
洪敏顺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siliconware Precision Industries Co Ltd
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Priority to CNB2005100753331A priority Critical patent/CN100466212C/en
Publication of CN1877802A publication Critical patent/CN1877802A/en
Application granted granted Critical
Publication of CN100466212C publication Critical patent/CN100466212C/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

The invention discloses a semiconductor packing part and preparing method, which comprises the following parts: base, semiconductor chip, radiating part and packing colloid, wherein the base with chip is placed in the mould with nest in the semiconductor packing punching operation, which chucks the base through the lateral of base circuit layout region; cutting to remove packing colloid and preset part larger than base size. The invention can avoid destroy base effectively, which improves chip radiating property for semiconductor packing part.

Description

Semiconductor package part and method for making thereof
Technical field
The invention relates to a kind of semiconductor package part and method for making thereof, particularly about a kind of when the semiconductor packages mold pressing processing procedure, prevent that base plate line from being weighed and integrating wounded the semiconductor package part and the manufacture method thereof of heat sink.
Background technology
Because increasing substantially of various portable (Portable) products such as communication, network and computer, can dwindle integrated circuit (IC) area and have high density and the ball grid array of many pinizations characteristic (BGA) packaging part day by day becomes the main flow of encapsulation on the market, and normal and high-effect chip collocation such as microprocessor, chipset, drawing chip, with the performance calculation function of high speed more.Wherein, ball grid array (BGA) is a kind of advanced person's a semiconductor die package technology, it adopts substrate to settle semiconductor chip, and plant at this substrate back and to put the soldered ball (Solder Ball) that a plurality of one-tenth grid arrays are arranged, make on the semiconductor chip carriers of same units area and can hold more I/O link (I/O Connection), with the needs of the semiconductor chip that adapts to Highgrade integration (Integration), by these soldered balls with whole encapsulation unit welding and be electrically connected to external device (ED).
See also Figure 1A to Fig. 1 C, traditionally as U.S. Pat 5,652,185 and 6,552,428 disclosed with the semiconductor package part (as ball grid array (BGA) semiconductor package) of substrate as chip carrier (Chip Carrier), when encapsulating mold pressing (Molding), be with the packing colloid coating chip at this substrate for chip on sticking surface of putting.As shown in the figure; in the mold pressing processing procedure; the substrate 11 that is bonded with chip 10 is interposed in the mould with patrix 12 and counterdie 13; just the clamped areas (clamping area) with this patrix 12 corresponds to predetermined mold clamping line MCL (mold clamp line) on this substrate 11; and this patrix 12 has die cavity 120; for potting resin wherein from injection molding mouth 110 streamers; till this die cavity 120 is filled up fully; be formed for coating the packing colloid 14 of this semiconductor chip 10; protect semiconductor chip 10 can not be subjected to the influence of the moisture of external environment condition or pollution whereby and damage; for follow-up when cutting single job; the edge is the die-cut substrate 11 in the pre-set dimension of this packaging part (PKG line) P position respectively; just carry out die-cut (Punch) along the die-cut line on this substrate 11 (being packaging part pre-set dimension position); form required semiconductor package part, and the size of this packing colloid 14 is less than these semiconductor package part substrate 11 sizes.
Because when carrying out molding operation, be to connect the substrate that is equipped with chip to be interposed in the upper and lower intermode of mould and matched moulds, for the follow-up potting resin of filling therein, like this, when if clamping pressure is big, hallrcuts (Micro-Crack) can take place because of the layer (Solder Mask) of refusing that improper pressurized will make its surface go up coating in substrate, can cause the fracture of base plate line pressurized when serious, has influence on the reliability on the manufactured goods electrical property.Moreover, clamping pressure is excessive to cause occurring on the substrate problems such as hallrcuts or rupture of line if avoid, when clamping pressure is reduced, tend to cause between the bottom surface of upper surface of base plate and patrix and form the gap, potting resin mould stream infiltrates in this gap in the mold pressing processing procedure, the glue (Flash) that overflows takes place on the surface that causes the not packed colloid lid of substrate to cover, glue can be removed after the mold pressing processing procedure is finished though overflow, but can increase manufacturing cost and processing procedure, and also easily injure substrate or packing colloid accidentally, cause the acceptance rate of manufactured goods to reduce because of handling.
See also Fig. 2, for solving above-mentioned excessive glue problem, United States Patent (USP) 5,744 proposes for No. 084 a kind ofly on substrate 21 surfaces ponding structure 25 to be set, and for connecing the clamped areas of putting patrix 22, and then prevents above-mentioned excessive glue phenomenon.Yet this ponding structure 25 must additionally be made and its processing procedure complexity the requirement when not meeting actual production after the base plate line layout is finished; Moreover this method still can't solve problems such as the base plate line that is caused when substrate is inserted and put by mould is weighed wounded.
See also Fig. 3 A and Fig. 3 B, it is a United States Patent (USP) 6,452, the method for making of the 268 another kind of semiconductor piece installings that disclose, mainly be to offer outward extending recess (Recess) 321 being used for the patrix (UpperMold) 32 that compression molding goes out the packing colloid mould, patrix 32 matched moulds that make mould are to counterdie (Lower Mold) 33, clamp (Clamp) and live this substrate 31, injecting glue in the die cavity 320 of patrix 32 after, make potting resin from injection molding mouth streamer to this die cavity 320, wherein, the potting resin mould stream of fusion is when flowing into this patrix recess 321, can quicken to absorb the heat of mould because of runner narrows down, cause the viscosity change of mould stream to make its flow velocity slow down greatly, thereby avoid resin mold slime flux glue between the composition surface of substrate 31 and patrix 32; After the mold pressing processing procedure is finished, can form the packing colloid 34 that coats semiconductor chip 30, and to flow into potting resins in this recess 321 be that curing molding is the shoulder 341 that the bottom from this packing colloid 34 outwards stretches out.
But, though strength that can be when opening being set in this patrix reducing the mould clamping in above-mentioned processing procedure, but its effect is still limited, can't effectively solve problems such as base plate line is weighed wounded, especially when being applied in the additional layers substrate of high-end Chip Packaging, but under micron situation of line width miniaturization to 20, be subjected to the sensitiveness of mould clamping also higher, so the circuit pressurized breakage problem that can't avoid substrate to cause fully because of the mould clamping.Moreover need to change Mould design earlier when implementing, the extra recess that forms can cause the increase of cost like this in patrix.
In addition, when moving, have a large amount of heats and produce,, can cause the loss efficient of heat not good, the performance and the useful life of jeopardizing semiconductor chip as can't effectively providing semiconductor chip good heat radiation approach because of the Highgrade integration semiconductor chip.
Therefore, how effectively solving in the mold pressing processing procedure problems such as causing the fracture of circuit pressurized because of clamping pressure is improper, and can avoid the increase of processing procedure cost, also can improve the radiating efficiency of BGA semiconductor package part simultaneously, is the big problem that industry need solve.
Summary of the invention
For overcoming the shortcoming of above-mentioned prior art, main purpose of the present invention is to provide a kind of semiconductor package part and the method for making thereof that can avoid weighing wounded base plate line in Encapsulation Moulds compacting journey.
Another object of the present invention is to provide a kind of semiconductor package part and method for making thereof of not using special mould just can avoid weighing wounded in the Encapsulation Moulds compacting journey base plate line.
A further object of the present invention is to provide a kind of connecing on chip to put heat sink, the semiconductor package part that can improve chip cooling and method for making thereof.
For reaching above-mentioned and other purpose, the invention provides a kind of method for producing semiconductor packaging part and comprise: the substrate module that comprises a plurality of base board units sheet is provided, at least one semiconductor chip is connect put and be electrically connected on this base board unit; With respectively this connects the base board unit that is equipped with semiconductor chip and is contained in the mould that is formed with die cavity, be filled in this die cavity for potting resin, corresponding each base board unit forms a plurality of individual packages colloids that envelope this semiconductor chip on this substrate module sheet, and wherein the size of this packing colloid is greater than the pre-set dimension of this semiconductor package part; And carry out cutting operation along the pre-set dimension position of this semiconductor package part, remove in this packing colloid and the base board unit size greater than the part of this packaging part pre-set dimension.Can plant a plurality of soldered balls at this base board unit back side in addition.
The alternative method for producing semiconductor packaging part of the present invention is to connect to put heat sink on chip, improve the radiating efficiency of semiconductor chip, this method for making comprises: the substrate module that comprises a plurality of base board units sheet is provided, at least one semiconductor chip is connect put and be electrically connected on this base board unit; On the chip of this base board unit respectively, connect and put a heat sink; Respectively this connects the base board unit that is equipped with semiconductor chip and heat sink and is contained in the mould that is formed with die cavity with correspondence, supply the potting resin filling in this die cavity, corresponding each base board unit forms a plurality of individual packages colloids that envelope this semiconductor chip and heat sink on this substrate module sheet, and wherein the size of this packing colloid is greater than the pre-set dimension of this semiconductor package part; And carry out cutting operation along the pre-set dimension position of this semiconductor package part, remove in this packing colloid and the base board unit size greater than the part of this packaging part pre-set dimension.Can plant a plurality of soldered balls at this base board unit back side in addition.The size of this heat sink can be greater than or less than the packaging part pre-set dimension.
By above-mentioned method for making, a kind of semiconductor package part provided by the invention comprises: substrate, and this substrate has first surface and opposing second surface; Semiconductor chip connects and puts and be electrically connected on this substrate first surface; Heat sink connects and puts on this semiconductor chip; And packing colloid, be formed on this substrate first surface by a mould that is formed with die cavity, and the die cavity size of this mould is greater than the pre-set dimension of semiconductor package part, avoid mould to weigh the circuit of substrate wounded, envelope this heat sink and semiconductor chip for this packing colloid, and the side of this packing colloid and substrate is cut mutually flat.
This semiconductor package part also can comprise a plurality of soldered balls that plant at this substrate second surface.The size of this heat sink can select to be greater than or less than the pre-set dimension of packaging part in addition, and the side of this heat sink of confession and the side of this packing colloid and substrate are cut flat mutually, or the side of this heat sink is embedded in the packing colloid.
Semiconductor package part of the present invention and method for making thereof mainly are in the molding operation of semiconductor packing process, the substrate that chip is then arranged is contained in the mould with die cavity, and make the pre-set dimension of the die cavity size of this mould greater than semiconductor package part, the part that just makes this mould be used for this substrate of cramping is the outside in this base plate line layout district, avoid mould to weigh the circuit of substrate wounded, for follow-up potting resin is filled in this die cavity, be formed for enveloping the packing colloid of this semiconductor chip, make the pre-set dimension of the size of this packing colloid greater than semiconductor package part, then utilize cutting operation to remove in this packing colloid and the substrate size again, need not need to worry that the clamped areas (clamp area) of mould can weigh the circuit of substrate wounded greater than the part of this packaging part pre-set dimension.
In sum, the invention provides a kind of semiconductor package part and the method for making thereof that can avoid in Encapsulation Moulds compacting journey, weighing wounded base plate line, do not need to use special mould, just can effectively avoid weighing base plate line wounded in the Encapsulation Moulds compacting journey, can on chip, connect in the encapsulation procedure of the present invention and put heat sink, the heat that produces during by this heat sink loss semiconductor chip operation, formation can improve the semiconductor package part of chip cooling performance.
Description of drawings
Figure 1A to 1C figure is a conventional semiconductor packages part method for making schematic diagram;
Fig. 2 is a United States Patent (USP) 5,744, the generalized section that the ponding structure is set on substrate surface of No. 084 announcement;
Fig. 3 A and 3B figure are United States Patent (USP)s 6,452, the method for producing semiconductor packaging part generalized section of No. 268 announcements;
Fig. 4 A to Fig. 4 E is the schematic diagram of method for producing semiconductor packaging part embodiment 1 of the present invention;
Fig. 5 A to Fig. 5 D is the generalized section of method for producing semiconductor packaging part embodiment 2 of the present invention;
Fig. 6 is the generalized section of semiconductor package part embodiment 3 of the present invention; And
Fig. 7 is the generalized section of semiconductor package part embodiment 4 of the present invention.
Embodiment
Below by particular specific embodiment explanation embodiments of the present invention.Only show the assembly relevant in the following drawings with the present invention, and the assembly that shows not is the draftings such as number, shape and dimension scale when implementing according to reality, number, shape and dimension scale during actual enforcement is a kind of optionally design, and its assembly layout form may be more complicated.
Embodiment 1
See also Fig. 4 A to Fig. 4 E, it is the schematic diagram of method for producing semiconductor packaging part embodiment 1 of the present invention.This figure only illustrates basic structure of the present invention in a schematic way.
Shown in Fig. 4 A, substrate module sheet 41 at first is provided, this substrate module sheet 41 comprises a plurality of base board units 410, this base board unit 410 can array or the vertical bar mode arrange.Then on this base board unit 410 respectively, connect and put and electrically connect at least one semiconductor chip 40, and this semiconductor chip 40 is electrically connected to this base board unit except the flip chip shown in can icon, and it also can be electrically connected to this base board unit 410 by the routing mode.This base board unit for example is additional layers (Build-up) substrate.
Shown in Fig. 4 B and Fig. 4 C; this is connect the substrate module sheet 41 that is equipped with semiconductor chip 40 is interposed in the mould with patrix 42 and counterdie 43; this patrix 42 has die cavity 420; for potting resin wherein from injection molding mouth streamer; be formed for coating the packing colloid 44 of this semiconductor chip 40, protection semiconductor chip 40 can not be subjected to the influence of the moisture of external environment condition or pollution and damage.Wherein the die cavity 420 planar dimension M of this mould are greater than the planar dimension P (shown in dotted line) of the predetermined semiconductor package part of finishing, just this mould is used for the mould holder solidus MCL of the clamped areas (clamping area) of this substrate module sheet 41 of cramping, be positioned at the configuration outside of this base board unit 410, avoid mould to weigh the circuit of base board unit 410 wounded, in the follow-up die cavity 420 that potting resin is filled to this mould, be formed for coating the packing colloid 44 of this semiconductor chip 40.
Other sees also shown in Fig. 4 D, is being formed with the packing colloid floor map that is used to coat semiconductor chip on corresponding each base board unit 410 on the substrate module sheet 41, and the planar dimension M of this packing colloid is greater than the plane pre-set dimension P of semiconductor package part.
Shown in Fig. 4 E, carry out cutting operation, utilize for example cutter cutting tools such as (saw singulation), cut along predetermined package size P (dotted line shown in Fig. 4 D), remove in this packing colloid 44 and the base board unit 410 size greater than the part of this packaging part pre-set dimension, separate respectively this base board unit 410 simultaneously, need not to worry that the clamped areas (clamp area) of mould can weigh the circuit of substrate wounded.Can plant a plurality of soldered balls (not marking) in the corresponding respectively bottom surface of this base board unit in addition, the semiconductor package part of finishing for encapsulation is electrically connected to external device (ED).
Embodiment 2
Fig. 5 A to Fig. 5 D is the generalized section of method for producing semiconductor packaging part embodiment 2 of the present invention.The method for making of the embodiment of the invention 2 and embodiment 1 are roughly the same, main difference is, among the embodiment 2 semiconductor chip connect put and be electrically connected to base board unit after, on the semiconductor chip of corresponding each base board unit, connect and put heat sink, encapsulate mold pressing again and cut operations such as single, imitate attitude by the heat radiation that being provided with of this heat sink improved packaging part.
Shown in Fig. 5 A, the substrate module sheet 51 that includes a plurality of base board units 510 is provided, at least one semiconductor chip 50 is connect put and be electrically connected to respectively on this base board unit 510.Though showing this semiconductor chip among the figure is to be electrically connected to this base board unit with flip chip, non-as limit.
Shown in Fig. 5 B, on chip 50, connect and put heat sink 55 this base board unit 510 respectively.
Shown in Fig. 5 C, with respectively this connects the base board unit 510 that is equipped with semiconductor chip 50 and heat sink 55 and is contained in the mould that is formed with die cavity, be filled in this die cavity for potting resin, form the packing colloid 54 that coats this semiconductor chip 50 and heat sink 55, wherein the size M of this packing colloid 54 is greater than the pre-set dimension P of this semiconductor package part, and the size of this heat sink is greater than the packaging part pre-set dimension.
Shown in Fig. 5 D, cut single job, carry out cutting operation along the pre-set dimension P position of this semiconductor package part, remove in this packing colloid 54, base board unit 510 and the heat sink 55 size greater than the part of this packaging part pre-set dimension P.Can plant a plurality of soldered balls (not marking) at this base board unit back side in addition.
By above-mentioned method for making, the present invention also provides a kind of semiconductor package part, and this packaging part comprises: base board unit 510 has first surface and opposing second surface; At least one semiconductor chip 50 connects and puts and be electrically connected on these base board unit 510 first surfaces; Heat sink 55 connects and puts on this semiconductor chip 50; And packing colloid 54, be formed on the first surface of this base board unit 510, envelope this heat sink 55 and semiconductor chip 50, and this packing colloid 54 is cut mutually with the side of base board unit 510 flat.This semiconductor package part also can comprise a plurality of soldered balls that plant at this substrate second surface.The size of this heat sink is greater than the pre-set dimension of packaging part in addition, and the side of this heat sink of confession and the side of this packing colloid and substrate are cut flat mutually, expose outside this packing colloid; This semiconductor chip 50 is to be electrically connected to this substrate with flip-chip or routing mode.Whereby can be by connecing the heat that heat sink loss semiconductor chip when operation of putting on this semiconductor chip produces, and then improve the useful life and the usefulness of semiconductor package part.
Embodiment 3
Fig. 6 is the generalized section of semiconductor package part embodiment 3 of the present invention.The semiconductor package part of the embodiment of the invention 3 and embodiment 2 are roughly the same, main difference is, semiconductor chip 60 is through the routing operation among the embodiment 3, be electrically connected to this base board unit 610 by many bonding wires 66, and then this semiconductor chip 60 can be electrically connected to external device (ED) by a plurality of soldered balls 67 that plant in base board unit 610 bottom surfaces.
In addition, touch this bonding wire 66, can form protuberance 650 or a pad at interval, make this heat sink 65 can not contact this bonding wire 66 problem that is short-circuited in this heat sink bottom surface for avoiding connecing the heat sink of putting on this semiconductor chip 60 65.
Embodiment 4
Fig. 7 is the generalized section of semiconductor package part embodiment 4 of the present invention.The semiconductor package part of the embodiment of the invention 4 is roughly the same with embodiment 2, main difference is, connect heat sink 75 sizes of putting on semiconductor chip 70 among the embodiment 4 less than the packaging part pre-set dimension, when carrying out mold pressing and cutting single job, this heat sink 75 is coated in the packing colloid 74 fully follow-up.
Therefore, semiconductor package part of the present invention and method for making thereof mainly are in the molding operation of semiconductor packing process, the substrate that chip is then arranged is contained in the mould with die cavity, and make the pre-set dimension of the die cavity size of this mould greater than semiconductor package part, the part that just makes this mould be used for this substrate of cramping is the outside in this base plate line layout district, avoid mould to weigh the circuit of substrate wounded, for follow-up potting resin is filled in this die cavity, formation envelopes the packing colloid of this semiconductor chip, make the pre-set dimension of the size of this packing colloid greater than semiconductor package part, then utilize cutting operation again, remove that size need not to worry that greater than the part of this packaging part pre-set dimension the clamped areas of mould can weigh the circuit of substrate wounded in this packing colloid and the substrate.
In addition, the present invention can connect on chip in encapsulation procedure in addition and put heat sink, the heat that produces during by this heat sink loss semiconductor chip operation, and formation can improve the semiconductor package part of chip cooling performance.

Claims (10)

1. a method for producing semiconductor packaging part is characterized in that, this method for making comprises:
The substrate module that comprises a plurality of base board units sheet is provided, at least one semiconductor chip is connect put and be electrically connected on this base board unit;
With respectively this connects the base board unit that is equipped with semiconductor chip and is contained in the mould that is formed with die cavity, be filled in this die cavity for potting resin, corresponding each base board unit forms a plurality of individual packages colloids that envelope this semiconductor chip on this substrate module sheet, and wherein the size of this packing colloid is greater than the pre-set dimension of this semiconductor package part; And
Cutting operation is carried out in pre-set dimension position along this semiconductor package part, removes in this packing colloid and the base board unit size greater than the part of this semiconductor package part pre-set dimension.
2. method for producing semiconductor packaging part as claimed in claim 1 is characterized in that, this substrate module sheet is to arrange with array way arrangement or vertical bar mode.
3. method for producing semiconductor packaging part as claimed in claim 1 is characterized in that, this base board unit is the additional layers substrate.
4. method for producing semiconductor packaging part as claimed in claim 1 is characterized in that, this semiconductor chip is to be electrically connected to this base board unit with flip-chip or routing mode.
5. method for producing semiconductor packaging part as claimed in claim 1 is characterized in that, the die cavity size of this mould is greater than the predetermined semiconductor package part size of finishing.
6. method for producing semiconductor packaging part as claimed in claim 1 is characterized in that, the part that this mould is used for this base board unit of cramping is the outside in this base board unit configuration district.
7. a method for producing semiconductor packaging part is characterized in that, this method for making comprises:
The substrate module that comprises a plurality of base board units sheet is provided, at least one semiconductor chip is connect put and be electrically connected on this base board unit;
On the chip of this base board unit respectively, connect and put a heat sink;
Respectively this connects the base board unit that is equipped with semiconductor chip and heat sink and is contained in the mould that is formed with die cavity with correspondence, supply the potting resin filling in this die cavity, corresponding each base board unit forms a plurality of individual packages colloids that envelope this semiconductor chip and heat sink on this substrate module sheet, and wherein the size of this packing colloid is greater than the pre-set dimension of this semiconductor package part; And
Cutting operation is carried out in pre-set dimension position along this semiconductor package part, removes in this packing colloid and the base board unit size greater than the part of this semiconductor package part pre-set dimension.
8. method for producing semiconductor packaging part as claimed in claim 7 is characterized in that, the size of this heat sink is cut flat greater than the pre-set dimension of semiconductor package part for the side of this heat sink and the side of this packing colloid and substrate mutually.
9. method for producing semiconductor packaging part as claimed in claim 7 is characterized in that, the size of this heat sink is embedded in this packing colloid this heat sink integral body less than the pre-set dimension of semiconductor package part.
10. method for producing semiconductor packaging part as claimed in claim 7 is characterized in that, this heat sink is formed with the protuberance that protrudes to chip.
CNB2005100753331A 2005-06-10 2005-06-10 Semiconductor package and its making method Expired - Fee Related CN100466212C (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CNB2005100753331A CN100466212C (en) 2005-06-10 2005-06-10 Semiconductor package and its making method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNB2005100753331A CN100466212C (en) 2005-06-10 2005-06-10 Semiconductor package and its making method

Publications (2)

Publication Number Publication Date
CN1877802A CN1877802A (en) 2006-12-13
CN100466212C true CN100466212C (en) 2009-03-04

Family

ID=37510191

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2005100753331A Expired - Fee Related CN100466212C (en) 2005-06-10 2005-06-10 Semiconductor package and its making method

Country Status (1)

Country Link
CN (1) CN100466212C (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108152298B (en) * 2017-12-21 2020-11-03 京信通信系统（中国）有限公司 Method and device for detecting welding spot

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5744084A (en) * 1995-07-24 1998-04-28 Lsi Logic Corporation Method of improving molding of an overmolded package body on a substrate
EP0883171A1 (en) * 1997-06-03 1998-12-09 STMicroelectronics S.A. Semiconductor package manufacturing method having an integrated circuit
CN2519417Y (en) * 2002-01-25 2002-10-30 威盛电子股份有限公司 Multichip packaging structure with radiating member
US6552428B1 (en) * 1998-10-12 2003-04-22 Siliconware Precision Industries Co., Ltd. Semiconductor package having an exposed heat spreader
CN1171294C (en) * 2000-11-17 2004-10-13 矽品精密工业股份有限公司 Manufacturing method of thin spherical grid array integrated circuit package
US20050095875A1 (en) * 2001-06-04 2005-05-05 Chien-Ping Huang Fabrication method of semiconductor package with heat sink

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5744084A (en) * 1995-07-24 1998-04-28 Lsi Logic Corporation Method of improving molding of an overmolded package body on a substrate
EP0883171A1 (en) * 1997-06-03 1998-12-09 STMicroelectronics S.A. Semiconductor package manufacturing method having an integrated circuit
US6552428B1 (en) * 1998-10-12 2003-04-22 Siliconware Precision Industries Co., Ltd. Semiconductor package having an exposed heat spreader
CN1171294C (en) * 2000-11-17 2004-10-13 矽品精密工业股份有限公司 Manufacturing method of thin spherical grid array integrated circuit package
US20050095875A1 (en) * 2001-06-04 2005-05-05 Chien-Ping Huang Fabrication method of semiconductor package with heat sink
CN2519417Y (en) * 2002-01-25 2002-10-30 威盛电子股份有限公司 Multichip packaging structure with radiating member

Also Published As

Publication number Publication date
CN1877802A (en) 2006-12-13

Similar Documents

Publication Publication Date Title
CN102891123B (en) Stacked die semiconductor package body
US20030106212A1 (en) Method of attaching a heat sink to an IC package
US20070278701A1 (en) Semiconductor package and method for fabricating the same
CN102136434A (en) Method of stacking flip-chip on wire-bonded chip
CN105762084A (en) Packaging method and packaging device for flip chip
CN103594447B (en) IC chip stacked packaging piece that the big high frequency performance of packaging density is good and manufacture method
CN102054714B (en) Method for manufacturing packaging structure
CN108389850A (en) Three-dimensional system level packaging structure and its packaging method
CN100466212C (en) Semiconductor package and its making method
KR20150046117A (en) Device and method of manufacturing the same
CN101090077A (en) Semiconductor package and its manufacturing method
CN105914155A (en) Flip chip and package method thereof
CN112185903A (en) Electronic package and manufacturing method thereof
CN206116378U (en) Semiconductor encapsulation construction
CN102709199B (en) Mold array process method for covering side edge of substrate
CN101483168B (en) Molding mode SIM card encapsulation construction based on metal frame and encapsulation method thereof
KR20010025874A (en) Multi-chip semiconductor package
CN204216033U (en) Lead frame, semiconductor package body
CN208460760U (en) Three-dimensional system level packaging structure
KR100729502B1 (en) Carrier for multi chip package, multi chip package and method for fabricating the same
CN100446200C (en) Heat radiation type packaging structure and its making method
CN105590904A (en) Fingerprint identification multi-chip package structure and preparation method thereof
CN100362639C (en) Semiconductor packer and production for godown chip
CN100466210C (en) Radiating semiconductor packer and its production
CN218827107U (en) Package substrate

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20090304