CN206116378U - Semiconductor encapsulation construction - Google Patents
Semiconductor encapsulation construction Download PDFInfo
- Publication number
- CN206116378U CN206116378U CN201621146500.7U CN201621146500U CN206116378U CN 206116378 U CN206116378 U CN 206116378U CN 201621146500 U CN201621146500 U CN 201621146500U CN 206116378 U CN206116378 U CN 206116378U
- Authority
- CN
- China
- Prior art keywords
- bearing
- packaging structure
- semiconductor packaging
- connecting portion
- packing colloid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn - After Issue
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Abstract
The utility model discloses a semiconductor encapsulation construction. According to the utility model discloses a semiconductor encapsulation construction of embodiment includes: package substrate, it has first surface and second surface, and this first surface is relative with this second surface, and this second surface is provided with first weld pad, an electronic component, it sets up in this first surface, the 2nd electronic component, it sets up in this second surface, the lead frame, it includes first bearing and second bearing, wherein the second bearing has connecting portion, and connection material, these connecting portion of its cladding and this first weld pad of connection. This semiconductor encapsulation construction still includes an encapsulation colloid, this package substrate of its at least cladding, an electronic component, the 2nd electronic component. The utility model provides a semiconductor encapsulation construction can improve the dissipation of heat problem in the two -sided encapsulation module, still has with low costsly, prevents to encapsulate the module and takes place bent advantage of sticking up.
Description
Technical field
This utility model is related to field of semiconductor package, more particularly to semiconductor packaging structure.
Background technology
Semiconductor industry is devoted to manufacturing compact product, and various electronic building bricks need to be highly integrateable in limited face
In long-pending semiconductor packaging structure, stannum ball or stannum ball and the combinative structure of substrate is usually used as pin and mainboard
(Mainboard) it is electrically connected with.However, stannum ball is carrying out easily producing asking of coming off or subside during reflow (Reflow) is combined
Topic, lacks ball or highly inconsistent defect so as to cause semiconductor packaging structure to produce.Also, as stannum ball is with circular shape
Formula is arranged on mainboard, stannum ball and lower section mainboard because of the little problem that can cause poor heat radiation of contact area, especially for Gao Gong
The electronic building brick of rate.Further, since needing higher temperature during injection semiconductor packaging structure, therefore can not keep away
Cause substrate that warped occurs with exempting from.
Therefore, it is necessary to a kind of semiconductor packaging structure is provided, to solve the problems of prior art.
Utility model content
One of the purpose of this utility model is to provide semiconductor packaging structure, and which simply processing procedure and technique can be realized
The semiconductor packaging structure of low-cost and high-quality.
An embodiment of the present utility model provides semiconductor packaging structure, and which includes：Base plate for packaging, which has the first table
Face and second surface, the first surface are relative with the second surface, and the second surface is provided with the first weld pad；First electronics group
Part, which is arranged at the first surface；Second electronic building brick, which is arranged at the second surface；Lead frame, which includes the first bearing
With the second bearing, wherein the second bearing has connecting portion；Connecting material, which coats the connecting portion and connects first weld pad；With
And first packing colloid, which at least coats the base plate for packaging, first electronic building brick and second electronic building brick.
In another embodiment of the present utility model, first electronic building brick includes the first chip and the second packing colloid,
First chip bearing is in the first surface and is configured through connecting material and connecting portion to be electrically connected to lead frame, and this
Two packing colloids coat first chip.In another embodiment of the present utility model, second electronic building brick includes the second core
Piece, second chip bearing is in second surface and is configured through connecting material and connecting portion to be electrically connected to lead frame.
In another embodiment of the present utility model, the material of lead frame is the metal material in addition to stannum.It is of the present utility model again
In one embodiment, the semiconductor packaging structure also includes the 3rd packing colloid, and the 3rd packing colloid is injection molding and is filled in first
In the space of bearing and the second bearing.In another embodiment of the present utility model, the base plate for packaging includes hole.In this practicality
In new another embodiment, connecting portion has rough surface.In another embodiment of the present utility model, the semiconductor packages
Construction further includes screen layer, and which is configured at least cover the first packing colloid.In another embodiment of the present utility model
In, the connecting portion projects the surface of second bearing.
The heat that the semiconductor packaging structure that this utility model embodiment is provided can not only improve in double-faced packaging module disappears
Scattered problem, also with low cost, prevents package module from the advantage of warped occurring.
Description of the drawings
Fig. 1 is the longitudinal cross-section schematic diagram of the semiconductor packaging structure according to one embodiment of this utility model.
Fig. 2 a-2f are the schematic flow sheets that semiconductor packaging structure is manufactured according to one embodiment of this utility model, and which can be made
Make the semiconductor packaging structure shown in Fig. 1.
Specific embodiment
To be better understood from spirit of the present utility model, which is made below in conjunction with part preferred embodiment of the present utility model
Further illustrate.
Fig. 1 is the longitudinal cross-section schematic diagram of the semiconductor packaging structure 100 according to one embodiment of this utility model.
As shown in figure 1, being included according to the semiconductor packaging structure 100 of one embodiment of this utility model：Base plate for packaging 10,
One electronic building brick 12, the second electronic building brick 14, lead frame 16, connecting material 18 and the first packing colloid 20.
In the present embodiment, the base plate for packaging 10 has relative first surface 102 and second surface 104, second surface 104
It is provided with the first weld pad (not shown).
First electronic building brick 12 is arranged at the first surface 102 of the base plate for packaging 10.First electronic building brick 12 includes
First chip 122 and the second packing colloid 124.First chip 122 can pass through conventional chip and engage (Die Bond) technique
The first surface 102 of the base plate for packaging 10 is carried on, (Wire Bond) technique is engaged by routing and is connected to the first surface
102 and through connecting material 18 and connecting portion 166 being electrically connected to lead frame 16.Second packing colloid, 124 Jing is molded to wrap
Cover first chip 122 to play a part of to protect first chip 122.The material of the second packing colloid 124 can be resin
Deng other composite materials commonly used in the art.First electronic building brick 12 is alternatively other potted elements, by surface mount
(Surface Mount Technology, SMT) technology is arranged on the first surface 102 of the base plate for packaging 10.
Second electronic building brick 14 is arranged at the second surface 104 of the base plate for packaging 10.Second electronic building brick 14 includes
Second chip 142, second chip 142 can be carried on second table by way of conventional upside-down mounting die bond (Flip Chip)
Face 104 and it is configured through connecting material 18 and connecting portion 166 to be electrically connected to lead frame 16.Second chip 142 with should
Eutectic Layer (not shown) is formed between the second surface 104 of base plate for packaging 10.
The lead frame 16 includes the first bearing 162 and the second bearing 164.Second bearing 164 has connecting portion 166.
The connecting portion 166 is projected upwards from the surface of second bearing 164 and the connecting portion 166 has rough surface.First bearing
162 and second bearing 164 can be imprinted the upper surface of the lead frame 16 or this is etched using etch process by imprint process and draw
The upper surface of wire frame 16 and formed.The lead frame 16 also includes mould filling in first bearing 162 and second bearing
The 3rd packing colloid 168 in 164 space, and the lead frame 16 comprising the 3rd packing colloid 168 and the first packaging plastic
Body 20 has similar thermal coefficient of expansion (Coefficient of thermal expansion, CTE).The lead frame 16
Material is the metal material in addition to stannum, for example, steel, ferrum, aluminum, nickel and zinc etc..
The connecting material 18 coats the connecting portion 166, and connects the first weld pad (not shown) of second surface 104
With the connecting portion 166 of the second bearing 164.In the present embodiment, the connecting portion 166 projects the surface of second bearing 164.
If necessary, the connecting portion 166 can have coarse surface.On the second surface 104 of connecting material 18 and the base plate for packaging 10
The first weld pad between be formed with Eutectic Layer (not shown).
First packing colloid 20 at least coats the base plate for packaging 10, first electronic building brick 12 and second electronic building brick
14。
In the present embodiment, the base plate for packaging 10 also includes multiple holes 106, and the hole 106 runs through the base plate for packaging 10
First surface 102 and second surface 104.When the first packing colloid 20 is molded the base plate for packaging 10, first electronic building brick 12
And during second electronic building brick 14, the hole 106 can further mould mobile equilibrium (Mold-Flow Balance).Specifically, work as note
When moulding the first packing colloid 20, flow velocity can be flow to through hole 106 in first packing colloid 20 of the fast side of flow velocity slow
One side is so as to the mould mobile equilibrium of the semiconductor packaging structure 100 that furthers.The position of the hole 106 and the design of size can be according to tools
The design of the electronic building brick of body and be adjusted, do not describe in detail herein.
The semiconductor packaging structure 100 also includes screen layer 108, and the screen layer 108 is configured to cover first encapsulation
Colloid 20 and the 3rd packing colloid 168.The semiconductor packaging structure 100 also includes mount components or other adnexaes 109, for example
In the present embodiment, which can further include the passive element of the first surface 102 that the base plate for packaging 10 is arranged at by SMT technologies
109。
The first packing colloid 20, the second packing colloid 124, the 3rd packing colloid 168 in this utility model embodiment
Material can be selected according to the concrete condition of semiconductor packaging structure, and above-mentioned three kinds of materials can be with identical or different.In addition, can
With the concrete condition according to semiconductor packaging structure, the first packing colloid 20 with similar CTE, the second packing colloid are selected
124th, the material of the 3rd packing colloid 168.
In embodiment of the present utility model, base plate for packaging 10 is connected to the lead frame of lower section by connecting material 18
16, and then be electrically connected with external component.As shown in figure 1, the cladding connecting portion 166 of connecting material 18, and contact the second bearing
164 surface, therefore lock construction (interlock structure) in being formed, strengthen between connecting material 18 and connecting portion 166
Connection, that is, strengthen the connection between the base plate for packaging 10 and the lead frame 16.If necessary, (for example, can be lost by technique
Carving method) make the connecting portion 166 that there is coarse surface, and then increase the contact surface between connecting material 18 and connecting portion 166
Product, thus strengthens the connection between connecting material 18 and connecting portion 166.Therefore, such connected mode is compared to traditional stannum
Ball as compared with the mode that lower section mainboard connects, with more preferable bonding strength.Additionally, connecting material 18 and the second bearing
The guiding path of 164 compositions is coated by the first packing colloid 20 and the 3rd packing colloid 168.First packing colloid 20 and
Heat in semiconductor packaging structure 100 effectively outwards can be conducted by three packing colloids 168, so as to reduce semiconductor packages structure
Make 100 temperature.Furthermore, when the lead frame 16 comprising the 3rd packing colloid 168 is with injection semiconductor packaging structure 100
The similar thermal coefficient of expansion of the first packing colloid 20 for being used.Therefore, when the temperature of semiconductor packaging structure 100 is raised, example
First packing colloid 20 is molded such as or when semiconductor packaging structure 100 produces heat during use, due to lead frame
Frame 16 is with the thermal coefficient of expansion similar to the first packing colloid 20, therefore semiconductor packaging structure 100 is not susceptible to warped.
Additionally, this utility model is without the need for particular process sequence and the process of reprocessabilty, low cost of manufacture simple with manufacturing process, and hold
The advantage for easily engaging with the processing procedure for forming screen layer.
Additionally, this utility model embodiment additionally provides the method for manufacturing semiconductor packaging structure 100.
Fig. 2 a-2f are the schematic flow sheets that semiconductor packaging structure is manufactured according to another embodiment of the present utility model, its
The semiconductor packaging structure 100 shown in Fig. 1 can be manufactured.
As shown in Figure 2 a, there is provided base plate for packaging 10, the base plate for packaging 10 has relative first surface 102 and second surface
104, second surface 104 is provided with the first weld pad (not shown).The base plate for packaging 10 also includes multiple holes 106, the hole
First surface 102 and second surface 104 of the hole 106 through the base plate for packaging 10.
Then the first electronic building brick 12 is provided, first electronic building brick 12 includes the first chip 122 and the second packing colloid
124.The first surface 102 that the first chip 122 is arranged at conventional wafer bonding process the base plate for packaging 10 can be passed through, then
First chip 122 is connected to by the first surface 102 by routing joint technology.Then, being molded the second packing colloid 124 makes
Which coats first chip 122 to play a part of to protect first chip 122.So far complete to arrange the first electronic building brick 12
The step of first surface 102 of the base plate for packaging 10.In other embodiments, can be pre-formed comprising the second packing colloid
124 and first chip 122 the first electronic building brick 12, then first electronic building brick 12 is arranged at the of base plate for packaging 10 again
One surface 102.The material of the second packing colloid 124 can be other composite materials commonly used in the art such as resin.Attachment unit
Part or other adnexaes 109 can be connected to the first surface 102 of base plate for packaging 10 by SMT technologies.
As shown in Figure 2 b, the fluxes 110 on the first weld pad of the second surface 104 of the base plate for packaging 10, then
Stannum ball 112 is arranged on first weld pad.Second electronic building brick 14 is then arranged at the second surface of the base plate for packaging 10
104.Second electronic building brick 14 includes the second chip 142.Second chip 142 can be set by way of traditional upside-down mounting die bond
It is placed in the second surface 104 and is subsequently configured through connecting material 18 and connecting portion 166 to be electrically connected to lead frame 16, holds
After chat.
As shown in Figure 2 c, there is provided lead frame 16.The lead frame 16 includes the first bearing 162 and the second bearing 164.Should
Second bearing 164 has connecting portion 166.The connecting portion 166 is projected from the surface of second bearing 164.The lead frame 16 can
By imprint process imprint the lead frame 16 upper surface or using etch process etch the lead frame 16 upper surface and
Formed.The lead frame 16 also includes threeth envelope of the mould filling in the space of first bearing 162 and second bearing 164
Dress colloid 168, and the lead frame 16 comprising the 3rd packing colloid 168 has similar thermal expansion to the first packing colloid 20
Coefficient with prevent injection semiconductor packaging structure 100 during there is warped.The material of the lead frame 16 be except stannum it
Outer metal material, for example, the blaster fuse frame material such as steel, ferrum, aluminum, nickel and zinc.If necessary, technique (for example, etching side can be passed through
Method) make the connecting portion 166 that there is coarse surface.
Then, the fluxes 170 on the surface of connecting portion 166.
As shown in Figure 2 d, the base plate for packaging 10 and the lead frame 16 are pressed so that connecting portion 166 is docked with stannum ball 112,
And carry out reflow process.After reflow is processed, make the stannum ball 112 in Fig. 2 b form connecting material 18 and coat the connecting portion 166
And the first weld pad of the second surface 104 of the base plate for packaging 10 is connected to, wherein scaling powder 110 and 170 is waved in reflow process
Send out, Eutectic Layer is formed between the first weld pad on the second surface 104 of connecting material 18 and the base plate for packaging 10 and (is not shown in figure
Go out).
As shown in Figure 2 e, injection forms the first packing colloid 20, and first packing colloid 20 at least coats the base plate for packaging
10th, first electronic building brick 12 and second electronic building brick 14.When the first packing colloid 20 be molded the base plate for packaging 10, this first
When electronic building brick 12 and second electronic building brick 14, hole 106 can further mould mobile equilibrium (Mold-Flow Balance).Tool
Body ground, can flow to the slow side of flow velocity so as to further partly through hole 106 in first packing colloid 20 of the fast side of flow velocity
The mould mobile equilibrium of conductor packaging structure 100.The position of the hole 106 and the design of size can be according to specific electronic building bricks
Design and be adjusted, do not describe in detail herein.
Finally, as shown in figure 2f, the first packing colloid 20 of different semiconductor packaging structures 100 is cut with to different
Semiconductor packaging structure 100 is split.The formation screen that can subsequently adopt Coating technique or surface sputtering process etc. to commonly use
Cover layer process and screen layer 108 is formed to cover the first packing colloid 20, so as to obtain semiconductor packaging structure as shown in Figure 1
100。
The semiconductor packaging structure that this utility model is provided employs structure that lead frame combined with connecting material to change
It is apt to the shortcoming of existing stannum ball attachment structure, enhances the bonding strength of base plate for packaging and lead frame.Further, since first and
Three packing colloids coat connecting portion, and which also provides thermally conductive pathways for semiconductor packaging structure.Also, due to comprising the 3rd encapsulation
The first packing colloid that the lead frame of colloid is used to injection semiconductor packaging structure has similar thermal coefficient of expansion,
The problem of semiconductor packaging structure warped can effectively be improved.
Technology contents of the present utility model and technical characterstic have revealed that as above, but those of ordinary skill in the art still may be used
A variety of replacements and modification without departing substantially from this utility model spirit can be made based on teaching of the present utility model and announcement.Therefore, originally
The protection domain of utility model should be not limited to the content disclosed in embodiment, and should replace without departing substantially from of the present utility model including various
Change and modify, and covered by present patent application claims.
Claims (9)
1. a kind of semiconductor packaging structure, it is characterised in that include：
Base plate for packaging, which has first surface and second surface, and the first surface is relative with the second surface, and described second
Surface is provided with the first weld pad；
First electronic building brick, which is arranged at the first surface；
Second electronic building brick, which is arranged at the second surface；
Lead frame, which includes：
First bearing and the second bearing, wherein second bearing has connecting portion；
Connecting material, its described connecting portion of cladding and connection first weld pad；And
First packing colloid, which at least coats the base plate for packaging, first electronic building brick and second electronic building brick.
2. semiconductor packaging structure according to claim 1, it is characterised in that wherein described first electronic building brick includes
One chip and the second packing colloid, first chip bearing in the first surface and be configured through the connecting material and
To be electrically connected to the lead frame, second packing colloid coats first chip to the connecting portion.
3. semiconductor packaging structure according to claim 1, it is characterised in that wherein described second electronic building brick includes
Two chips, second chip bearing is in the second surface and is configured through the connecting material and the connecting portion with electricity
It is connected to the lead frame.
4. semiconductor packaging structure according to claim 1, it is characterised in that the material of wherein described lead frame be except
Metal material outside stannum.
5. semiconductor packaging structure according to claim 1, it is characterised in that wherein described semiconductor packaging structure is also wrapped
The 3rd packing colloid is included, the 3rd packing colloid is injection molding the space for being filled in first bearing and second bearing
In.
6. semiconductor packaging structure according to claim 1, it is characterised in that wherein described base plate for packaging includes hole.
7. semiconductor packaging structure according to claim 1, it is characterised in that wherein described connecting portion has rough surface.
8. semiconductor packaging structure according to claim 1, it is characterised in that further include screen layer, which is configured to
First packing colloid is covered at least.
9. semiconductor packaging structure according to claim 1, it is characterised in that wherein described connecting portion projects described second
The surface of bearing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621146500.7U CN206116378U (en) | 2016-10-21 | 2016-10-21 | Semiconductor encapsulation construction |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621146500.7U CN206116378U (en) | 2016-10-21 | 2016-10-21 | Semiconductor encapsulation construction |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206116378U true CN206116378U (en) | 2017-04-19 |
Family
ID=58528028
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201621146500.7U Withdrawn - After Issue CN206116378U (en) | 2016-10-21 | 2016-10-21 | Semiconductor encapsulation construction |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206116378U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106328611A (en) * | 2016-10-21 | 2017-01-11 | 苏州日月新半导体有限公司 | Semiconductor encapsulation structure and manufacturing method |
| CN107731715A (en) * | 2017-10-12 | 2018-02-23 | 苏州日月新半导体有限公司 | The stacking method and its warpage preventing tool of encapsulating compound band |
-
2016
- 2016-10-21 CN CN201621146500.7U patent/CN206116378U/en not_active Withdrawn - After Issue
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106328611A (en) * | 2016-10-21 | 2017-01-11 | 苏州日月新半导体有限公司 | Semiconductor encapsulation structure and manufacturing method |
| CN106328611B (en) * | 2016-10-21 | 2019-03-12 | 苏州日月新半导体有限公司 | Semiconductor packaging structure and its manufacturing method |
| CN107731715A (en) * | 2017-10-12 | 2018-02-23 | 苏州日月新半导体有限公司 | The stacking method and its warpage preventing tool of encapsulating compound band |
| CN107731715B (en) * | 2017-10-12 | 2024-01-30 | 日月新半导体(苏州)有限公司 | Method for stacking packaging material belts and warping prevention jig thereof |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20170419 Effective date of abandoning: 20190312 |