CN100463153C - 具有电路焊盘的器件及其制造方法 - Google Patents

具有电路焊盘的器件及其制造方法 Download PDF

Info

Publication number
CN100463153C
CN100463153C CNB2006100003202A CN200610000320A CN100463153C CN 100463153 C CN100463153 C CN 100463153C CN B2006100003202 A CNB2006100003202 A CN B2006100003202A CN 200610000320 A CN200610000320 A CN 200610000320A CN 100463153 C CN100463153 C CN 100463153C
Authority
CN
China
Prior art keywords
circuit pad
pad
chip
substrate
transmission line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB2006100003202A
Other languages
English (en)
Other versions
CN1819167A (zh
Inventor
B·A·弗洛伊德
U·R·法伊弗
S·K·雷诺兹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CN1819167A publication Critical patent/CN1819167A/zh
Application granted granted Critical
Publication of CN100463153C publication Critical patent/CN100463153C/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5225—Shielding layers formed together with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P5/00—Coupling devices of the waveguide type
    • H01P5/02—Coupling devices of the waveguide type with invariable factor of coupling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0605—Shape
    • H01L2224/06051—Bonding areas having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1905—Shape
    • H01L2924/19051—Impedance matching structure [e.g. balun]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/07—Electric details
    • H05K2201/0707—Shielding
    • H05K2201/0723—Shielding provided by an inner layer of PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/07—Electric details
    • H05K2201/0776—Resistance and impedance
    • H05K2201/0792—Means against parasitic impedance; Means against eddy currents
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Microwave Amplifiers (AREA)

Abstract

本发明提供了屏蔽的电路焊盘，其中通过包括分路传输线分支消除了寄生电容，分路传输线分支减小了毫米波应用中的衬底感应损耗。电路焊盘位于衬底上，屏蔽件位于电路焊盘下，以及分路传输线分支连接到电路焊盘。由此，获得用于毫米波应用的受控阻抗。然后最小化了电路焊盘和屏蔽件之间的间隔。

Description

具有电路焊盘的器件及其制造方法
技术领域
本发明总体上涉及用于毫米波频率范围内的电路工作的芯片上电路焊盘，以及具体涉及为了改进衬底感应损耗在有损耗衬底上使用的芯片上电路焊盘。
背景技术
毫米波频率范围内工作的电子产品可以基于砷化镓(GaAs)或磷化铟(InP)半导体技术，以提供诸如个人区域网络和汽车雷达的应用所需的速度和功率。但是，为了降低成本和功率损耗，要求显著地减小基于这些砷化镓(GaAs)或磷化铟(InP)的半导体产品的系统尺寸。
已经表明硅锗(SiGe)工艺技术被很好地定位于提供毫米波频率范围内的速度和功率解决办法，例如用于高度集成的无线电电路。但是，标准的硅衬底通常具有较低的电阻率，因此在毫米波频率下，该衬底可能极大地影响芯片上互连的信号损失。因此，在毫米波频率下，根据输入/输出连接的物理尺寸，有损耗衬底可能极大地影响输入/输出连接(IO)的信号损失。
输入/输出连接如芯片上电路焊盘被设计用于较低的频率操作。图1A-B分别示出了在衬底上设置的芯片上电路焊盘的示例性实施例的前视图和侧视图。如图1A-B所示，芯片上电路焊盘可以由具有八边形形状的顶部金属板110构成。应该意识到该焊盘是足够大的，如100×100μm，以提供用于引线接合或倒装芯片球封装的空间结构。
如图1A-B所示，电路焊盘110被设置在衬底100上，其中在电路焊盘110下面设置固体金属屏蔽件112，以减小由衬底100引起的损耗。在图1A-B所示的实施例中，在衬底100上提供电路焊盘110和金属屏蔽件112之间的间隔h1，以及该间隔被最大化，以使电路焊盘110和金属屏蔽件112之间形成的寄生电容最小。亦即，当间隔h1增加时，寄生电容减小。
如图1A-B所示，设置馈电线114，以将焊盘结构连接到芯片上电路，如输入缓冲器或输出驱动器。在一般的通信系统中，该结构可以是低噪声放大器或功率放大器。
发明内容
在毫米波频率范围内工作，如在图1A-B的示例性实施例中在芯片上电路焊盘正下方直接设置固体金属屏蔽件通常是不希望的，因为该结构的大寄生电容。
由此，根据本发明的各个示例性实施例，提供改进的屏蔽电路焊盘，其中通过包括分路(shunt)传输线分支(stub)消除了寄生电容。可以包括线分支，以有效地避免焊盘电容，以及组合结构仅仅表示芯片外电源和芯片上电路之间的高阻抗节点。这样，屏蔽件不以任何方式影响电路性能，并可以使用而不用进一步考虑减小在毫米波应用中的衬底感应损耗。
根据本发明的各个示例性实施例，提供一种器件，包括衬底，位于衬底上的电路焊盘，位于电路焊盘下的屏蔽件，以及连接到电路焊盘的分路传输线分支。
根据本发明的各个示例性实施例，提供一种消除寄生电容的方法。
根据这些示例性实施例，该方法包括以下步骤：确定焊盘电容，确定将要连接到电路焊盘的所需线分支长度，输入外部电源或负载阻抗，以及提供外部电源或负载阻抗作为芯片上馈电线的阻抗。
根据本发明的各个示例性实施例，获得用于毫米波应用的受控阻抗。亦即，由于调谐电路焊盘表示高阻抗节点，在工作的频带中电路焊盘可以被认为是电透明的。因此芯片外负载或电源阻抗不以任何方式改变以及在至馈电线的输入处将被看到。亦即，如果以这样的方式选择芯片上馈电线，以使芯片上馈电线具有与芯片外电源或负载阻抗相同的特性线阻抗，那么芯片外电源或负载阻抗在它被连接到芯片上电路的馈电线的另一端也可以看到。该阻抗将与馈电线的长度无关。因此馈电线的长度无关紧要和在任意阻抗匹配网络中不必考虑。
因此，根据本发明的各个示例性实施例，馈电线的长度可以具有将芯片上电路连接到电路焊盘所需的任意长度。
根据本发明的各个示例性实施例，可以最小化电路焊盘和屏蔽件之间的间距，而对芯片上电路没有任何损害。
通过结合附图阅读的示例性实施例的以下详细描述，将描述或显而易见本发明的这些及其他示例性实施例、方面、目的、特点和优点。
附图说明
图1A-B分别示出了在衬底上设置的芯片上电路焊盘的示例性公知实施例的前视图和侧视图。
图2A-B分别示出了根据本发明在衬底上设置的具有分路传输线分支的芯片上电路焊盘的示例性实施例的前视图和侧视图。
图3示出了为差分焊盘结构结合两个电路焊盘的本发明的一个示例性实施例。
图4示出了使用引线接合技术在示例性半导体集成电路封装中集成的根据本发明的一个示例性实施例的示例性衬底。
图5示出了使用倒装芯片接合技术在又一示例性半导体集成电路封装中集成的根据本发明的一个示例性实施例的示例性衬底。
图6说明根据本发明的示例性实施例消除寄生电容的示例性方法的流程图。
具体实施方式
图2A-B分别示出了根据本发明的示例性实施例，在衬底上设置的示例性芯片上电路焊盘和与其连接的传输线分支的前视图和侧视图。更具体地说，图2A和2B说明设置在有损耗衬底200上的示例性芯片上电路焊盘210和传输线分支220，其中图2A示意地说明衬底200的顶平面图，图2B是沿线I-I′图2A的衬底200的示意性剖面图。
现在参考图2A和2B，基于图1A-B的示例性框架，在衬底200上设置电路焊盘210。应该意识到衬底200可以包括任意适合的材料，包括例如介质/绝缘材料，如熔融的硅石(SiO2)、氧化铝、聚苯乙烯、陶瓷、聚四氟乙烯基衬底、FR4等，或半导体材料，如低或高电阻率的硅或砷化镓(GaAs)、磷化铟(InP)等。
应该意识到根据本发明的各个示例性实施例，有损耗衬底可以被用作衬底200，由于无损耗衬底将不需要屏蔽件。因此，该示例性实施例能够使用廉价的有损耗衬底。
还应该意识到，根据本发明的各个示例性实施例，电路焊盘210可以是非常宽的频带，不在极低的频率，如DC至100GHz，但是在足够宽以覆盖一般通信系统的工作频带的频带范围内。例如，在各个实施例中，带宽可以覆盖50至70GHz。
如图2A-B所示，电路焊盘210设有与其连接的传输线分支220。在图2A-B所示的示例性实施例中，在电路焊盘210和传输线分支220下设置金属屏蔽件212。金属屏蔽件212被设置在电路焊盘210和传输线分支220下，间隔h2，以减小由有损耗衬底200引起的电路焊盘210的损耗。电路焊盘210和传输线分支220连同金属屏蔽件212一起可以形成为衬底200的顶金属层的一部分。
由于传输线分支220的增加，代替图1A-B中的作为屏蔽件120的正方形形状的屏蔽件，使用图2A-B的屏蔽件212，其包括传输线分支220下的突出部分。但是，应该意识到根据本发明的各个示例性实施例，屏蔽件212不局限于图2A-B所示的示例性形状，可以使用提供屏蔽功能以屏蔽电路焊盘210和传输线分支220的任意形状。
如图2A所示，设置馈电线214，以提供到电路焊盘210的芯片上馈电。馈电线214被设置为将焊盘结构连接到作为输入缓冲器或输出驱动器的芯片上电路。在一般的通信系统中，该焊盘结构可以是低噪声放大器或功率放大器。在毫米波频率下，馈电线214可以由具有特性阻抗(Z0)的传输线制成，以使信号分散或不需要的反射最小。可以选择馈电线214的尺寸，如长度和宽度，以与焊盘电容结合，获得外部芯片外电源与集成的芯片上电路的最佳阻抗匹配。应该意识到对于特定的电路，为了获得阻抗匹配，可能需要附加的匹配元件，如电容器、电感器或传输线。
根据本发明的各个示例性实施例，传输线分支220被分路，以消除不需要的寄生电容，从而减小由有损耗衬底引起的损耗。由此，寄生电容可以被消除，与电路焊盘210和屏蔽件212之间的间隔h2无关。因此，间隔h2可以被最小化，以在半导体后段制程的金属叠层内实现有效的屏蔽。例如，可以选择更靠近电路焊盘210的较厚的金属层，如铜层，以提供较低的电阻性接地屏蔽。
如图2B所示，在端部传输线分支220可以通过电容器230或直过孔，被短路至接地屏蔽件212。应该意识到在输入和输出信号被AC耦合的应用中可以使用简单的过孔，以及在DC耦合输入/输出信号的情况下，为了防止短路，分路电容器是希望的。
如所述，通过使传输线分支220短路，在毫米波频率下，不需要的寄生电容被减小至零或被消除。在这种毫米波频率下，分路传输线分支220的长度可以被选择为在具有足够带宽的工作的中心频率下该结构具有真正的阻抗。该调谐(tuning)使电路焊盘210在中心频率下电透明。该频率进一步远离其中心频率，电路焊盘210将更不透明。但是，由于焊盘和分支电容具有极低的品质因子，因此该组合结构可以具有非常宽的带宽。因此具有相似特性阻抗的芯片上传输线可以被连接到电路焊盘210，以将输入/输出信号传送到芯片上任意位置，而不需要重新匹配该阻抗。
根据本发明的各个示例性实施例，获得用于毫米波应用的受控阻抗。亦即，由于调谐电路焊盘210表示高阻抗节点，在工作的频带中电路焊盘210可以被认为是电透明的。因此芯片外负载或电源阻抗不以任何方式改变以及在至馈电线214的输入处将被看到。
在各种应用中，外部芯片外电源或负载阻抗可以被选为50Ω。如果以这样的方式选择芯片上馈电线214，以使芯片上馈电线214具有与芯片外电源或负载阻抗相同的50Ω特性线路阻抗，那么芯片外电源或负载阻抗在它被连接到芯片上电路的馈电线214的另一端处也可以看见。该阻抗将与馈电线214的长度无关，如果传输线的输入是如在现有技术焊盘中的电容性的，通常不是该情况。因此馈电线214的长度无关紧要和不必考虑任意阻抗匹配网络。在实际芯片布图中，由于馈电线214的长度可以具有将芯片上电路连接到电路焊盘210需要的任意长度，因此该设计是非常方便的。
应该意识到，根据本发明的各个示例性实施例，选择传输线分支220的长度，以使焊盘电容谐振(resonated)。亦即，不同的电路焊盘210需要较长的或较短的分支220。
图3示出了两个电路焊盘被结合以形成差分焊盘结构的本发明的示例性实施例。在图3所示的示例性实施例中，差分电路设有接地-信号-接地结构，广泛的用于毫米波应用。但是，应该意识到本发明的实施例不局限于该接地-信号-接地结构，根据本发明可以应用其他结构。
如图3所示，在衬底300上设置电路焊盘310和350，具有分别与其连接的分路分支320和360。传输线可以通过分别在其处设置的电容器330和370在端部短路。在图3所示的示例性实施例中，分支320和360被弯曲，以减小空间使用。但是，应该意识到本发明的示例性实施例不局限于任意特定的结构。
在电路焊盘310和350以及分支320和360下分别设置金属屏蔽件312和352。如图3所示，屏蔽312和352的形状由电路焊盘310和350以及分支320和360的形状决定。
在图3所示的示例性实施例中，在接地-信号-接地结构中设置电路焊盘310和350，其中在接地焊盘342，344和346之间另外地设置电路焊盘310和350。
为了说明，将特别参考半导体集成电路封装中的衬底和这种衬底的集成描述本发明的示例性实施例。但是，应当理解，本发明更广泛地用于适合于给定应用和/或工作频率的衬底的任意集成。
更具体地说，图4说明在半导体集成电路封装中集成的根据本发明的示例性实施例的示例性衬底的集成。如图4所示，衬底400是通过引线接合集成在电路封装中的芯片。通常，在半导体制造中通常使用接合，用于使芯片与衬底互连，以提供用于功率和信号分配的电子路径。如图4所示，提供引线接合，以将衬底400上的电路焊盘410和450以及接地焊盘442，444和446连接到引线框4000。
在图4所示的示例性实施例中，接地焊盘442，444和446分别通过引线元件481，483和485连接到接地的引线框4000，以提供接地连接。电路焊盘410和450分别通过引线元件482和486连接到连接焊盘4800和4810，以分别提供正和负电子路径。
在图4所示的示例性实施例中，引线元件481-486在一端连接到衬底400的表面和在另一端连接到引线框4000的表面。应当理解本发明不局限于图4所示的引线接合结构，可以使用其他结构，如倒装芯片球接合。
例如，图5说明在半导体集成电路封装中的根据本发明的示例性实施例的衬底的又一种集成。
更具体地说，图5说明通过倒装芯片球接合在电路封装中集成的作为芯片的衬底500，以提供用于功率和信号分配的电子路径。如图5所示，提供倒装芯片球接合，以将衬底500上的电路焊盘510和550以及接地焊盘542，544和546连接到引线框5000(图中未示出)。
在图5所示的示例性实施例中，接地焊盘542，544和546分别通过接地球581，583和585连接到接地引线框5000，以提供接地连接。电路焊盘510和550分别连接到正和负信号球582和586，以分别提供正和负电子路径。
应当意识到根据本发明的示例性实施例的衬底可以被封装作为在相对较小的封装中集成的集成电路芯片，以构成射频(RF)或无线通信芯片。例如，图4和5可以是集成地封装天线和集成电路芯片、芯片到另一芯片或仅仅一个芯片到其封装的示意性透视图。在此情况下，电路焊盘能够将天线如偶极天线连接到集成天线馈电网络如连接到集成电路芯片的集成电路的差分馈电。馈电网络框架根据例如给定应用希望的阻抗和/或将与芯片连接的器件的类型而改变。
应当理解，图4-5的示例性实施例仅仅是说明封装衬底的实施例，基于在此的教导，所属领域的普通技术人员可以容易地想到其他框架。
图6说明根据本发明的示例性实施例消除寄生电容的示例性方法的流程图。从步骤600开始，控制进行至步骤610，其中电路焊盘被输入到用于消除寄生电容的调谐系统。接下来，在步骤620中，确定焊盘电容。应该意识到焊盘电容可以通过电磁模拟或测量来确定。然后控制进行至步骤630。
在步骤630中，确定被连接到电路焊盘所需的分支长度。应该意识到，根据本发明的各个示例性实施例，可以使用分析计算或模拟器中的电传输线模型来发现所需的分支长度。应该意识到，根据本发明的各个示例性实施例，选择传输线分支的长度，以使焊盘电容谐振。
接下来，在步骤640中，输入外部电源或负载阻抗。如上所述，在各个应用中，外部芯片外电源或负载阻抗可以被选为50Ω。然后，在步骤650中，提供外部电源或负载阻抗作为用于芯片上馈电线的阻抗。因此，如果以这样的方式选择芯片上馈电线，以使芯片上馈电线具有与芯片外电源或负载阻抗相同的50Ω特性线阻抗，那么芯片外电源或负载阻抗在它被连接到芯片上电路的馈电线的另一端处可以看到。该阻抗将与馈电线的长度无关，因此馈电线的长度无关紧要以及在任意阻抗匹配网络中不必考虑。
然后控制进行至步骤660，工序结束。
应该理解根据本发明的封装中的衬底和衬底的集成能够用于大量的应用，如集相控阵列系统、个人区域网络、雷达馈电、由于冗余的高可靠性、点对点系统等。而且，根据本发明的集成电路芯片封装的使用节省大量空间、尺寸、成本和重量，这些是任意民用或军用的实际额外支出。
尽管在此参考用于说明的附图描述了示例性实施例，但是应当理解本发明不局限于那些精确的实施例，在不脱离本发明的范围的情况下，所属领域的技术人员在此可以实现多种其他改变和改进。

Claims (17)

1.一种器件，包括：
衬底；
所述衬底上的电路焊盘；
所述电路焊盘下的屏蔽件；以及
连接到所述电路焊盘的分路传输线分支，所述分路传输线分支具有使所述电路焊盘的电容谐振的长度。
2.根据权利要求1的器件，其中所述衬底包括有损耗衬底。
3.根据权利要求1的器件，其中所述器件在毫米波应用中提供。
4.根据权利要求1的器件，其中所述分路传输线分支被短路到所述屏蔽件以消除寄生电容。
5.根据权利要求4的器件，其中所述分路传输线分支通过电容器或直过孔之一被短路到所述屏蔽件。
6.根据权利要求1的器件，还包括在所述电路焊盘和所述屏蔽件之间的间隔，其中所述间隔被最小化。
7.根据权利要求1的器件，还包括受控阻抗。
8.根据权利要求7的器件，还包括至所述电路焊盘的馈电线，其中所述馈电线包括与芯片外负载阻抗相同的特性线阻抗。
9.根据权利要求1的器件，还包括第二衬底，所述第二衬底上的第二电路焊盘，所述第二电路焊盘下的第二屏蔽件，以及连接到所述第二电路焊盘的第二分路传输线分支，其中所述器件包括差分焊盘结构。
10.一种集成电路封装，包括：
集成芯片；
所述集成芯片上的接地焊盘；
所述集成芯片上的电路焊盘；
所述电路焊盘下的屏蔽件；
连接到所述电路焊盘的分路传输线分支，所述分路传输线分支具有使所述电路焊盘的电容谐振的长度；以及
连接到所述集成芯片上的所述电路焊盘和所述接地焊盘的引线框。
11.根据权利要求10的集成电路封装，其中所述引线框通过引线接合和倒装芯片球接合之一连接到所述电路焊盘和所述接地焊盘。
12.一种用于制造具有电路焊盘的器件的方法，包括以下步骤：
提供电路焊盘；
确定所述电路焊盘的电容；
确定将要连接到所述电路焊盘的传输线分支的长度，以使所述电路焊盘的所述确定的电容谐振；以及
确定至所述电路焊盘的馈电线的阻抗，其中芯片上的馈电线具有与芯片外负载阻抗相同的特性线阻抗。
13.根据权利要求12的用于制造具有电路焊盘的器件的方法，其中所述芯片外负载阻抗在连接到芯片上电路的馈电线的端部可以看到。
14.根据权利要求12的用于制造具有电路焊盘的器件的方法，其中所述传输线分支被短路到所述屏蔽件以消除寄生电容。
15.根据权利要求12的用于制造具有电路焊盘的器件的方法，其中所述馈电线的阻抗与所述馈电线的长度无关。
16.根据权利要求12的用于制造具有电路焊盘的器件的方法，其中所述方法在毫米波应用中采用。
17.根据权利要求12的用于制造具有电路焊盘的器件的方法，还包括在所述电路焊盘下提供屏蔽件，以及最小化所述电路焊盘和所述屏蔽件之间的间隔。
CNB2006100003202A 2005-01-05 2006-01-04 具有电路焊盘的器件及其制造方法 Expired - Fee Related CN100463153C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/029,518 2005-01-05
US11/029,518 US7566952B2 (en) 2005-01-05 2005-01-05 On-chip circuit pad structure

Publications (2)

Publication Number Publication Date
CN1819167A CN1819167A (zh) 2006-08-16
CN100463153C true CN100463153C (zh) 2009-02-18

Family

ID=36639463

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2006100003202A Expired - Fee Related CN100463153C (zh) 2005-01-05 2006-01-04 具有电路焊盘的器件及其制造方法

Country Status (4)

Country Link
US (1) US7566952B2 (zh)
JP (1) JP5132054B2 (zh)
CN (1) CN100463153C (zh)
TW (1) TW200633097A (zh)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7843033B2 (en) 2008-02-08 2010-11-30 Freescale Semiconductor, Inc. Shielded integrated circuit pad structure
KR20160063402A (ko) * 2008-09-12 2016-06-03 가부시키가이샤 한도오따이 에네루기 켄큐쇼 디스플레이 장치
KR100935854B1 (ko) 2009-09-22 2010-01-08 테세라 리써치 엘엘씨 와이어 본딩 및 기준 와이어 본딩에 의해 제어되는 임피던스를 가진 마이크로전자 어셈블리
KR100950511B1 (ko) 2009-09-22 2010-03-30 테세라 리써치 엘엘씨 와이어 본딩 및 도전성 기준 소자에 의해 제어되는 임피던스를 포함하는 마이크로전자 어셈블리
CN101932191B (zh) * 2009-06-25 2012-09-05 北京普源精电科技有限公司 一种测量设备及其放大电路、阻抗部件和多层印刷电路板
CN101932189B (zh) * 2009-06-25 2012-09-05 北京普源精电科技有限公司 一种测量设备及其放大电路、阻抗部件和多层印刷电路板
CN101932190B (zh) * 2009-06-25 2012-09-05 北京普源精电科技有限公司 一种测量设备及其放大电路、阻抗部件和多层印刷电路板
WO2011078857A1 (en) * 2009-12-22 2011-06-30 Cornell University Electrical prism: a high quality factor filter for millimeter-wave and terahertz frequencies
US8786083B2 (en) 2010-09-16 2014-07-22 Tessera, Inc. Impedance controlled packages with metal sheet or 2-layer RDL
US8853708B2 (en) 2010-09-16 2014-10-07 Tessera, Inc. Stacked multi-die packages with impedance control
US8581377B2 (en) * 2010-09-16 2013-11-12 Tessera, Inc. TSOP with impedance control
US9136197B2 (en) 2010-09-16 2015-09-15 Tessera, Inc. Impedence controlled packages with metal sheet or 2-layer RDL
JP2014063991A (ja) 2012-08-31 2014-04-10 Toshiba Corp 半導体装置、高周波伝送装置および半導体製造方法
KR20150135255A (ko) 2013-03-25 2015-12-02 르네사스 일렉트로닉스 가부시키가이샤 반도체 장치 및 그 제조 방법
JP2017121032A (ja) * 2015-06-30 2017-07-06 住友電気工業株式会社 高周波装置
US9711471B2 (en) 2015-11-18 2017-07-18 Nxp Usa, Inc. Semiconductor device package, electronic device and method of manufacturing electronic devices using wafer level chip scale package technology
US9992860B2 (en) 2016-04-26 2018-06-05 Hewlett Packard Enterprise Development Lp Printed circuit board capacitor structures
JP2017034265A (ja) * 2016-09-15 2017-02-09 ルネサスエレクトロニクス株式会社 半導体装置
CN108447852A (zh) * 2018-04-19 2018-08-24 加特兰微电子科技(上海)有限公司 一种毫米波芯片封装结构及印刷电路板
EP3796013B1 (en) * 2019-09-18 2023-08-02 Infineon Technologies AG Interface adapted to receive a radio frequency probe for testing an electric device, and method for testing an electric device arranged on a substrate

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1097082A (zh) * 1993-04-28 1995-01-04 株式会社村田制作所 多层型高频平行带状线电缆
CN1250227A (zh) * 1998-09-18 2000-04-12 株式会社日立制作所 半导体装置
JP2000200905A (ja) * 1999-01-06 2000-07-18 Nissan Motor Co Ltd 半導体装置
CN1449030A (zh) * 2002-04-03 2003-10-15 松下电器产业株式会社 内装半导体的毫米波段模块
US6712284B2 (en) * 2001-03-30 2004-03-30 Fujitsu Quantum Devices Limited High frequency semiconductor device

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5025232A (en) * 1989-10-31 1991-06-18 Texas Instruments Incorporated Monolithic multilayer planar transmission line
JPH04326206A (ja) * 1991-04-25 1992-11-16 Fujitsu Ltd 電力増幅器
JP2798051B2 (ja) * 1996-03-29 1998-09-17 日本電気株式会社 電界効果トランジスタ
JPH10145112A (ja) * 1996-11-14 1998-05-29 Toshiba Corp 配線基板
JPH10224106A (ja) * 1997-02-05 1998-08-21 Oki Electric Ind Co Ltd 高周波回路及びその特性の調整方法
JP2000049554A (ja) * 1998-07-30 2000-02-18 Kyocera Corp ローパスフィルタおよび回路基板
JP2000077914A (ja) * 1998-09-02 2000-03-14 Murata Mfg Co Ltd 伝送線路変換器およびその変換特性調整方法
JP2001284992A (ja) * 2000-03-28 2001-10-12 Toshiba Corp 高周波増幅器及び高周波半導体装置
TW529109B (en) * 2001-09-11 2003-04-21 Apack Comm Inc Flip chip type monolithic microwave integrated circuit package
US20040012457A9 (en) * 2001-12-18 2004-01-22 Soltan Mehdi Frederik Internal impedance match in integrated circuits
US7190244B2 (en) * 2004-11-18 2007-03-13 Her Majesty The Queen In Right Of Canada As Represented By The Minister Of Industry, Through The Communications Research Centre Canada Reduced size transmission line using capacitive loading

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1097082A (zh) * 1993-04-28 1995-01-04 株式会社村田制作所 多层型高频平行带状线电缆
CN1250227A (zh) * 1998-09-18 2000-04-12 株式会社日立制作所 半导体装置
JP2000200905A (ja) * 1999-01-06 2000-07-18 Nissan Motor Co Ltd 半導体装置
US6712284B2 (en) * 2001-03-30 2004-03-30 Fujitsu Quantum Devices Limited High frequency semiconductor device
CN1449030A (zh) * 2002-04-03 2003-10-15 松下电器产业株式会社 内装半导体的毫米波段模块

Also Published As

Publication number Publication date
JP5132054B2 (ja) 2013-01-30
CN1819167A (zh) 2006-08-16
TW200633097A (en) 2006-09-16
US20060145308A1 (en) 2006-07-06
US7566952B2 (en) 2009-07-28
JP2006191027A (ja) 2006-07-20

Similar Documents

Publication Publication Date Title
CN100463153C (zh) 具有电路焊盘的器件及其制造方法
US7342299B2 (en) Apparatus and methods for packaging antennas with integrated circuit chips for millimeter wave applications
CN102113116B (zh) 高品质因数变压器集成电路、封装集成电路及其形成方法
US8451581B2 (en) Passive coupler between package substrate and system board
US7812775B2 (en) Mm-wave fully integrated phased array receiver and transmitter with on-chip antennas
US7586193B2 (en) Mm-wave antenna using conventional IC packaging
JP2790033B2 (ja) 半導体装置
TWI663785B (zh) 電子裝置、射頻裝置及其訊號傳輸構件
CN102473690A (zh) 具有屏蔽层和电容耦合芯片侧电源端子的半导体器件
KR102302911B1 (ko) 전력 증폭 모듈
Božanić et al. Systems-level packaging for millimeter-wave transceivers
CN100550365C (zh) 电子器件及其承载衬底
CN109314298A (zh) 补偿电磁耦合器
Ahn et al. 28 GHz GaAs pHEMT MMICs and RF front‐end module for 5G communication systems
EP3414791B1 (en) Antenna package for a millimetre wave integrated circuit
Zhu et al. Investigation of the capacitance compensation structure for wire-bonding interconnection in multi-chips module
US6759742B2 (en) Interchangeable bond-wire interconnects
US6204815B1 (en) Increased propagation speed across integrated circuits
US7110741B2 (en) Radiofrequency unit
US10491172B2 (en) Systems and methods providing a matching circuit that bypasses a parasitic impedance
US20220093581A1 (en) Ic package providing isolated filter on lead-frame
US7466998B2 (en) Layout and architecture for reduced noise coupling between circuitry and on-chip antenna
JP2011172173A (ja) ミリ波回路モジュール及びそれを用いたミリ波送受信機
Weng et al. Development of a compact low-temperature co-fired ceramic antenna front-end module
CN219247834U (zh) 电子芯片和电子系统

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20090218

Termination date: 20190104

CF01 Termination of patent right due to non-payment of annual fee