CN100446224C - 配线基体部件及其制造方法 - Google Patents

配线基体部件及其制造方法 Download PDF

Info

Publication number
CN100446224C
CN100446224C CNB2005100746732A CN200510074673A CN100446224C CN 100446224 C CN100446224 C CN 100446224C CN B2005100746732 A CNB2005100746732 A CN B2005100746732A CN 200510074673 A CN200510074673 A CN 200510074673A CN 100446224 C CN100446224 C CN 100446224C
Authority
CN
China
Prior art keywords
film
matrix part
metal
metal film
distribution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB2005100746732A
Other languages
English (en)
Other versions
CN1702856A (zh
Inventor
臼井良辅
中村岳史
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Publication of CN1702856A publication Critical patent/CN1702856A/zh
Application granted granted Critical
Publication of CN100446224C publication Critical patent/CN100446224C/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/421—Blind plated via connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48237—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0388—Other aspects of conductors
    • H05K2201/0394—Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/07—Electric details
    • H05K2201/0753—Insulation
    • H05K2201/0769—Anti metal-migration, e.g. avoiding tin whisker growth
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09563—Metal filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09809—Coaxial layout
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0315—Oxidising metal
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

一种配线基体部件，具有绝缘树脂膜和设于其表面的第二导电膜及第一导电膜。另外，配线基体部件包括埋入设于绝缘树脂膜的凹部而形成且电连接绝缘树脂膜的表里的敷金属夹层。敷金属夹层含有覆盖凹部的侧壁形成的第一金属膜、覆盖第一金属膜形成的金属氧化膜、和设于金属氧化膜上的第二金属膜。

Description

配线基体部件及其制造方法
技术领域
本发明涉及配线基体部件及其制造方法。
背景技术
随着PDA、DVC、DSC这样的轻便型电子设备的高功能化加速，为使这样的制品被市场接受，而需要其小型、轻量化，为实现小型、轻量化，而要求高集成的系统LSI。另一方面，对这些电子设备要求更便于使用，对用于设备的LSI，要求高功能化、高性能化。因此，随着LSI芯片的高集成化，在要求其I/O数增大的同时，还强烈要求封装自身的小型化，为使两方面同时成立，强烈要求开发适合于半导体部件的高密度的衬底安装的半导体封装。为对应这样的要求，而开发了各种称为CSP(芯片尺寸封装Chip SizcPackage)的封装技术。例如专利文献1中记载有这种CSP。
在这种半导体封装中，为得到和电路元件的电连接，而在绝缘树脂膜上设置敷金属夹层(ビァ)。目前，这种敷金属夹层如下形成，首先，在绝缘树脂膜上形成敷金属夹层孔，在敷金属夹层孔内利用无电解镀敷法等形成薄膜，然后，利用电解镀敷法埋入敷金属夹层孔。
但是，近年来，伴随电子设备的高速化，开始使用铜作为形成敷金属夹层或配线的材料。对这样利用铜形成的敷金属夹层或配线，若如上所述以两阶段形成敷金属夹层时，存在利用无电解镀敷法形成的薄膜和形成于其上的电解镀敷膜的粘附性差的问题。另外，在这些膜间的界面，也存在产生应力徙动或电致徙动的问题。由此，存在配线的可靠性低的问题。
专利文献1：JP特开2003-249498号公报
专利文献2：JP特开2002-110717号公报
发明内容
本发明是鉴于上述问题点而开发的，本发明的目的在于，提供一种技术，其使在基体部件中形成金属材料构成的配线基体部件的稳定性良好。
根据本发明，提供一种配线基体部件，其特征在于，包括基体部件和构成埋入设于基体部件的凹部形成的配线的金属膜，金属膜包括覆盖凹部的侧壁形成的第一金属膜、覆盖第一金属膜形成的金属氧化膜、和设于金属氧化膜上的第二金属膜。
在此，所谓配线包括沿大致与衬底表面平行的平面延伸的配线、及收入敷金属夹层孔或接触孔中的连接孔配线(连接孔塞子)。在此，金属氧化膜的厚度可等于或小于10nm，最好等于或小于1nm。由此，可保持金属膜的电连接良好。另外，金属氧化膜的厚度可为等于或大于0.1nm。通过在第一金属膜和第二金属膜之间设置这种金属氧化膜，可使这些膜间的粘附性良好。另外，通过设置这样的金属氧化膜，可提高金属膜的应力徙动承受性或电致徙动承受性。
在本发明的配线基体部件中，第一金属膜和第二金属膜可由铜构成。在本发明的配线基体部件中，金属氧化膜可为使第一金属膜氧化的膜。在本发明的配线基体部件中，基体部件可为绝缘树脂膜。另外，基体部件可为搭载元件用的插入件(ィンタポ-ザ)。
根据本发明，提供一种配线基体部件的制造方法，其特征在于，包括：在基体部件上形成凹部的工序；覆盖凹部侧壁形成第一金属膜的工序；使第一金属膜表面氧化，在第一金属膜上形成金属氧化膜的工序；在金属氧化膜上形成第二金属膜的工序。可通过第一金属膜、金属氧化膜、及第二金属膜构成配线。
在本发明的配线基体部件的制造方法中，第一金属膜及第二金属膜可由铜构成。
任意组合本发明的结构作为本发明的方式也有效。另外，将本发明的表述方式变换为其它主题也包括在本发明的方式中。
附图说明
图1A～图1F是表示本发明实施形态的配线基体部件的制造顺序的工序剖面图；
图2是详细表示以图1A～图1F所示的顺序制造的敷金属夹层的结构的剖面图；
图3是表示含有以图1A～图1F所示的顺序制造的配线基体部件的半导体装置的剖面图；
图4是表示实施例中的敷金属夹层的剖面图的图；
图5是表示将图4的虚线包围的部分放大的TEM照片的图；
图6是表示实施例的剥离强度的测定结果的图。
具体实施方式
图1是表示本发明实施形态的配线基体部件的制造顺序的工序剖面图。首先，如图1A所示，准备在绝缘树脂膜106的两面形成有第一导电膜102及第二导电膜104的片状基体部件。然后，在形成有第二导电膜104的面上配置抗蚀剂，形成用于形成敷金属夹层孔的开口。以该抗蚀剂为掩模，利用湿式蚀刻选择地除去第二导电膜104。由此，可在形成敷金属夹层孔的区域除去第二导电膜104。另外，第二导电膜104也可以利用激光直描法(开孔对准)选择性地除去。
然后，以第二导电膜104为掩模，在绝缘树脂膜106上形成敷金属夹层孔108(图1B)。敷金属夹层孔108例如可适当组合二氧化碳激光、YAG激光、干式蚀刻及反向喷溅法而形成。在利用激光形成敷金属夹层孔108时，第一导电膜102作为截断层起作用。
二氧化碳激光以第一条件及改变脉冲宽度构成的第二条件两阶段照射。以0.25ms的脉冲周期，使用1.0W功率的激光，作为第一条件，可采用例如脉冲宽度为8～10μs，发射数为1。作为第二条件，可采用例如脉冲宽度为3～5μs，脉冲间隔等于或大于25ms，发射数为3。由此，形成具有圆锥形状侧壁的敷金属夹层孔108，该圆锥形状侧壁的直径从第二导电膜104向第一导电膜102的方向逐渐缩小。
然后，也可以利用使用YAG激光及氯或氟等卤系气体的干式蚀刻进行微细加工。此时，下层的第一导电膜102的表面也被除去一部分，在第一导电膜102上形成凹部(图2)。
然后，通过湿式处理粗化及清洗敷金属夹层孔108内。然后，首先利用无电解镀敷法形成第一金属膜110(约0.5～10μm)(图1C)。作为无电解镀敷用催化剂，可使用钯，为使无电解用催化剂附着于挠性绝缘树脂膜上，可使钯以配位化合物的状态含于水溶液，浸渍挠性的绝缘树脂膜，使钯的配位化合物附着在表面上，直接使用还原剂，还原成金属钯，形成用于开始镀敷的核。另外，第一金属膜110也可以通过喷溅法或CVD法形成。在通过喷溅形成第一金属膜110时，条件可例如为：Ar流量50sccm、压力5mtorr、AC150W、DC24kW、温度-40℃。
然后，向第一金属层110表面高压(约500kPa)吹空气(空气或氧气)，形成金属氧化膜112(约0.1～1nm)(图1D)。然后，在金属氧化膜112上利用电解镀敷法形成第二金属膜114(约20μm)，埋入敷金属夹层孔108内(图1E)。在本实施形态中，第一金属膜110及第二金属膜114可由铜构成。金属氧化膜112可为使铜氧化得到的第一氧化铜。在利用铜构成第二金属膜114时，可将第二导电膜104在室温下浸渍于硫酸铜水溶液中，利用电解镀敷法形成。
然后，将第二导电膜104及第一导电膜102构图成规定形状，形成配线。由此，得到配线基体部件101(图1F)。配线可通过以光致抗蚀剂为掩模，向例如从抗蚀剂露出的位置喷雾化学蚀刻液，蚀刻除去不需要的导电膜来形成。抗蚀剂可使用可用于通常的印刷线路板的抗蚀剂材料。此时，配线可丝网印刷抗蚀油墨而形成，或将抗蚀用感光性干膜层制在导电膜上，在其上使透光的光掩模与配线导体的形状重合，使紫外线曝光，利用显影液除去未曝光的位置来形成。在使用铜箔作为第一导电膜102或第二导电膜104时，化学蚀刻液可使用氯化铜和盐酸溶液、氯化铁溶液、硫酸和过氧化氢溶液、过硫酸胺溶液等用于通常的印刷线路板的化学蚀刻液。
然后，层积在两面设置第一导电膜102和第二导电膜104的绝缘树脂膜106，反复进行同样的处理，可得到多层配线结构。
图2是详细表示这样形成的敷金属夹层(连接孔配线)116的结构。这样，由于在第一金属膜110和第二金属膜114之间设有金属氧化膜112，故可使第一金属膜110和第二金属膜114的粘附性良好。另外，在利用铜构成这样的敷金属夹层116时，通过在敷金属夹层116中设置金属氧化膜112，可提高敷金属夹层孔的应力徙动承受性或电致徙动承受性。
如参照图1B的说明所述，若在形成敷金属夹层孔108时，在第一导电膜102上形成凹部，则构成敷金属夹层116的底部被第一导电膜102包围的结构，敷金属夹层116和第一导电膜102的接触面积增加，故也可以使这些导电材料低电阻化。
以上说明的配线基体部件可用于图3所示的半导体装置100。半导体装置100包括：配线基体部件101、载置于其上的电路元件120、密封电路元件120的密封树脂134、电连接电路元件120和第一导电膜102的接合线132、与敷金属夹层116电连接的补片126。电路元件120通过例如银膏等导电膏128固定在第一导电膜102上。另外，在构图有第一导电膜102及第二导电膜104的配线之间埋入光致抗焊剂124。电路元件120例如为晶体管、二极管、IC芯片等半导体元件，或片状电容、片状电阻等无源元件。另外，电路元件120也可以为层积了多个元件的形态。此时，多个元件的组合可为例如SRAM和闪存存储器、SRAM和PRAM。
在将半导体基体部件应用于这种半导体装置100时，各种材料可如下。第一导电膜102及第二导电膜104是例如轧制铜箔等轧制金属。
作为绝缘树脂膜106只要是可加热软化的材料，则也可以使用任何材料，可以使用例如环氧树脂、BT树脂等蜜胺衍生物、液晶聚合物、PPE树脂、聚酰亚胺树脂、氟树脂、酚醛树脂、聚酰胺双马来酰胺等。通过使用这样的材料，可提高配线基体部件的刚性。作为绝缘树脂膜106，可使用环氧树脂、或BT树脂、PPE树脂、聚酰亚胺树脂、氟树脂、酚醛树脂、聚酰胺双马来酰胺等热硬性树脂，通过使用这样的树脂，可进一步提高配线基体部件的刚性。
环氧树脂可列举双酚A型树脂、双酚F型树脂、双酚S型树脂、苯酚漆用酚醛树脂、甲酚醛清漆型环氧树脂、三苯酚甲烷型环氧树脂、脂环式环氧树脂等。
蜜胺衍生物可列举蜜胺、蜜胺三聚氰酸酯、羟甲基化蜜胺、(异)三聚氰酸酯、蜜白胺、蜜勒胺、蜜弄、琥珀胍胺、硫酸蜜胺、硫酸乙酰鸟粪胺、硫酸蜜白胺、硫酸脒基蜜胺、蜜胺树脂、BT树脂、三聚氰酸、异三聚氰酸、异三聚氰酸衍生物、蜜胺异三聚氰酸、苯并鸟粪胺、乙酰鸟粪胺等蜜胺衍生物、胍系化合物等。
液晶聚合物可列举芳香族类聚酯、聚酰亚胺、聚酯酰胺、或含有这些的树脂组合物。其中，优选耐热性、加工性及吸湿性平衡优良的液晶聚合物或含有液晶聚合物的组合物。
另外，也可以在绝缘树脂膜106中含有填充物或纤维等填充材料。填充物可使用例如粒子状或纤维状的SiO2或SiN。由于绝缘树脂膜106中含有填充物或纤维，从而可降低绝缘树脂膜106的挠曲。另外，在绝缘树脂106中含有纤维的情况下，可提高绝缘树脂膜106的流动性。从这样的观点来看，构成绝缘树脂106的材料优选使用芳族聚酰胺无纺布。由此，可使加工性良好。
芳族聚酰胺纤维可使用对位芳族聚酰胺纤维或间位芳族聚酰胺纤维。对位芳族聚酰胺纤维例如可使用聚对苯二甲酰对苯二胺(PPD-T)，间位芳族聚酰胺纤维例如可使用聚间正苯基异酞酰胺(MPD-I)。
实施例
例1
和以上的实施形态说明的同样地形成敷金属夹层孔，在敷金属夹层孔内利用无电解镀敷法形成第一金属膜110(约1μm)，然后，向第一氧化膜110表面高压(约500kPa)吹氧气，形成金属氧化膜112(约1nm)。进而在金属氧化膜112上利用电解镀敷法形成第二金属膜114(约20μm)。由此，形成敷金属夹层116。图4是表示这样形成的敷金属夹层的结构的剖面图。
图5是放大图4的虚线包围的部分的TEM照片。在此，图中可见粒状的低对比度部。考察该低对比度部为非晶质氧化膜。这样，显示通过吹氧气，在第一金属膜110和第二金属膜114之间形成金属氧化膜112。
例2
在衬底上通过无电解镀敷法形成第一金属膜(约1μm)后，向第一金属膜表面高压(约500kPa)吹氧气，形成金属氧化膜(约1nm)。进而在金属氧化膜上利用电解镀敷法形成第二金属膜(约20μm)，准备试样。另外，作为比较例，准备不吹氧而在第一金属膜表面直接形成第二金属膜的试样。
图6表示使用以上的试样测定多个位置(测定点1～5)的剥离强度的结果。如图6所示，在进行了吹氧的试样(图中记载为有氧化膜)中，与未进行吹氧的试样(图中记载为没有氧化膜)相比，显示剥离强度提高。
含有以上说明的配线基体部件101的半导体装置100可应用于以下说明的ISB(Integratcd System in Board：注册商标)。ISB是在以半导体裸片为中心的电子部件的封装中具有由铜构成的配线图案且不使用支承电路部件的芯(基体部件)的独自的无芯系统封装(参照专利文献2)。
ISB封装如下得到，在也作为支承衬底起作用的导电箔上形成多层导电图案，制造多层配线结构，进而安装电路元件，利用绝缘树脂模制，除去导电箔。在该情况下，导电箔可构成背面露出的结构。
根据该封装，可得到以下优点。
(i)由于可无心安装，故可实现晶体管、IC、LSI的小型、薄型化。
(ii)由于从晶体管到系统LSI、片状电容及电阻可形成电路并封装，故可实现高度的SIP(System in Package)。
(iii)由于可组合使用现有的半导体芯片，故可在短时间内开发系统LSI。
(iv)由于在半导体裸片下方没有芯材，故可实现良好的散热性。
(v)由于电路配线是铜件，且没有芯材，故构成低介电常数的电路配线，发挥在高速数据传送或高频电路中优良的特性。
(vi)由于为将电极埋入封装内部的结构，故可抑止电极材料的质子污染的产生。
(vii)由于封装尺寸自由，每一个的废弃物和64管脚的SQFP封装相比，约为1/10的量，故可降低环境负荷。
(viii)从载置部件的印刷线路板到带有功能的电路衬底，可实现新概念的系统结构。
(ix)ISB的图案设计和印刷线路板的图案设计同样容易，设备厂家的设计人员可自己设计。
以上，基于实施形态和实施例说明了本发明。该实施形态及实施例仅为例示，可进行各种变形，另外，这样的变形例也属于本发明的范围，这一点本领域人员容易理解。
在以上的实施形态中，图1E中表示了将敷金属夹层孔108完全由第二金属膜114埋入的形态，但也可以为敷金属夹层孔108不利用第二金属膜114埋入的形态。
另外，在以上的实施形态中，说明了使用激光等形成敷金属夹层孔108的形态，但在例如使用感光性材料作为绝缘树脂膜106时，也可以通过以第二导电膜104为掩模，对绝缘树脂膜106照射光，将光照射的部分除去，而形成敷金属夹层孔108。感光性材料例如可使用感光性聚酰亚胺树脂、感光性环氧树脂、光致抗焊剂、聚甲基丙烯酸甲酯(PMMA)等。光致抗焊剂例如可使用PDF300(新日铁化学株式会社制)或AUS402(太阳ィンキ制造株式会社制)。
另外，在以上的实施形态中，以在形成于绝缘树脂膜106的敷金属夹层孔108中形成敷金属夹层116的形态为例进行了说明，但本发明也可以适用于在形成于半导体衬底上的层间绝缘膜上形成配线或敷金属夹层的情况。

Claims (10)

1、一种配线基体部件，其特征在于，包括基体部件和构成埋入设于所述基体部件的凹部形成的配线的金属膜，所述金属膜包括覆盖所述凹部的侧壁形成的第一金属膜、覆盖所述第一金属膜形成的金属氧化膜、和设于所述金属氧化膜上的第二金属膜。
2、如权利要求1所述的配线基体部件，其特征在于，所述第一金属膜和所述第二金属膜由铜构成。
3、如权利要求1所述的配线基体部件，其特征在于，所述金属氧化膜是氧化所述第一金属膜得到的膜。
4、如权利要求2所述的配线基体部件，其特征在于，所述金属氧化膜是氧化所述第一金属膜得到的膜。
5、如权利要求1所述的配线基体部件，其特征在于，所述基体部件是绝缘树脂膜。
6、如权利要求2所述的配线基体部件，其特征在于，所述基体部件是绝缘树脂膜。
7、如权利要求3所述的配线基体部件，其特征在于，所述基体部件是绝缘树脂膜。
8、如权利要求4所述的配线基体部件，其特征在于，所述基体部件是绝缘树脂膜。
9、一种配线基体部件的制造方法，其特征在于，包括：在基体部件上形成凹部的工序；覆盖所述凹部的侧壁形成第一金属膜的工序；使所述第一金属膜表面氧化，在所述第一金属膜上形成金属氧化膜的工序；在所述金属氧化膜上形成第二金属膜的工序。
10、如权利要求9所述的配线基体部件的制造方法，其特征在于，所述第一金属膜及所述第二金属膜由铜构成。
CNB2005100746732A 2004-05-28 2005-05-30 配线基体部件及其制造方法 Expired - Fee Related CN100446224C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2004159802A JP4993848B2 (ja) 2004-05-28 2004-05-28 配線基材
JP159802/04 2004-05-28

Publications (2)

Publication Number Publication Date
CN1702856A CN1702856A (zh) 2005-11-30
CN100446224C true CN100446224C (zh) 2008-12-24

Family

ID=35425660

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2005100746732A Expired - Fee Related CN100446224C (zh) 2004-05-28 2005-05-30 配线基体部件及其制造方法

Country Status (4)

Country Link
US (1) US7491895B2 (zh)
JP (1) JP4993848B2 (zh)
CN (1) CN100446224C (zh)
TW (1) TWI293203B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102347243A (zh) * 2010-07-29 2012-02-08 三菱电机株式会社 半导体装置及其制造方法

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4787091B2 (ja) * 2006-06-27 2011-10-05 株式会社ディスコ ビアホールの加工方法
US8143532B2 (en) * 2009-02-05 2012-03-27 Xilinx, Inc. Barrier layer to prevent conductive anodic filaments
US8248803B2 (en) * 2010-03-31 2012-08-21 Hong Kong Applied Science and Technology Research Institute Company Limited Semiconductor package and method of manufacturing the same
US20110253439A1 (en) * 2010-04-20 2011-10-20 Subtron Technology Co. Ltd. Circuit substrate and manufacturing method thereof
US9142497B2 (en) 2011-10-05 2015-09-22 Harris Corporation Method for making electrical structure with air dielectric and related electrical structures
US8901435B2 (en) * 2012-08-14 2014-12-02 Bridge Semiconductor Corporation Hybrid wiring board with built-in stopper, interposer and build-up circuitry
US9237648B2 (en) * 2013-02-25 2016-01-12 Invensas Corporation Carrier-less silicon interposer
WO2016136497A1 (ja) * 2015-02-27 2016-09-01 ポリマテック・ジャパン株式会社 回路シートおよび回路シートの製造方法
US9437536B1 (en) 2015-05-08 2016-09-06 Invensas Corporation Reversed build-up substrate for 2.5D

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4696861A (en) * 1983-11-09 1987-09-29 Brother Kogyo Kabushiki Kaisha Substrate processed for electroless plating for printed wiring pattern and process for manufacturing the processed substrate
US5487218A (en) * 1994-11-21 1996-01-30 International Business Machines Corporation Method for making printed circuit boards with selectivity filled plated through holes
US6188027B1 (en) * 1999-06-30 2001-02-13 International Business Machines Corporation Protection of a plated through hole from chemical attack
US6346678B1 (en) * 1998-01-14 2002-02-12 Canon Kabushiki Kaisha Circuit board and method of manufacturing a circuit board
US20020185721A1 (en) * 1999-09-30 2002-12-12 Chan Seung Hwang Chip size package having concave pattern in the bump pad area of redistribution patterns and method for manufacturing the same

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3146125A (en) * 1960-05-31 1964-08-25 Day Company Method of making printed circuits
US3434939A (en) * 1965-10-07 1969-03-25 Fabri Tek Inc Process for making printed circuits
US3560257A (en) * 1967-01-03 1971-02-02 Kollmorgen Photocircuits Metallization of insulating substrates
US4054479A (en) * 1976-12-22 1977-10-18 E. I. Du Pont De Nemours And Company Additive process for producing printed circuit elements using a self-supported photosensitive sheet
US4581301A (en) * 1984-04-10 1986-04-08 Michaelson Henry W Additive adhesive based process for the manufacture of printed circuit boards
JPS61176192A (ja) * 1985-01-31 1986-08-07 株式会社日立製作所 銅と樹脂との接着方法
JPH0429397A (ja) * 1990-05-24 1992-01-31 Hitachi Chem Co Ltd 多層プリント配線板の製造方法
US5252195A (en) * 1990-08-20 1993-10-12 Mitsubishi Rayon Company Ltd. Process for producing a printed wiring board
US5340947A (en) * 1992-06-22 1994-08-23 Cirqon Technologies Corporation Ceramic substrates with highly conductive metal vias
JP3174474B2 (ja) * 1995-03-24 2001-06-11 イビデン株式会社 プリント配線板の製造方法
JPH11191675A (ja) * 1997-12-26 1999-07-13 Nippon Riironaaru Kk ビルドアッププリント配線板の製造方法
JP3691952B2 (ja) * 1998-01-30 2005-09-07 株式会社日立製作所 配線基板及びその製造方法
JP2002110717A (ja) 2000-10-02 2002-04-12 Sanyo Electric Co Ltd 回路装置の製造方法
JP2003249498A (ja) 2002-02-25 2003-09-05 Toshiba Corp 半導体装置の製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4696861A (en) * 1983-11-09 1987-09-29 Brother Kogyo Kabushiki Kaisha Substrate processed for electroless plating for printed wiring pattern and process for manufacturing the processed substrate
US5487218A (en) * 1994-11-21 1996-01-30 International Business Machines Corporation Method for making printed circuit boards with selectivity filled plated through holes
US6346678B1 (en) * 1998-01-14 2002-02-12 Canon Kabushiki Kaisha Circuit board and method of manufacturing a circuit board
US6188027B1 (en) * 1999-06-30 2001-02-13 International Business Machines Corporation Protection of a plated through hole from chemical attack
US20020185721A1 (en) * 1999-09-30 2002-12-12 Chan Seung Hwang Chip size package having concave pattern in the bump pad area of redistribution patterns and method for manufacturing the same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
US618802U7B1 2001.02.13

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102347243A (zh) * 2010-07-29 2012-02-08 三菱电机株式会社 半导体装置及其制造方法
CN102347243B (zh) * 2010-07-29 2014-08-20 三菱电机株式会社 半导体装置及其制造方法

Also Published As

Publication number Publication date
US20050266214A1 (en) 2005-12-01
JP4993848B2 (ja) 2012-08-08
JP2005340653A (ja) 2005-12-08
CN1702856A (zh) 2005-11-30
TWI293203B (en) 2008-02-01
TW200603369A (en) 2006-01-16
US7491895B2 (en) 2009-02-17

Similar Documents

Publication Publication Date Title
CN100446224C (zh) 配线基体部件及其制造方法
JP4020874B2 (ja) 半導体装置およびその製造方法
CN101393871B (zh) 层积半导体芯片的半导体装置制造方法
US8132320B2 (en) Circuit board process
CN100541749C (zh) 半导体装置及其制造方法
CN1329968C (zh) 利用无引线电镀工艺制造的封装基片及其制造方法
US9161445B2 (en) Printed wiring board and method for manufacturing printed wiring board
US7550316B2 (en) Board on chip package and manufacturing method thereof
JP2010239150A (ja) 半導体モジュールおよびその製造方法
JP2003209366A (ja) フレキシブル多層配線基板およびその製造方法
JPH0653344A (ja) 開孔形成方法及び電子回路カード
US20170019989A1 (en) Circuit board and manufacturing method of the same
KR20040051310A (ko) 도금 인입선을 사용하지 않는 패키지 기판 및 그 제조 방법
US6372540B1 (en) Moisture-resistant integrated circuit chip package and method
JP2000332160A (ja) キャビティダウン型半導体パッケージ
US20050067712A1 (en) Semiconductor apparatus and method of fabricating the same
US20070281390A1 (en) Manufacturing method of a package substrate
JP2004200668A (ja) 半導体装置およびその製造方法ならびに薄板状配線部材
KR20150043135A (ko) 금속막을 포함한 인쇄회로기판 및 그것을 포함한 반도체 패키지
JP2005109037A (ja) 半導体装置
JP2005236035A (ja) 半導体装置およびその製造方法
JP2005235982A (ja) 配線基板の製造方法と配線基板、および半導体パッケージ
JP4402256B2 (ja) 半導体チップ塔載用配線部材の製造方法
KR20070053829A (ko) 반도체 장치 및 이의 제조 방법
JP2005235980A (ja) 配線基板の製造方法と配線基板、および半導体パッケージ

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20081224

Termination date: 20140530