CN100438033C - 半导体芯片以及包含该半导体芯片的封装及电子装置 - Google Patents

半导体芯片以及包含该半导体芯片的封装及电子装置 Download PDF

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CN100438033C
CN100438033C CNB2006101011850A CN200610101185A CN100438033C CN 100438033 C CN100438033 C CN 100438033C CN B2006101011850 A CNB2006101011850 A CN B2006101011850A CN 200610101185 A CN200610101185 A CN 200610101185A CN 100438033 C CN100438033 C CN 100438033C
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CN1949514A (zh
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苏昭源
林忠毅
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明为一种可降低应力影响的半导体芯片以及包含该半导体芯片的封装及电子装置。该半导体芯片包括:一转角区域以及一中心区域;以及一排除区域,包括该转角区域,其中该转角区域的对角线长度大于该半导体芯片的对角线长度的约百分之一,其中一模拟电路位于排除区域之外,且其中该半导体芯片利用90nm或更小尺寸的半导体工艺技术所制成。本发明的优点在于不会增加额外的工艺步骤及成本,又可改善具有应力敏感性电路的集成电路的性能及可靠度。

Description

半导体芯片以及包含该半导体芯片的封装及电子装置
技术领域
本发明总的关于一种集成电路,特别有关于一种对应力敏感性集成电路的制造。
背景技术
随着半导体技术的进步,对于集成电路功能及性能的需求逐渐增加,因此在电路中需要更多的组件。其中提升集成电路性能最常用的方法就是缩小半导体组件的尺寸大小,90nm、65nm、甚至45nm的工艺技术已用来制造高性能组件。在封装时,多个管芯会堆叠在一起,而管芯上可能有类似或完全不同功能的集成电路。为了将管芯堆叠进行封装,管芯必须经过背部研磨工艺(backside grinding process)进行薄化,以将管芯的背部及无源区域研磨至所需的厚度。一般是先将晶片薄化后切割成管芯。
然而此过程的应力会造成不良影响,特别是当工艺小于90nm的组件其对应力相当敏感,不只是组件性能会受到影响,应力还会造成组件故障,降低集成电路的可靠度,且当管芯越薄时,会产生更大的应力使问题恶化。
一般为了解决应力问题,通常是以降低应力为解决办法,包括在封装时增加管芯或模封材料的厚度,但这种解决应力的方法并不符合实际的需求。此外,由于封装工艺的改变需要测试及调整,因此会增加其成本及延缓产品上市时间,且封装后也需要进行功能测试,以确保集成电路功能的正常运作。
因此业界急需一种方法来降低应力对于集成电路的影响。
发明内容
有鉴于此,本发明较佳实施例提供一种应力敏感性电路的半导体结构的形成方法以及利用此方法形成的半导体结构。
半导体结构包括一半导体芯片,该芯片包括:一转角区域以及一中心区域;以及一排除区域,包括该转角区域,其中该转角区域的对角线长度大于该半导体芯片的对角线长度的约百分之一,其中一模拟电路位于排除区域之外,且其中该半导体芯片利用90nm或更小尺寸的半导体工艺技术制成。
如本发明所述的半导体芯片将应力敏感性电路移至排除区域之外,以降低应力对电路的影响。应力敏感性电路包括模拟电路。
如本发明所述的半导体芯片的排除区域较佳包括该半导体芯片的转角区域,其中该转角区域的对角线的长度大于该半导体芯片对角线长度的百分之一,较佳大于该半导体芯片对角线长度的百分之二。
如本发明所述的半导体芯片,其中该排除区域还包括:一边缘区域,其中该边缘区域的长度及宽度分别大于该半导体芯片的长度及宽度的约百分之一。
如本发明所述的半导体芯片的应力敏感性模拟电路包括一组件,具有沟道长度小于约最小沟道长度的五倍或十倍。
本发明还提供一种电子装置,包括:一半导体芯片,利用65nm或更小的工艺技术制成,其中该芯片包括一转角区域、一边缘区域及一中心区域;一排除区域,包括该转角区域;以及多个模拟电路,位于该半导体芯片之上,其中具有一沟道长度小于约最小沟道长度十倍的MOS组件的所述模拟电路,均位于该排除区域之外。
如本发明所述的电子装置,其中所有所述模拟电路形成在该排除区域之外。
如本发明所述的电子装置,其中该半导体芯片的厚度约小于200μm。
如本发明所述的电子装置,其中还包括一堆叠芯片封装,具有一额外芯片,位于该半导体芯片之上。
本发明还提供一种半导体芯片封装,包括:一半导体芯片,其厚度约小于200μm,其中该半导体芯片利用90nm或更小尺寸的工艺技术所制造,且包括:一排除区域,包括该半导体芯片的一转角区域,其中该转角区域的对角线长度大于该半该芯片对角线长度的约百分之一;以及一模拟电路,包括一MOS组件,其中具有一沟道长度小于约最小沟道长度十倍的MOS组件的模拟电路,均位于该排除区域之外;以及一模封材料,位于该半导体芯片之上。
如本发明所述的半导体芯片封装,其中所有该模拟电路位于该排除区域之外。
如本发明所述的半导体芯片封装,其中该模封材料的厚度约小于300μm。
如本发明所述的半导体芯片封装,其中还包括一额外半导体芯片,堆叠在该半导体芯片之上。
如本发明所述的半导体芯片封装,其中该半导体芯片还包括至少四铜层位于一基底之上。
如本发明所述的半导体芯片封装,其中该最小沟道长度约小于90nm。
如本发明所述的半导体芯片封装,其中该模封材料的厚度约小于300μm。
本发明还提供一种形成本发明较佳实施例的方法,包括以下步骤:分析并区分出应力敏感性电路,提供一半导体芯片,划分出其排除区域,以及将应力敏感性电路形成在排除区域之外。
本发明的优点在于不会增加额外的工艺步骤及成本,又可改善具有应力敏感性电路的集成电路的性能及可靠度。
附图说明
图1显示在一半导体芯片上直线路径及对角线路径的定义。
图2显示沿直线路径的应力分布,其中芯片上的应力显示为标准化路径长度的函数。
图3显示沿对角线路径的应力分布,其中芯片上的应力显示为标准化路径长度的函数。
图4到图7显示半导体芯片上不同排除区域的俯视图。
图8显示具有单一管芯的半导体封装结构剖面图。
图9显示具有堆叠管芯的半导体封装结构剖面图。
其中,附图标记说明如下:
20芯片
22、24、26、28排除区域
C芯片对角线长度
C1、C2、C3排除区域对角线长度
A芯片长度
B芯片宽度
A2、A3排除区域长度
B2、B3排除区域宽度
32基底    34管芯
36模封材料
40、42管芯
具体实施方式
图1显示一半导体芯片,分别沿路径1-4仿真芯片上的应力分布,路径1及2为直线,其中路径1平行于x轴,路径2平行于y轴,而路径3及4则为沿着芯片对角线方向的对角线路径。图2显示一芯片样品上沿着路径1及2方向的应力分布,数字0.0代表路径开始,而1.0代表路径结束,由图可知,芯片的边缘具有最大的应力,而路径1及2的中心(标准化路径长度接近0.5)具有最小的应力,负的代表压应力,但在其它芯片样本上也可能为张应力。
图3显示沿着路径3及4方向管芯应力的变化,同样的,在芯片的转角部分应力最大,而路径3及4中心(标准化路径长度接近0.5)的应力最小。在芯片的转角区域的应力远大于中心区域。此外,转角区域的应力远大于边缘区域的应力。
在其它芯片样本上所获得的应力分布可能会不同于图2及图3所得的应力分布。虽然应力分布取决于许多因素,例如:基底材料的种类、管芯的尺寸、层间介电层或金属间介电层的材料以及金属化层的数量,但无论影响应力分布的因素为何,芯片转角的应力都大于芯片中心的区域。
在本发明的较佳实施例中,芯片上的电路将先进行分析并区分为应力敏感区及非应力敏感区。应力敏感性电路就是在具有应力的状况下芯片的性能及可靠度将会降低。一般来说,模拟电路对于应力具有较高的敏感度,因此更可能为应力敏感性电路。常用在移动电话、无线应用模块、PDA、手持电子装置或影像捕捉装置中的相位闭锁回路(phase-locked loop,PLL),数字模拟转换器(digital-analog converter,DAC)、模拟数字转换器(analog-digitalconverter,ADC)、调节器(regulator)、滤波器等较可能为应力敏感性电路。
应力敏感的定义跟集成电路的制造技术及设计需求有关,例如,高性能需求的集成电路通常会被认为是应力敏感性电路,因为只要性能表现上稍微的降低,就会使电路无法满足设计的需求。同样的电路若应用在低性能需求的设计中,则为非应力敏感性电路。
当组件具有越小的沟道长度则有越高的应力敏感度,在集成电路中,特别是模拟电路,由于具有很小的沟道长度,因此为应力敏感性电路。在上一代的集成电路中,由于组件尺寸较大且性能要求不高,因此应力对其影响较小。然而,新一代集成电路由于其较小的组件尺寸,会产生许多应力问题。因此,本发明提供一种小尺寸电路的制造方法,较佳应用在以90nm、65nm甚至45nm工艺技术所制造具有MOS组件的电路中。在一较佳实施例中,将沟道长度小于约最小沟道长度十倍的模拟电路归类为应力敏感性电路。在另一实施例中,将沟道长度小于约最小沟道长度五倍的模拟电路归类为应力敏感性电路。在65nm工艺技术中最小沟道长度约65nm,因此沟道长度小于约325nm的电路称之为应力敏感性电路。
芯片上的应力也会受芯片的结构及材料的影响。例如,以介电常数低于约3的低介电常数材料所制造的芯片一般具有高应力。大量的金属化层或具有高应力的金属化层,例如铜层,也都会造成高应力的可能性。在一实施例中,利用含碳材料作为低介电常数材料所制造的芯片,或利用至少四层铜金属化层所制造的芯片,皆会产生高应力问题。在90nm、60nm、45nm或更小的工艺技术中,或是使用超低介电常数材料与大量金属化层(例如超过八层铜金属化层)的产品中,应力将成为工艺中关键问题所在。因此,在分析及将电路分类时最好能将上述因素加入考虑。
在一较佳实施例中,应力敏感性电路大都排除在具有高应力的排除区域之外,而形成在同一芯片上剩余的区域。而非应力敏感性电路可形成在应力敏感区域中也可形成在非应力敏感区域中。
虽然排除区域24是由应力大小来决定,但也可由应力及位置之间的关系来决定。图4至图7显示芯片20的俯视图,其中芯片20具有多个不同的排除区域,值得注意的是,图标并非显示实际的尺寸比例,实际上排除区域的尺寸比例可能小于图示的尺寸比例。
图4显示本发明的较佳实施例,芯片20具有长度A、宽度B及对角线长度C。排除区域22包括芯片20的三角形转角区域,排除区域22的对角线长度C1大于芯片20对角线长度C的约百分之一,较佳大于约百分之二,最佳大于约百分之五。
图5显示本发明较佳实施例的变化例,排除区域24包括芯片20的转角区域,同样地,排除区域24的对角线长度C2大于芯片20对角线长度C的约百分之一,较佳大于约百分之二,最佳大于约百分之五。排除区域24的长度A2及宽度B2分别较佳大于芯片长度A及宽度B的约百分之一,更佳大于约百分之二。
图6显示本发明较佳实施例的另一变化例,排除区域26包括芯片20的边缘区域26及转角区域27,即包括芯片20的周边,图7显示本发明另一较佳实施例,其中排除区域28包括较图6大的转角区域。如图6及图7所示的实施例中,排除区域26及28的长度A3及宽度B3较佳大于芯片20长度A及宽度B的约百分之一,更佳大于约百分之二。如图7所示的实施例中,排除区域28的对角线长度C3较佳大于芯片20对角线长度C的约百分之一,较佳大于约百分之二,更佳大于约百分之五。
值得注意的是,排除区域的理想位置及尺寸取决于基底材料、管芯尺寸等因素。因此,排除区域尺寸及位置的决定,较佳通过测量具有类似尺寸及材料的芯片上的应力,并依设计原则决定应力敏感性电路可接受的应力范围。
集成电路的制造也受芯片(或封装工艺中的管芯)厚度及封装工艺的影响。当芯片厚度小于约200μm时,应力敏感性电路较佳形成在排除区域之外。
图8显示半导体封装的剖面图,包括一管芯34固定在封装基底32上。模封材料36覆盖在管芯34之上,其中模封材料36有助于降低管芯34上的应力,当模封材料36的厚度增加时则减少管芯34上残留的应力。当模封材料36厚度T小于约300μm时,管芯34上具有很高的应力,此时应力敏感性电路较佳形成在管芯34的排除区域之外。
图9显示堆叠管芯40及42固定在基底32之上,虽然图标中只显示两个管芯的堆叠,但也可堆叠更多管芯。由于堆叠管芯一般厚度都相当薄,因此产生很高的应力,同样的,当模封材料36的厚度T小于约300μm时,应力敏感性电路较佳形成在排除区域之外。
相较于一般的集成电路工艺,本发明不会增加额外的工艺步骤及成本,又可改善具有应力敏感性电路的集成电路的性能及可靠度,并缩短产品上市时间。
虽然本发明已以较佳实施例公开如上,但其并非用以限定本发明,任何本领域的技术人员,在不脱离本发明的精神和范围内,当可作些许的更动与润饰,因此本发明的保护范围当视后附的权利要求书所界定范围为准。

Claims (15)

1.一种半导体芯片,包括:
一转角区域以及一中心区域;以及
一排除区域,包括该转角区域,
其中该转角区域的对角线长度大于该半导体芯片的对角线长度的百分之一,
其中一模拟电路位于在排除区域之外,
且其中该半导体芯片利用90nm或更小尺寸的半导体工艺技术制成。
2.如权利要求1所述的半导体芯片,其特征在于,该转角区域的对角线长度大于该半导体芯片的对角线长度的百分之二。
3.如权利要求1所述的半导体芯片,其特征在于,该排除区域还包括:一边缘区域,其中该边缘区域的长度及宽度分别大于该半导体芯片的长度及宽度的百分之一。
4.如权利要求1所述的半导体芯片,其特征在于,该模拟电路包括一组件,具有一沟道长度小于最小沟道长度的十倍。
5.一种电子装置,包括:
一半导体芯片,利用65nm或更小的工艺技术制成,其中该芯片包括一转角区域、一边缘区域及一中心区域;
一排除区域,包括该转角区域;以及
多个模拟电路,位于该半导体芯片之上,其中具有一沟道长度小于最小沟道长度十倍的MOS组件的所述模拟电路,均位于该排除区域之外。
6.如权利要求5所述的电子装置,其特征在于,所有所述模拟电路形成在该排除区域之外。
7.如权利要求6所述的电子装置,其特征在于,该半导体芯片的厚度小于200μm。
8.如权利要求5所述的电子装置,其特征在于,还包括一堆叠芯片封装,具有一额外芯片,位于该半导体芯片之上。
9.一种半导体芯片封装,包括:
一半导体芯片,其厚度小于200μm,其中该半导体芯片利用90nm或更小尺寸的工艺技术制造,且包括:
一排除区域,包括该半导体芯片之一转角区域,其中该转角区域具有一对角线长度大于该半该芯片对角线长度的百分之一;以及
一模拟电路,包括一MOS组件,其中具有一沟道长度小于最小沟道长度十倍的MOS组件的所述模拟电路,均位于该排除区域之外;以及
一模封材料,位于该半导体芯片之上。
10.如权利要求9所述的半导体芯片封装,其特征在于,所有该模拟电路位于该排除区域之外。
11.如权利要求9所述的半导体芯片封装,其特征在于,该模封材料的厚度小于300μm。
12.如权利要求9所述的半导体芯片封装,其特征在于,还包括一额外半导体芯片,堆叠在该半导体芯片之上。
13.如权利要求9所述的半导体芯片封装,其特征在于,该半导体芯片还包括至少四铜层位于一基底之上。
14.如权利要求9所述的半导体芯片封装,其特征在于,该最小沟道长度小于90nm。
15.如权利要求9所述的半导体芯片封装,其特征在于,该模封材料的厚度小于300μm。
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US9691749B2 (en) 2017-06-27
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