CN100437932C - 高介电常数氧化物膜的制造法、含该膜的电容器及制造法 - Google Patents

高介电常数氧化物膜的制造法、含该膜的电容器及制造法 Download PDF

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CN100437932C
CN100437932C CNB2004100283929A CN200410028392A CN100437932C CN 100437932 C CN100437932 C CN 100437932C CN B2004100283929 A CNB2004100283929 A CN B2004100283929A CN 200410028392 A CN200410028392 A CN 200410028392A CN 100437932 C CN100437932 C CN 100437932C
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film
oxide film
dielectric
atomic layer
dielectric oxide
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CN1531032A (zh
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李正贤
徐范锡
闵约赛
曹永真
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Samsung Electronics Co Ltd
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Abstract

本发明提供一种高介电常数氧化物膜的制造法、含该膜的电容器及制造法。制造高k介电氧化物膜的步骤是：(a)将半导体衬底装载到ALD装置中；(b)在半导体衬底上沉积具有第一元素和第二元素的预定成分比的反应材料；和(c)通过氧化反应材料使得第一元素和第二元素同时氧化，在半导体衬底上形成具有所述两种元素的第一高k介电氧化物膜。在该方法中，减小了装置的尺寸，提高了产量，且降低了制造成本。而且该高k介电氧化物膜表现出高介电常数和低泄漏电流和陷阱密度。于是，包括作为介电膜的该高k介电氧化物膜的电容器也表现出低泄漏电流和陷阱密度。

Description

高介电常数氧化物膜的制造法、含该膜的电容器及制造法
技术领域
本发明涉及一种制造材料膜的方法，采用该方法形成的电容器及其制造方法。更具体地，本发明涉及一种制造具有高介电常数的氧化物膜的方法，具有用该方法形成的介电膜的电容器，及其制造方法。
背景技术
随着诸如DRAM的半导体器件的集成密度的增加，使用二氧化硅(SiO2)膜制造栅氧化物膜或电容器变得更加复杂。因此，更加关注和研究具有比氧化硅膜的介电常数高的介电常数的材料。
具有高介电常数的材料(此后称为“高k介电材料”)是氧化铝(Al2O3)膜、氧化铪(HfO2)膜等。尤其是，加强研究多层结构，其中具有较低漏电流的氧化铝膜和具有较高介电常数的氧化铪膜顺序叠置。
近年来，尝试使用高k介电材料例如HfO2、ZrO2和SrTiO3来形成电容器或DRAM的栅氧化物膜。然而，在金属/绝缘体/硅(MIS)结构中，其中下电极由硅(Si)形成，因为高k介电材料通常具有低能带偏移(band offset)，所以漏电流增加。由于这个原因，实际上难以将这些高k介电材料应用于MIS结构中。
结果是，开发出在硅膜和高k介电材料之间形成氧化铝膜的方法，以降低漏电流，该氧化铝膜对于硅膜来说具有较低介电常数和高能带偏移。例如，已投入资金研究多层结构，其中硅膜、氧化铝(Al2O3)膜和高k介电材料顺序堆叠。
图1至3示出了将高k介电氧化物膜制成多层结构的传统方法。
参见图1，在硅膜10上形成氧化阻挡膜12。氧化阻挡膜12是使用快速热处理(RTP)形成的氮化物膜。在形成氧化阻挡膜12后，如图2所示，在氧化阻挡膜12上形成氧化铝膜14。接着，如图3所示，在氧化铝膜14上形成介电常数高于氧化铝膜14的介电常数的氧化铪膜16。附图标记18表示由多晶硅形成的虚拟上电极。
在制造高k介电氧化物膜的传统方法中，由于氧化铝膜的低介电常数，所以不能充分增大电容器的容值，该传统方法中氧化铝膜和氧化铪膜顺序堆叠。而且，由于必须在不同温度下形成氧化铝膜和氧化铪膜，因此需要两种不同的原子层沉积(atomic layer deposition)(ALD)装置。
即，根据传统方法，至少需要两个ALD装置。而且，氧化铪膜的沉积速率低于氧化铝膜的沉积速率，因此降低产量。而且，由于在电容器制备后，在执行热处理期间高k介电氧化物膜可能会结晶，因此漏电流会增加。
发明内容
本发明提供一种制造高k介电氧化物膜的方法，通过该方法减小所用装置的尺寸且提高产量。
本发明还提供一种采用该制造高k介电氧化物膜的方法形成的半导体器件的电容器。
本发明还提供一种制造该电容器的方法。
根据本发明的一个方面，提供一种制造高k介电氧化物膜的方法，其包括：(a)将半导体衬底装载在ALD装置中；(b)在半导体衬底上沉积具有第一元素和第二元素的预定成分比的反应材料；以及(c)通过氧化反应材料，使得第一元素和第二元素同时氧化，来在半导体衬底上形成具有该两种元素的第一高k介电氧化物膜。
本发明的方法还可包括：在形成第一高k介电氧化物膜之后，从ALD装置中排出剩余物，以及通过重复步骤(b)和(c)，在第一高k介电氧化物膜上形成第二高k介电氧化物膜。
步骤(b)包括：将具有第一元素的第一前体提供到ALD装置中，以将第一前体吸附在半导体衬底上；从ALD装置中排出剩余物；将具有与第一元素反应的第二元素的第二前体提供给ALD装置；以及从ALD装置中排出剩余物。
优选地，第一前体是第一元素和具有高电负性(electronegativity)的氯(Cl)和氟(F)中之一的合成物(composition)，而第二前体是第二元素和具有比氯或氟的电负性更低的电负性的烃系配体(a ligand of hydrocarbon series)的合成物。这里，烃系配体可以是CH2-CH2-...-CH3，或CH2-CH2-...-CH3的部分H被CH2-CH2-...-CH3替代的合成物。
在将半导体衬底装载到ALD装置中之前，可以在半导体衬底上形成氧化阻挡膜。
优选地第一元素和第二元素可分别是铪(Hf)和铝(Al)。第一高k介电氧化物膜可以是AHO((Alx，Hf1-x)Oy)膜，第二高k介电氧化物膜可以由AHO膜或者具有比AHO膜的介电常数更高的介电常数的介电膜形成。
第三高k介电氧化物膜，如具有比AHO膜的介电常数更高的介电常数的介电膜，还可形成在第一高k介电膜上。在除ALD装置外的沉积装置中形成第三高k介电氧化物膜。
根据本发明的另一方面，提供一种半导体器件的电容器，该电容器包括：下电极；形成在下电极上的AHO((Alx，Hf1-x)Oy)膜；以及形成在AHO膜上的上电极。
根据本发明的又一方面，提供一种制造半导体器件的电容器的方法，该方法包括：(a)在半导体衬底上形成下电极；(b)将其上形成有下电极的半导体衬底装载到ALD装置中；(c)在ALD装置中将具有第一元素和第二元素的预定成分比的反应材料沉积到下电极上；(d)通过氧化反应材料，使得第一元素和第二元素同时氧化，从而在下电极上形成具有所述两种元素的第一高k介电氧化物膜；(e)从ALD装置中卸载沉积有第一高k介电氧化物膜的所得结构；以及(f)在第一高k介电氧化物膜上形成上电极。
本发明的方法还可包括：在形成第一高k介电氧化物膜之后，从ALD装置中排出剩余物；以及通过重复步骤(c)和(d)，在第一高k介电氧化物膜上形成第二高k介电氧化物膜。
步骤(c)与制造该高k介电氧化物膜的方法中的相同。
在将半导体衬底装载到ALD装置中之前，在下电极上可以形成氧化阻挡膜。
在形成上电极之前，可以以不同于形成第二高k介电氧化物膜的方法的方法形成第三高k介电氧化物膜。例如，第三高k介电氧化物膜可以由具有比AHO膜的介电常数更高的介电常数的介电膜形成，并使用除ALD装置外的沉积装置，如CVD装置。
根据本发明，可以减小所用沉积装置的尺寸，而不会降低高k介电氧化物膜的性能。而且，可以节省沉积所需的时间，从而提高产量。
附图说明
通过参考附图详细描述本发明的示例性实施例，本发明的前述和其它特征和优点将变得更明显，在附图中：
图1至3是示出制造高k介电氧化物膜的传统方法的剖面图；
图4至13是示出根据本发明实施例的制造高k介电氧化物膜的方法的剖面图；
图14是示出氧化物膜的成分比随着沉积温度变化的曲线图，其影响根据本发明实施例的制造高k介电氧化物膜的方法；
图15A和15B分别是在根据本发明的实施例形成高k介电氧化物膜之后立即拍摄的示出了叠层结构的结晶程度的透射电子显微照片(TEM)、以及示出EDS分析结果的曲线图；
图16A和16B分别是在对形成了高k介电氧化物膜的所得结构退火之后拍摄的显示叠层结构的结晶程度的TEM、以及示出EDS分析结果的曲线图；
图17A和17B分别是显示根据传统方法和本发明形成的高k介电氧化物膜的电容-电压(C-V)变化的曲线图；以及
图18至21是使用根据本发明实施例的制造高k介电氧化物膜的方法形成的具有介电膜的电容器的剖面图。
具体实施方式
本申请要求于2003年3月11日向韩国知识产权局提交的韩国专利申请第2003-15197号的优先权，这里将其全文作参考引用。
将参考附图详细地描述根据本发明实施例的制造高k介电氧化物膜的方法、具有使用该方法形成的介电膜的电容器、以及制造该电容器的方法。在附图中，为清晰起见，放大了元件的形状。
在下文中，提供一种制造具有高介电常数以及低漏电流和低陷阱密度的高k介电氧化物膜的方法，该方法利用含铝前体和用于沉积高k介电材料层的另一前体的化学反应，还提供一种具有使用该方法形成的高k介电氧化物膜的电容器、以及制造该电容器的方法。
首先，参考图4至13描述根据本发明实施例的制造高k介电氧化物膜的方法。
图4和5分别是根据本发明的第一实施例和第二实施例形成的所得结构的剖面图。在图4和5中，附图标记40表示半导体衬底，42表示AHO((Alx，Hf1-x)Oy)膜。在图5中，附图标记44表示形成在半导体衬底40和AHO膜42之间的氧化阻挡膜，例如快速热处理氮化物膜(此后称为“RTN层”)。
实施例1
将其上待形成高k介电氧化物膜的半导体衬底例如硅衬底装载在ALD装置的晶片台上(未显示)。然后，预定量的含第一元素如铪(Hf)的第一前体被提供给ALD装置，且被化学吸附在半导体衬底40的表面上，如图6所示。第一前体46是第一元素和如Cl和F的具有高电负性的配体的合成物。例如，第一前体46是HfCl4。第一前体的没有被吸附在半导体衬底40的表面上的部分从ALD装置中排出。此后，含第二元素如铝(Al)的第二前体被提供给ALD装置，该第二元素与第一前体46的第一元素反应。第二前体是第二元素和烃系配体的合成物，例如Al(CH3)3、Al(CH2-CH2-...-CH3)、或Al(CH2-CH2-...-CH3)的一个H被CH2-CH2-...-CH3所取代的合成物。烃系配体具有比第一前体(precursor)中所含的Cl或F的电负性更低的电负性。
由于第一前体的配体的电负性不同于第二前体的配体的电负性，例如，第一前体中所含的氯容易与第二前体中所含的烃系元素发生反应。通过该反应，第一和第二前体的配体被作为副产物除去。结果是，通过化学吸附第一元素和第二元素得到的反应材料沉积在半导体衬底40上。
具体地，如图7所示，在第二前体47和第一前体46之间发生化学反应。第一前体46的配体(-Cl)和第二前体47的配体(-CH3)结合并挥发，于是用第二前体47中所含的铝填充因去除第一前体46的配体而形成的空缺(vacancy)。结果是，如图8所示，包括两种正离子即Hf离子和Al离子的反应材料(Hf-Al)48被均匀地形成在半导体衬底40上。
接着，将用于氧化反应材料48的如O3和H2O的预定量的氧化气体提供到形成有反应材料48的半导体衬底40上。氧化气体与铪和铝同时反应。即，形成在半导体衬底40上的反应材料48被氧化，从而在半导体衬底40上形成氧化剂((Alx，Hf1-x)Oy)50，如图9所示。在氧化剂((Alx，Hf1-x)Oy)50中，值“x”的范围是从0.1至0.9，值“Y”的范围是从2至5。在图9中，附图标记50a表示由氧化剂50形成的高k介电氧化物膜，即AHO层。
提供第一前体46至氧化该反应材料48优选地在预定温度下进行，例如250℃至400℃，更优选地在300℃。
然而，如图14所示，因为反应材料48的成分比(Hf/(Al+Hf))随着温度而变化，所以可以通过控制温度来调整成分比，且可以改变前述示例性温度范围。例如，在反应材料48具有一特定成分比，因而表现出良好的漏电流性能和/或介电常数性能的情况下，将示例性处理温度改变至反应材料48具有该特定成分比的温度。
在图14中，附图标记G1表示第一曲线，该曲线示出了反应材料48的成分比随处理温度的变化。
接着，如图9所示，在半导体衬底40上形成高k介电氧化物膜50a，然后执行排出工艺，以便从ALD装置中除去剩余气体。接着，重复n次从供应第一前体46至氧化反应材料48至排出剩余气体，直至在半导体衬底40上沉积所需厚度的高k介电氧化物膜。在执行最终排出工艺后，在预定温度下对完成的高k介电氧化物膜进行热处理。
实施例2
如图10至13所示，第二实施例中的制造步骤与第一实施例中的制造步骤相同，其不同之处在于，供应第一前体46至最终步骤在半导体衬底40上形成了氧化阻挡膜44之后进行。氧化阻挡膜44是氮化物膜，它通过将半导体衬底40装载到氮气氛炉中、以及使用RTP对其处理预定时间段来获得。氧化膜44可以防止被沉积在半导体衬底40上的介电材料和硅之间的反应。于是，可以稳定地维持介电材料的介电常数。氧化阻挡膜44可以用氮氧化硅(SiON)形成。
此后，将基于测量结果，描述根据本发明实施例的高k介电氧化物膜的性能。
图15A是TEM，示出了根据本发明形成的AHO膜的结晶程度；图15B示出了第二曲线G2和第三曲线G3，其分别示出了铪和铝的含量随AHO层位置的变化。图15A和15B示出了在形成AHO膜之后和在热处理AHO膜以便结晶之前立即测量的结果。同时，图16A和16B与图15A和15B类似，不同之处在于测量结果是在热处理AHO膜以便结晶之后得到的。在图16B中，附图标记G4和G5分别表示第四曲线和第五曲线，其分别对应于第二曲线G2和第三曲线G3。
参考图15A，半导体衬底40的结晶线Lc终止在半导体衬底40和氧化阻挡膜44之间的界面处。而且，图16A显示出与图15A类似的结果。因此，可以推断出在本发明中，可以抑制热处理期间AHO膜的结晶。
在本发明中，由于AHO膜被形成至约30
Figure C20041002839200121
的薄厚度，所以AHO膜的结晶度没有降低，而是增加漏电流。因此，如图15A和16A所示，如果AHO膜的结晶被抑制，则也可抑制漏电流。
这里，AHO膜的漏电流的抑制程度与AHO层的成分比密切相关。于是，漏电流的抑制程度受到反应材料48的沉积温度的影响。
在图15B和16B中，水平轴代表测量位置。测量位置沿垂直方向，从形成于半导体衬底40上的AHO膜42的表面直到半导体衬底40(位置“20”或“40”)分布。
参考图15B和16B的第二至第五曲线G2、G3、G4和G5，在最终热处理以便结晶之前测量的AHO层中所含的铪和铝含量的分布情况(G2和G3)类似于在最终热处理后测量的分布情况(G4和G5)。基于上述结果，即使在完成最终热处理之后，AHO层中所含铪和铝的含量的分布得以保留。
另外，图17A和17B示出了电容随偏压的变化。图17A示出了关于一电容器(此后称为“传统电容器”)的电容-电压(C-V)变化，该电容器包括通过传统的制造高k介电氧化物膜的方法形成的氧化铝膜；且17B示出了关于一电容器(此后称为“本发明电容器”)的C-V变化，该电容器包括根据本发明的AHO膜。
在图17A中，第六曲线G6示出了当从正(+)到负(-)将偏压施加到传统电容器上时电容量的变化，第七曲线G7示出了当从负(-)到正(+)施加偏压时电容量的变化。
在图17B中，第八曲线G8示出了当从正(+)到负(-)将偏压加到本发明电容器上时电容量的变化，第九曲线G9示出了当从负(-)到正(+)加偏压时电容量的变化。
如图17A所示，在第六曲线G6和第七曲线G7之间存在间隙，这是由存在于传统电容器的高k介电氧化物膜(即氧化铝膜)中的陷阱造成的。
另一方面，如图17B所示，与第六曲线G6和第七曲线G7不相同，在第八曲线G8和第九曲线G9之间不存在间隙。这意味着在本发明电容器包括的如AHO膜或由AHO膜和另外的高k介电氧化物膜(如图19的42、62)形成的材料膜的高k介电氧化物膜中不存在陷阱，或者在本发明电容器中存在密度比传统电容器中低得多的陷阱。
根据本发明的用于制造高k介电氧化物膜的上述方法(此后称为“本发明方法”)可以应用于形成栅氧化物膜或电容器的介电膜。图18至21是半导体器件的电容器的剖面图，其包括使用本发明方法形成的介电膜。
在图18所示的电容器中，在下电极60a上形成氧化阻挡膜44，且在氧化阻挡膜44上形成AHO((Alx，Hf1-x)Oy)膜42，作为高k介电膜。在AHO((Alx，Hf1-x)Oy)膜42中，值“x”的范围从0.1至0.9，且值“y”的范围从2至5。在AHO膜42上布置上电极60b。下电极60a是与下半导体衬底(未显示)连接的硅电极，且氧化阻挡膜44是RTN膜或氮氧化硅(SiON)膜。上电极60b例如由多晶硅形成。AHO膜42是通过本发明方法得到的介电膜。作为AHO层的替代物，图18所示的电容器和图19至21所示的其它电容器中可以包括任何其它的等效介电膜。
同时，如图19所示，还可在上电极60b和AHO膜42之间形成介电层，例如HfO2层、ZrO2或STO层，其具有比AHO膜42的介电常数更高的介电常数。在图19中，附图标记62表示包括在AHO膜42和上电极60b之间的高k介电膜。
图20示出了从图18所示的电容器中去掉氧化阻挡膜44的情况。类似地，还可在AHO膜42和上电极60b之间形成如图19所示的高k介电膜62。
图21示出了具有空间电极(sterical electrode)的电容器。这里，下电极78a具有柱形形状，且经由导电插塞76与半导体衬底70连接，导电插塞76填充形成在层间电介质(ILD)72中的接触孔74。下电极78a被氧化阻挡膜44覆盖。氧化阻挡膜44可以选择性地形成。氧化阻挡膜44被具有预定厚度的AHO膜42覆盖。AHO膜42是通过本发明方法得到的介电膜。AHO膜42被由诸如多晶硅形成的上电极78b覆盖。类似地，还可在上电极78b和AHO膜42之间形成如图19所示的高k介电膜62。在这种情况下，可以选择性地形成氧化阻挡膜44。即，由于AHO膜42和下电极78a之间的反应性很小，所以如果需要，可以形成氧化阻挡膜44。
同时，下文中将简要介绍图18至21中所示电容器的制造方法。
将下电极60a或78a形成为与半导体衬底(未显示)连接。接着，将形成有下电极60a或78a的半导体衬底装载到ALD装置中，且通过本发明方法，在下电极60a或78a上形成高k介电氧化物膜42作为介电膜。此后，将堆叠有高k介电氧化物膜42的所得结构从ALD装置中取出。然后，在预定沉积装置中，在高k介电氧化物膜42上形成上电极60b或78b。
如图18、19和21所示，制造电容器的方法还可包括在下电极60a或78a与高k介电氧化物膜42之间形成氧化阻挡膜44。而且，还可在上电极60a或78b与高k介电氧化物膜42之间形成如图19所示的介电膜62，其具有比高k介电氧化物膜42的介电常数更高的介电常数。这里，尽管介电膜62优选在ALD装置中形成，但是也可在除ALD装置外的沉积装置如化学气相沉积(CVD)装置中形成介电膜62。
如上所述，根据本发明的制造高k介电氧化物膜如AHO膜的方法包括：利用铝和铪的前体之间的化学反应在半导体衬底上沉积铝离子和铪离子，且同时氧化铝离子和铪离子。因此，与要求至少两个ALD装置的传统方法不同，本发明仅需要一个ALD装置。结果是，在本发明中，可以减小装置的尺寸，可以提高产量，并且可以降低制造成本。而且，本发明的高k介电氧化物膜如AHO膜除了具有低泄漏电流和陷阱密度外，还表现出高介电常数。结果是，包括该高k介电氧化物膜作为介电膜的电容器也表现出低泄漏电流和低陷阱密度。
尽管已经参考本发明的示例性实施例具体显示和描述了本发明，但是本领域的普通技术人员可以理解，可以对其作各种形式和细节上的变化，而不脱离由所附权利要求限定的本发明的精神和范围。例如，本领域普通技术人员可以形成在高k介电膜之上和之下包括AHO膜的电容器。

Claims (37)

1.一种制造高k介电氧化物膜的方法，该方法包括：
a、将半导体衬底装载到原子层沉积装置中；
b、在该半导体衬底上沉积具有第一元素和第二元素的预定成分比的反应材料；以及
c、通过氧化该反应材料，使得该第一元素和该第二元素同时氧化，从而在该半导体衬底上形成具有所述两种元素的第一高k介电氧化物膜。
2.如权利要求1所述的方法，还包括：
在形成该第一高k介电氧化物膜后，从该原子层沉积装置中排出剩余物；以及
通过重复步骤b和c，在该第一高k介电氧化物膜上形成第二高k介电氧化物膜。
3.如权利要求1所述的方法，其中步骤b包括：
将具有该第一元素的第一前体提供给该原子层沉积装置，将该第一前体吸附在该半导体衬底上；
从该原子层沉积装置中排出剩余物；
将具有与该第一元素反应的该第二元素的第二前体提供给该原子层沉积装置；以及
从该原子层沉积装置中排出剩余物。
4.如权利要求2所述的方法，其中步骤b包括：
将具有该第一元素的第一前体提供给该原子层沉积装置，将该第一前体吸附在该半导体衬底上；
从该原子层沉积装置中排出剩余物；
将具有与该第一元素反应的该第二元素的第二前体提供给该原子层沉积装置；以及
从该原子层沉积装置中排出剩余物。
5.如权利要求3所述的方法，其中该第一前体是该第一元素与氯和氟中之一的合成物。
6.如权利要求5所述的方法，其中该第二前体是该第二元素和烃系配体的合成物，该烃系配体具有比氯或氟的电负性更低的电负性。
7.如权利要求6所述的方法，其中该烃配体是CH2-CH2-...-CH3、或CH2-CH2-...-CH3的部分H被CH2-CH2-...-CH3替代的合成物。
8.如权利要求1所述的方法，其中在将该半导体衬底装载到该原子层沉积装置中之前，在该半导体衬底上形成氧化阻挡膜。
9.如权利要求1所述的方法，其中该第一元素和该第二元素分别是铪和铝。
10.如权利要求1所述的方法，其中该第一高k介电氧化物膜是(Alx，Hf1-x)Oy膜。
11.如权利要求2所述的方法，其中该第一高k介电氧化物膜是(Alx，Hf1-x)Oy膜。
12.如权利要求2所述的方法，其中该第二高k介电氧化物膜由(Alx，Hf1-x)Oy膜形成。
13.如权利要求11所述的方法，其中该第二高k介电氧化物膜由(Alx，Hf1-x)Oy膜形成。
14.如权利要求1所述的方法，其中还在该第一高k介电氧化物膜上形成第三高k介电氧化物膜。
15.如权利要求4所述的方法，其中该第一前体包括作为该第一元素的铪。
16.如权利要求4所述的方法，其中该第二前体包括作为该第二元素的铝。
17.如权利要求15所述的方法，其中该第二前体包括作为该第二元素的铝。
18.如权利要求8所述的方法，其中该氧化阻挡膜由快速热氮化物膜或氮氧化硅膜形成。
19.如权利要求14所述的方法，其中该第三高k介电氧化物膜由具有比(Alx，Hf1-x)Oy膜的介电常数更高的介电常数的介电膜形成。
20.如权利要求19所述的方法，其中在除该原子层沉积装置外的沉积装置中形成具有比(Alx，Hf1-x)Oy膜的介电常数更高的介电常数的该介电膜。
21.如权利要求9所述的方法，其中步骤b和c在同一温度下进行。
22.一种半导体器件的电容器，该电容器包括：
下电极；
形成在该下电极上的(Alx，Hf1-x)Oy膜，其中x范围为0.1至0.9，y范围为2至5；以及
形成在该(Alx，Hf1-x)Oy膜上的上电极。
23.如权利要求22所述的电容器，还包括形成在该下电极和该(Alx，Hf1-x)Oy层之间的氧化阻挡膜。
24.如权利要求22所述的电容器，还包括在该上电极和该(Alx，Hf1-x)Oy层之间的具有比该(Alx，Hf1-x)Oy膜的介电常数更高的介电常数的介电膜。
25.如权利要求23所述的电容器，还包括在该上电极和该(Alx，Hf1-x)Oy层之间的具有比该(Alx，Hf1-x)Oy膜的介电常数更高的介电常数的介电膜。
26.一种制造半导体器件的电容器的方法，该方法包括：
a、在半导体衬底上形成下电极；
b、将其上形成有该下电极的该半导体衬底装载到原子层沉积装置中；
c、在该原子层沉积装置中将具有第一元素和第二元素的预定成分比的反应材料沉积到该下电极上；
d、通过氧化该反应材料，使得该第一元素和该第二元素同时氧化，从而在该下电极上形成具有所述两种元素的第一高k介电氧化物膜；
e、从该原子层沉积装置中卸载沉积有该第一高k介电氧化物膜的所得结构；以及
f、在该第一高k介电氧化物膜上形成上电极。
27.如权利要求26所述的方法，还包括：
在形成该第一高k介电氧化物膜之后，从该原子层沉积装置中排出剩余物；以及
通过重复步骤c和d，在该第一高k介电氧化物膜上形成第二高k介电氧化物膜。
28.如权利要求26所述的方法，其中步骤c包括：
将具有该第一元素的第一前体提供给该原子层沉积装置，将该第一前体吸附在该半导体衬底上；
从该原子层沉积装置中排出剩余物；
将具有与该第一元素反应的该第二元素的第二前体提供给该原子层沉积装置；以及
从该原子层沉积装置中排出剩余物。
29.如权利要求27所述的方法，其中步骤c包括：
将具有该第一元素的第一前体提供给该原子层沉积装置，将该第一前体吸附在该半导体衬底上；
从该原子层沉积装置中排出剩余物；
将具有与该第一元素反应的该第二元素的第二前体提供给该原子层沉积装置；以及
从该原子层沉积装置中排出剩余物。
30.如权利要求26所述的方法，其中在将该半导体衬底装载到该原子层沉积装置中之前，在该下电极上形成氧化阻挡膜。
31.如权利要求26所述的方法，其中该第一高k介电氧化物膜是(Alx，Hf1-x)Oy层。
32.如权利要求27所述的方法，其中该第一高k介电氧化物膜是(Alx，Hf1-x)Oy层。
33.如权利要求27所述的方法，其中该第二高k介电氧化物膜是(Alx，Hf1-x)Oy膜或具有比该(Alx，Hf1-x)Oy膜的介电常数更高的介电常数的介电膜。
34.如权利要求28所述的方法，其中该第一前体包括铪，该第二前体包括铝。
35.如权利要求26所述的方法，在形成该上电极之前，还包括在该第一高k介电氧化物膜上形成第三高k介电氧化物膜。
36.如权利要求35所述的方法，其中该第三高k介电氧化物膜由具有比该(Alx，Hf1-x)Oy层的介电常数更高的介电常数的介电膜形成。
37.如权利要求26所述的方法，其中步骤d在250℃至400℃的温度下进行。
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