CN100437541C - Method for realizing serial peripheral unit interface - Google Patents
Method for realizing serial peripheral unit interface Download PDFInfo
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- CN100437541C CN100437541C CNB2006100600792A CN200610060079A CN100437541C CN 100437541 C CN100437541 C CN 100437541C CN B2006100600792 A CNB2006100600792 A CN B2006100600792A CN 200610060079 A CN200610060079 A CN 200610060079A CN 100437541 C CN100437541 C CN 100437541C
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Abstract
The present invention relates to a multiple-working mode method for realizing serial peripheral interfaces. SPI configuration parameters are used for setting working modes of an SPI; then, data reception and transmission are carried out according to all relevant programmable parameters of synchronous serial data frames in various working modes; simultaneously, actual full-duplex synchronous serial transmission is realized. Because the working modes of SPI interfaces and all the relevant parameters of the serial data frames of the present invention all can be configured through software, the SPI interfaces realized by the method can support all current peripheral units with the SPI interfaces. SPI extended functions designed by the present invention, for example equipment enabling signal can be configured into a frame synchronous signal to make the frame synchronous signal support other common synchronous serial peripheral interfaces, widen the application range of the SPI interfaces, and the designing investment of systems on a chip is reduced.
Description
Technical field
The present invention relates to technology of serial communication, or rather, relate to a kind of implementation method of Serial Peripheral Interface (SPI).
Background technology
Serial Peripheral Interface (SPI) is mainly used to finish parallel bus interface to the data-switching between the external serial interface.Be particularly useful for configuration and control to peripheral hardware, device, the general transfer rate that requires is not high, data volume is little because this class is used.And because the SPI interface logic is simple, interface pin is few, programming is used conveniently, therefore most peripheral hardware/devices are also all supported the SPI serial line interface.
In general, SPI adopts a kind of synchronous serial communication mode of MS master-slave formula structure, and 1 main equipment can be with 1 or a plurality of slave unit.Parallel bus interface end bus is different with the parallel bus type, and the signal of serial line interface end mainly contains 4 signals:
Serial data signal: main equipment output-slave unit input;
Serial data signal: main equipment input-slave unit output;
Bit clock signal;
The slave unit enable signal.
The SPI serial data transmission is by the bit clock and the control of slave unit enable signal of main equipment.The slave unit enable signal is an effective signal of optional low level, is used to enable the I/O of the serial data of slave unit.When having only a slave unit, the slave unit enable signal on the slave unit is ground connection directly, promptly not special-purpose slave unit enable signal.At this moment, the serial communication between the bit clock signal control master/slave arrangement, that is: main equipment only produces bit clock signal when data transmit-receive.
Existing SPI interface can only can't be realized full duplex truly with half-duplex mode work.The SPI interface of a kind of embedded microcomputer shown in Figure 1 is relatively to approach a type of full duplex, and 8 bit data register of its main equipment and 8 bit data register of slave unit connect together and formed 16 bit registers of a distribution.When carrying out data transmission, 16 register moves 8 bit positions by bit clock signal, exchanging between main equipment and slave unit of data efficient: the data of writing into the data register of main equipment have sent to slave unit, and the data of writing into the slave unit data register have sent to main equipment.
Though going up, this transmission mode surface is full duplex, that is: transceive data simultaneously, but actual data transmit-receive process is controlled by main equipment fully---because determined slave unit to send the sequential of data from the generation of selecting signal and bit clock, so it is not a full duplex mode truly.And once can only connect a slave unit, Transmission bit rate also have only 8 kinds optional.When the disposable read-write between main equipment and slave unit is transmitted in addition, do not support the wait between command word and the data word, and from selecting signal transmission course, must remain effectively.Clock output can not be arranged when not having data transmission, otherwise may make mistakes.
The implementation of another kind of synchronous serial interface (SSP) has been done 3 classes to consecutive frame form branch then from existing device, sets different support characteristics at 3 kinds of different frame formats, and is as shown in the table:
| Frame format | Idle bit clock level | The efficiently sampling edge | The bit stream order | Valid data word width (unit: bit) | Single frames frame length (unit: bit) |
| Frame format 1 | 0 | Negative edge | MSB | 4～16 | 4～16 |
| Frame format 2 | 0/1 | Rising edge/negative edge | MSB | 4～16 | 4～16 |
| Frame format 3 | 0 | Rising edge | MSB | 4～16 | 13～25 |
Table 1SSP is to the support characteristic of 3 kinds of Frames
This SSP interface that designs based on type of device can be realized the frame format of part with the peripheral hardware/device of SPI interface.But do not support the data transmission of full duplex equally, and the division of frame type is also mechanical relatively.
Be not difficult to find out simultaneously, above-mentioned any interface implementation no matter, the scope of the valid data bit wide of its support is all less, and main equipment receives the data procedures complexity: except command word, also need extra junk data to produce bit clock signal and slave unit enable signal; Though frame format 3 does not need extra junk data, its command word is fixed as 8 bits, has limited its range of application greatly.
Summary of the invention
Can only be suitable for the shortcoming of particular job scope at prior art, the invention provides a kind of SPI interface implementation method of multi-operation mode, and all parameters relevant with data transmission can be disposed by CPU, enlarge the application scenario of SPI serial line interface, reduce the kind of synchronous serial interface in SOC (system on a chip) (SOC) design, thereby reduce the cost of designing and developing of SOC chip.
The mode of operation of to the effect that passing through SPI configuration settings SPI of multi-operation mode Serial Peripheral Interface (SPI) of the present invention (SPI) implementation method, carry out data transmit-receive according to the relevant all programmable parameter of synchronous serial data frame under the various mode of operations then, realize full duplex synchronous serial transmission truly simultaneously.
The implementation method of multi-operation mode Serial Peripheral Interface (SPI) (SPI) mainly comprises following step:
(1) by CPU configuration SPI configuration parameter, enables this equipment SPI;
(2) SPI determines a kind of as present mode in the multiple mode of operation according to its configuration parameter;
(3) under the work at present pattern of determining, carry out data transmit-receive according to the SPI configuration parameter.
Wherein said SPI configuration parameter comprises: the mode of operation of SPI, bit clock state, master/slave pattern, read-write indication, valid data width, sampling edge, bit stream order, clock division coefficient, peripheral hardware selections, disposable read-write sum, order that number of words, frame are continuous, latent period, waiting clock status, DMA transmit.
The mode of operation of wherein said SPI comprises following 4 kinds:
(P1) the 1st pattern (PATTERN1): master/slave pattern, sheet select pin output as the slave unit enable signal;
(P2) the 2nd pattern (PATTERN2): master/slave pattern, sheet select pin output as frame synchronizing signal;
(P3) the 3rd pattern (PATTERN3): master/holotype, sheet select pin output as the devices enable signal;
(P4) the 4th pattern (PATTERN4): master/holotype, sheet select pin output as frame synchronizing signal.
Bit clock state in the described parameter is in order to support the requirement of different peripheral to bit clock signal, make the complete control able to programme of bit clock state when not having data transmission that it comprises following 3 kinds:
(C1) state 1 (SCLK_FREE): when not having data transmit-receive, bit clock signal exists all the time;
(C2) state 2 (SCLK_HIGH): when not having data transmit-receive, bit clock signal is a high level;
(C3) state 3 (SCLK_LOW): when not having data transmit-receive, bit clock signal is a low level.
Introduced the main contents of the relevant SPI configuration of the present invention above, the process of SPI data transmit-receive has been described below,, therefore hereinafter also be referred to as the frame transmitting-receiving because data transmit-receive mainly carries out with the form of Frame.
Under the PATTERN1 pattern, the working method of SPI can only be one of master/slave, and sheet selects pin output as the slave unit enable signal, and its implementation is:
Data transmit-receive when SPI is in the main equipment working method carries out according to the following steps:
(P1a) when main equipment sends the buffer zone non-NULL, enable slave unit, the read/write indicating bit is judged;
When (P1b) indicating bit is for " reading ", send command word, receive data word after the latent period through appointment to slave unit; When indicating bit is " writing ", directly send data word;
(P1c) remove to enable the slave unit enable signal after this read/write is finished;
When SPI is in the slave unit working method, as long as the slave unit enable signal is effective, just directly receive/send out data.
Under the PATTERN2 pattern, the working method of SPI can only be one of master/slave, and sheet selects pin output as frame synchronizing signal, and its implementation is:
Only carry out data when SPI is in the main equipment working method and send, carry out according to the following steps:
(P2a) judge that main equipment sends whether non-NULL of buffer zone;
(P2b) directly send data word during non-NULL, and every begin to send a data word before the transmit frame synchronizing signal;
When being in the slave unit working method, SPI only carries out Data Receiving, as long as the frame synchronizing signal of receiving just begins to receive data.
Under the PATTERN3 pattern, the both sides of data transfer are main equipments, all can initiate the data transmit operation at any time, and its implementation is:
The data of SPI send carries out according to the following steps:
(P3a) judge sending buffer zone, during non-NULL, from wherein reading a data word;
(P3b) make the devices enable output signal effective;
(P3c) data word and string are changed and sent;
(P3c) make the devices enable output signal invalid, restart buffer state is judged.
SPI is idle or carry out data when sending, as long as the devices enable input signal is effective, just begins to receive data.
Under the PATTERN4 pattern, the both sides of data transfer are main equipments, are that with the PATTERN3 difference devices enable signal changes frame synchronizing signal into, and its implementation is:
The data of SPI send carries out according to the following steps:
(P4a) judge sending buffer zone, during non-NULL, from wherein reading a data word;
(P4b) send a frame synchronizing signal;
(P4c) data word and string are changed and sent;
(P4d) restart buffer state is judged.
SPI is idle or carry out data when sending, as long as the frame synchronizing signal of receiving just begins to receive data.
Beneficial effect of the present invention is: make the working method of SPI interface and all relevant parameters of serial data frame can pass through software arrangements, can support the peripheral hardware of at present all band SPI interfaces according to the SPI interface of the method for the invention realization; The SPI expanded function (can be configured to be frame synchronizing signal as the devices enable signal) of the present invention's design is supported the synchronous serial Peripheral Interface that other is commonly used, reduces the chip design input of SOC (system on a chip).
Description of drawings
Fig. 1 is the SPI interface synoptic diagram between two embedded microcomputers of prior art.
Fig. 2 is the workflow synoptic diagram of SPI of the present invention.
Fig. 3 is the SPI main equipment working method operating process under the PATTERN1 pattern of the present invention.
Fig. 4 is the SPI slave unit working method operating process under the PATTERN1 pattern of the present invention.
Fig. 5 is a consecutive frame timing sequence diagram of the present invention.
Fig. 6 is the SPI operating process under the PATTERN3 pattern of the present invention.
Fig. 7 is the SPI serial line interface leg signal explanation under 4 kinds of mode of operations of the present invention.
Embodiment
The invention will be further described below in conjunction with drawings and Examples.Realization of the present invention mainly is that the mode of operation of SPI mouth is selected, and to the realization of programming of the working method of each pattern, entire work process as shown in Figure 2.
Wherein, the SPI configuration parameter comprises: the mode of operation of SPI, the bit clock state programmable parameter relevant with data transmission and frame format with other, and respectively as table 2,3,4 listed.
Under the semiduplex mode, the serial data transmission activity all is to be initiated by main equipment, and slave unit is only done the passive data transmit-receive work of carrying out, and makes response (if the peripheral hardware support is talked about accordingly) according to command word information; Under full-duplex mode, there is not the branch of master/slave arrangement, promptly the receiving-transmitting sides of serial data is all as main equipment, and equipment both sides' data transmission/reception operation is independent fully.
| The mode of operation numbering | The mode of operation name | Working method is described |
| Pattern 1 | PATTERN1 | Half-duplex, sheet select pin output as the slave unit enable signal |
| Pattern 2 | PATTERN2 | Half-duplex, sheet select pin output as frame synchronizing signal |
| Mode 3 | PATTERN3 | Full duplex, sheet select pin output as the slave unit enable signal |
| Pattern 4 | PATTERN4 | Full duplex, sheet select pin output as frame synchronizing signal |
Table 2SPI mode of operation is divided
| The bit clock status number | The name of bit clock state | Bit clock is described |
| State 1 | SCLK_FREE | No matter whether carry out transceive data, bit clock signal exists all the time |
| State 2 | SCLK_HIGH | When not having data transmit-receive, bit clock signal is a high level |
| State 3 | SCLK_LOW | When not having data transmit-receive, bit clock signal is a low level |
Table 3 bit clock signal programmed settings table
| Parameter name | The pattern of effect | Parametric description |
| Master/slave pattern | PATTERN1-2 | Main equipment is controlled whole transmission course, the response that slave unit is only passive, or not response |
| The read-write indication | PATTERN1-2 | Transmission direction in the disposable data transmission |
| The valid data width | PATTERN1-4 | Valid data width in the unit, data buffer |
| The sampling edge | PATTERN1-4 | Receive the efficiently sampling edge of data |
| The bit stream order | PATTERN1-4 | High/low position in the serial data stream is sent out earlier |
| The clock division coefficient | PATTERN1-4 | The selection of transfer rate (only effective) to main equipment |
| Peripheral hardware is selected | PATTERN1-2 | The chip selection signal of 4 peripheral hardwares (only effective) to main equipment |
| Disposable read-write sum | PATTERN1-2 | The total number of the valid data of disposable read-write (only effective) to main equipment |
Other programmable parameter list of table 4
A read/write processes between SPI and peripheral hardware at first is the SPI that the SPI parameter is configured (the mode of operation parameter of wherein most importantly determining SPI) and this equipment of enabling according to the type and the job requirement of peripheral hardware by the CPU of this equipment; SPI determines self working mode according to its parameter and carry out data transmit-receive according to the parameter relevant with data transmission under this pattern afterwards.
Under each different mode of operation, the workflow of SPI is also different, below in conjunction with accompanying drawing the flow process under its different mode is illustrated.
Fig. 3 is under the PATTERN1 pattern, and SPI is operated in the schematic flow diagram under the main equipment mode." latent period " in the corresponding parameter list 4 of the cycle of the appointment in the step 307 wherein; The reception length L in the step 309 or the initial value of the transmission length T in the step 324 are determined by parameter " disposable read/write sum "; Have " frame is continuous " to judge (step 311,325) in process flow diagram, the value of " frame is continuous " is " effectively " in corresponding the parameter list.
The concrete course of work has judged whether at first that for when main equipment is idle (frame 300) data need transmission, promptly sends whether non-NULL (step 301) of buffer zone.If it is meaningful to send buffer zone, then enable corresponding slave unit (step 302), and to determine " to read " according to the read-write indicating bit still be " writing " data (step 303).Read data promptly sends the process that main equipment receives by slave unit and is: main equipment from send buffer zone read one or more as order data word and send to slave unit (step 304,305,306); Send the back and wait for the cycle (step 307) of appointment,, begin string afterwards and conversion receives data word (step 308) to give slave unit data setup times; Whether data word of every reception is zero judge (step 309) to L afterwards during reception, and makes the reception length L from subtracting (step 310), controls receiving course with this, receives until total data.Write data, promptly the process that is received by main equipment transmission slave unit is: send (step 321,322) from the transmission buffer zone sense data word warp and the conversion of going here and there, data word of every transmission sends length T from subtracting (step 323) during transmission, and whether be zero to judge (step 324) to T, control process of transmitting with this, finish until the total data transmission, remove to enable slave unit enable signal (step 326) then.Here be noted that in the block diagram 300 that the main equipment free time, meaning did not have data transmission as initial state, the devices enable signal is a disarmed state.And in the main equipment reading data course, all will reset (step 312,313) to the slave unit enable signal after each continuous Frame sends and finishes then is the needs at physical device.
Fig. 4 is under the PATTERN1 pattern, and SPI is operated in the schematic flow diagram under the slave unit mode.This example receives data for slave unit, and the situation flow process of transmission similarly.As seen, just go here and there and change and receive/send data as long as the slave unit enable signal is effective this moment.
Under this mode of operation, the SPI interface can only be one of master/slave pattern, thus the reception of serial data frame with send and can not carry out simultaneously, be i.e. half-duplex mode.The PATTERN2 pattern also is a half-duplex mode.Its working method and flow process and PATTERN1 are basic identical, and just the slave unit enable signal changes frame synchronizing signal into.Beginning all to produce a frame synchronizing signal before valid data word of reception/transmission at every turn.Corresponding frame format sequential as shown in Figure 5.Wherein data both can begin transmission at the negative edge of frame synchronizing signal, also can rise thereon along beginning transmission, respectively as Fig. 5 (a) with (b).
Fig. 6 is the SPI operating process synoptic diagram under the PATTERN3 pattern.The flow process that sends and receive with data under this pattern is respectively shown in Fig. 6 left side and right side subgraph.Because this moment, SPI worked under the full-duplex mode, the data transmit-receive both sides initiate the data transmit operation at any time, and the data transmission/reception of SPI interface is separate, does not disturb mutually.During device free (frame 600), whether SPI detects the transmission buffer zone has data to need to send (step 601), have and then therefrom read a data word (step 602), set devices enable output signal (step 603) (" set " is to instigate the devices enable output signal for effective herein), also (step 604) changed and sent to string then, making the devices enable output signal at last is invalid (step 605), gets back to initial state and finishes a transmit operation.Receive operation then by the control of devices enable input signal, during device free (frame 610), receive data word (step 612) for effectively (step 611) just gone here and there and changed in case judge this signal.Reception can be carried out simultaneously with transmission.
SPI operating process and PATTERN3 under the PATTERN4 pattern are similar, and just the devices enable signal changes frame synchronizing signal into.Beginning all to produce a frame synchronizing signal before valid data word of reception/transmission at every turn.Corresponding frame format sequential as shown in Figure 5.Wherein data both can begin transmission at the negative edge of frame synchronizing signal, also can rise thereon along beginning transmission, respectively as subgraph among Fig. 5 (a) with (b).
The leg signal of SPI pin correspondence under different mode is different, as shown in Figure 7.Wherein subgraph 7.1 corresponding PATTTERN1 patterns comprise a bit clock output signal, two data-signals and 4 slave unit enable signals in the pin at this moment.Two data-signals are respectively as data output and input, and this moment, a main equipment can be with 4 slave units.Subgraph 7.2 corresponding PATTERN2 patterns, leg signal and 7.1 similar, just the slave unit enable signal changes frame synchronizing signal into.Subgraph 7.3 corresponding PATTTERN3 patterns, leg signal comprise bit clock output, data output and devices enable output; And bit clock input, data input and devices enable input, also have one to keep pin.As seen the relevant pin of data input and output this moment is " symmetries ".Subgraph 7.4 corresponding PATTERN4 patterns, with 7.3 similar, just the devices enable signal changes frame synchronizing signal into.
In 4 kinds of mode of operations, PATTERN1 and PATTRERN2 belong to semiduplex mode, by the relevant parameters configuration, can realize following functions:
Support the valid data width of 1 ~ 32 bit;
Improve the serial data receiving efficiency of main equipment, when promptly main equipment reads the slave unit data, only need the command word data, do not need CPU additionally to produce junk data and keep bit clock signal;
When main equipment reads slave unit, support the slave unit data preparatory period of 0 ~ 3 bit;
Support 1 ~ 128 valid data word of disposable read-write, i.e. the longest 128 * 32 bits that reach of single frames data;
When the SPI main equipment did not have data transmit-receive, bit clock signal was controlled fully, has reduced error probability.
PATTERN3 and PATTRERN4 belong to full-duplex mode, and the various functions under above-mentioned semiduplex mode, serial data transmission both sides are as main equipment, and the serial data that all can independently carry out sends, receives.
Claims (8)
1. the implementation method of a Serial Peripheral Interface (SPI) is characterized in that, may further comprise the steps:
(1) configuration parameter of CPU configuration Serial Peripheral Interface (SPI) enables this equipment Serial Peripheral Interface (SPI);
(2) Serial Peripheral Interface (SPI) is determined a kind of for present mode in the multiple mode of operation according to its configuration parameter;
(3) under the work at present pattern of determining, carry out data transmit-receive according to the Serial Peripheral Interface (SPI) configuration parameter.
2. method according to claim 1, it is characterized in that Serial Peripheral Interface (SPI) configuration comprises following parameter: the mode of operation of Serial Peripheral Interface (SPI), bit clock state, master/slave pattern, read-write indication, valid data width, sampling edge, bit stream order, clock division coefficient, peripheral hardware selections, disposable read-write sum, order that number of words, frame are continuous, latent period, waiting clock status, DMA transmit.
3. method according to claim 2 is characterized in that, the bit clock signal when the bit clock state in the described parameter refers to not have data transmit-receive comprises: when not having data transmit-receive, and first state that bit clock signal exists all the time; When not having data transmit-receive, bit clock signal is second state of high level; And when not having data transmit-receive, bit clock signal is the low level third state.
4. according to claim 1 or 2 or 3 described methods, it is characterized in that the mode of operation of Serial Peripheral Interface (SPI) comprises: under the master/slave pattern, sheet selects first pattern of pin output as the slave unit enable signal; Under the master/slave pattern, sheet selects second pattern of pin output as frame synchronizing signal; Under the master/holotype, sheet selects under the three-mode and master/holotype of pin output as the devices enable signal, and sheet selects the four-mode of pin output as frame synchronizing signal.
5. method according to claim 4 is characterized in that, under described first pattern, the data transmit-receive when Serial Peripheral Interface (SPI) is in the main equipment working method carries out according to the following steps:
(P1a) when main equipment sends the buffer zone non-NULL, enable slave unit, the read/write indicating bit is judged; When (P1b) indicating bit is for " reading ", send command word, receive data after the latent period through appointment to slave unit; When indicating bit is " writing ", directly send data;
(Plc) remove to enable the slave unit enable signal after this read/write is finished;
When Serial Peripheral Interface (SPI) is in the slave unit working method, as long as the slave unit enable signal is effective, just directly receive/send out data.
6. method according to claim 4 is characterized in that, under described second pattern, only carries out data when Serial Peripheral Interface (SPI) is in the main equipment working method and sends, and carries out according to the following steps:
(P2a) judge that main equipment sends whether non-NULL of buffer zone;
(P2b) directly send data word during non-NULL, and every begin to send a data word before the transmit frame synchronizing signal;
When being in the slave unit working method, Serial Peripheral Interface (SPI) only carries out Data Receiving, as long as the frame synchronizing signal of receiving just begins to receive data.
7. method according to claim 4 is characterized in that, under described three-mode, the data of Serial Peripheral Interface (SPI) send carries out according to the following steps:
(P3a) judge sending buffer zone, during non-NULL, from wherein reading a data word;
(P3b) make the devices enable output signal effective;
(P3c) data word and string are changed and sent;
(P3c) make the devices enable output signal invalid, restart buffer state is judged;
Serial Peripheral Interface (SPI) is idle or carry out data when sending, as long as the devices enable input signal is effective, just begins to receive data.
8. method according to claim 4 is characterized in that, under described four-mode, the data of Serial Peripheral Interface (SPI) send carries out according to the following steps:
(P4a) judge sending buffer zone, during non-NULL, from wherein reading a data word;
(P4b) send a frame synchronizing signal;
(P4c) data word and string are changed and sent;
(P4d) restart buffer state is judged;
Serial Peripheral Interface (SPI) is idle or carry out data when sending, as long as the frame synchronizing signal of receiving just begins to receive data.
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| CN105824777B (en) * | 2016-03-18 | 2019-03-08 | 烽火通信科技股份有限公司 | A kind of implementation method of spi bus in IPRAN equipment |
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| CN1851682A (en) | 2006-10-25 |
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