CN107015936A - A kind of SPISlave communication modules - Google Patents

Abstract

The invention provides a kind of SPI Slave communication modules, including for data cached 8byte FIFO, SPI_SR registers；Wherein described SPI_SR registers are provided with the RDF positions for identifying the data that whether are stored with the 8byte FIFO, for identifying whether that the TDE positions for the data for needing to send can be write into 8byte FIFO；Wherein described SPI Slave communication modules also include being used for data cached inner buffer buffer, in addition to following aux control register：Receiving register SPI_RS_NUM, transmitter register SPI_TS_NUM, asynchronous FIFO read register SPI_FIFO_RPTR, asynchronous FIFO write-in register SPI_FIFO_WPTR, and a SPI_CMD register for being used to receive the CMD orders that main side is sent, and return to the SPI_STATE registers of current SPI Slave module status.

Description

A kind of SPI Slave communication modules

Technical field

The present invention relates to electronic technology field, more particularly to a kind of SPI Slave communication modules.

Background technology

Chinese Digital audio broadcasting CDR (China Digital Radio, CDR) be after AM and FM audio broadcasting technologies it After grow up ground third generation broadcast technology, be an important component of China's broadcasting digitalization process, be broadcast Digitized developing direction, is the digital broadcast audio standard that China has independent intellectual property right.

CDR allows to transmit the digital stereophonic program of many sets or all the way surround sound program in an analog fm channel, and Preferable subjective sound quality is kept, while can match channels layering feature, using the teaching of the invention it is possible to provide the two kinds of layerings of stereo and surround sound Coding mode, so as to take into account the service range and service quality of digital frequency modulation broadcast.CDR transmission plans are directed to different operations Scene, sets three kinds of transmission modes, and one is the SFN covering for large area, and an emitter can cover tens kilometers Scope, also high-speed mobile receive, as we country high ferro, per hour more than 300 kilometers of speed received.It is also high Data rate transmission, can transmit higher data volume on frequency.

In the epoch of this fusion, network is only dissolved into, function is integrated just broader practice, so, CDR Equipment/module need badly it is a kind of it is convenient, be reliably communicatively connected to the equipment such as onboard system, television set.

The content of the invention

For attenuation factor purely capacitive present in prior art be using multiple optional electric capacity in parallel cause from From the point of view of input its input impedance can with gain it is different and different the problem of, the embodiment of the present invention proposes a kind of design more For the attenuation factor that the fixed input impedance of rational constant impedance is constant.

To achieve these goals, the embodiment of the present invention proposes a kind of SPI Slave communication modules, including for caching 8byte FIFO, SPI_SR registers of data；Wherein described SPI_SR registers, which are provided with, to be used to identify in the 8byte FIFO The RDF positions for the data that whether are stored with, the TDE for identifying whether can to write the data for needing to send into 8byte FIFO Position；Wherein described SPI Slave communication modules also include being used for data cached inner buffer buffer, in addition to following auxiliary Control register：Receiving register SPI_RS_NUM, transmitter register SPI_TS_NUM, asynchronous FIFO read register SPI_ FIFO_RPTR, asynchronous FIFO write register SPI_FIFO_WPTR, and one is used to receive the CMD orders that main side is sent SPI_CMD registers, and return to the SPI_STATE registers of current SPI Slave module status.

Wherein, the SPI Slave modules, which also have, is used to identify the RxOVRES marks with the presence or absence of data spilling is received Position, for identifying send whether FIFO and internal shift register are sky TxEMPTY flags, for identifying SPI interface Piece selects the NSSR flags of NSS signal rising edges.

Wherein, the SPI Slave modules are additionally provided with SPI_CR registers, and the SPI_CR registers, which are provided with, to be used to identify The polarity of SPI clocks and the CPOL flags of phase and CPHA flags, for identifying whether receive/send data IN_EN Flag, OUT_EN flags.

The above-mentioned technical proposal of the present invention has the beneficial effect that：A kind of SPI Slave communications are proposed in such scheme Module, communication that can be through row intermodule and equipment room imparts the CDR equipment using the SPI Slave communication module equipment With more preferable portable, function expansibility and compatibility.In addition, the present invention can be also used for digital television chip and be System.

Brief description of the drawings

Fig. 1 is the structural representation of the Slave SPI modules of the embodiment of the present invention；

The workflow schematic diagram that Fig. 2 a and Fig. 2 b are Shift Register in Fig. 1.

Embodiment

To make the technical problem to be solved in the present invention, technical scheme and advantage clearer, below in conjunction with accompanying drawing and tool Body embodiment is described in detail.

Serial Peripheral Interface SPI (Serial Peripheral Interface) is developed by motorola inc A low cost, the interface that easily uses, be mainly used in the connection between microcontroller and peripheral chip.SPI interface can For connection memory, A/D converter, D/A converter, real-time clock/calendar, audio chip, lcd driver, sensor Deng.SPI is 4 line interfaces, main to use 4 signals：Main frame output/slave input (MOSI), main frame input/slave output (MISO), serial SCLK or SCK, peripheral hardware piece choosing (CS).MOSI signals are produced by main frame, and slave is received, and the signal is used for serial Input (SI) or serial date transfer (SDI).MISO signals are produced by slave, but produced under the control of main frame, the letter Number be used for Serial output (SO) or serial data output (SDO).SPI is a synchronous protocol interface, all transmission all referring to One common clock, this synchronizing clock signals are produced by main frame, and the peripheral hardware (slave unit) for receiving data is come pair using clock The reception of serial bit stream enters to synchronize.Multiple chips with SPI interface can be connected to the same SPI interface of main frame On, main frame selects to receive the slave unit of data by controlling the chip select input pin of slave unit.

The structures of the Slave SPI modules of the embodiment of the present invention is as shown in Figure 1, including：Clock unit SPCK, piece menu First NSS, module enabling unit SPIEN；Wherein clock unit SPCK, piece menu member NSS, module enabling unit SPIEN are produced together Raw module internal clock SPI Clock；Also include command status register SPI_CSR0, receive data register SPI_RDR, hair Send data register SPI_TDR；

Also include shift register Shift Register, wherein shift register Shift Register connect life respectively Make status register SPI_CSR0 and receive data register SPI_RDR, and its least significant bit LSB connections receive data-signal MOSI, and highest significant position MSB linkup transmit data-signals MISO；

Wherein command status register SPI_CSR0 includes setting shift register to move digit BITS, clock phase control NCPHA, clock polarity control CPOL；Wherein receiving data register SPI_RDR includes receiving data bit RD, is also connected with receiving number According to storage FIFO RDRF, receive overflow register OVRES；Wherein transmitting data register SPI_TDR includes sending data bit TD, and it is also connected with sending data in empty TDRE.

The signal that Fig. 1 is related to is described as follows shown in table：

And the interface signal of SPI Slave modules is as follows,

In the embodiment of the present invention, SPI Slave modes are controlled and transmitted data using AHB interface.

After SPI serial ports receives data, it will be cached in the 8byte FIFO of inside modules.Now, if in setting Disconnected enable bit RDF_EN=1, INTR_EN=1, will produce interrupt signal, informs CPU to capture data；If in being not provided with RDF positions that are disconnected to enable, then needing CPU to inquire about in SPI_SR registers, to know whether to receive data.CPU reads SPI_SR Afterwards, if RDF=1, show there are the data received in 8Byte FIFO, subsequent CPU can be read back the number by ahb bus According to.

When being sent out data by SPI interface, CPU can set TDE_EN=1, INTR_EN=1 to produce transmission Interrupt signal.Regardless of whether receiving interrupt signal, CPU, which can be inquired about, obtains TDE in SPI_SR registers, to know whether The data sent can be write to the 8Byte FIFO of inside modules.If 8byte, which sends FIFO memory, data, SPI Slave

Module will send data therein after SPI interface NSS chip selection signals are effective to Master, otherwise send " 0 ".

SPI Slave modules also have the mode bits such as RxOVRES, TxEMPTY, NSSR, are used to refer to current whether there is and " connect The state such as receipts data spilling ", " it is sky to send FIFO and internal shift register ", " SPI interface piece selects NSS signals rising edge ", And have respective interrupt enable bit to control whether to produce interrupt signal.

CPOL and CPHA in SPI Slave module SPI_CR registers are used for selecting the polarity and phase of SPI clocks： IN_EN, OUT_EN are for choosing whether to receive, sending data, (as IN_EN=0,8Byte, which receives FIFO, will not deposit SPI The data that MaSter is sent；As OUT_EN=0,8byte sends FIFO and will not send out the data wherein deposited, SPI MISO signal wires will be always for 0).

In order to improve the ease for use of SPI slave interfaces, internal damping buffer is added, for data cached, and phase That answers adds aux control register：SPI_RS_NUM、SPI_TS_NUM、SPI_FIFO_RPTR、SPI_FIFO_WPTR.Volume Two eight bit registers of outer increase, the SPI_CMD for receiving the CMD orders that Master ends are sent, and return current The SPI_STATE of Slave module status.Its application method is shown in Fig. 2 a and Fig. 2 b.Shift Regiseter part-structures such as Fig. 2 Shown.

Following table defines the abbreviation that Fig. 2 a and Fig. 2 b are related to：

Wherein, the CDR terminals/module major function include CDR frequencies code stream and FM frequencies reception and demodulating and decoding with And the broadcasting of CDR and FM programs, as during terminal also include MP3 and WMA audios play, system set etc. function.CDR terminals are set When standby/module is as slave unit, communicated using SPI Slave modes with main equipment through row, the control of main equipment transmission can be received System order control CDR and FM broadcasting, the voice data that can also be transmitted by slave unit after demodulation is delivered to main equipment and played.Wherein The SPI Slave modes are according to the above structure and operation principle design；SPI Slave modes are to use SPI interface, relevant interface is explained in detail made above.It is all to use same interface or using replacing title but function Identical interface, is accordingly to be regarded as in the protection domain of the application in scope.Increase or delete useless default interface but primary interface Consistent, it is accordingly to be regarded as in the protection domain of the application in scope.The SPI Slave module communications methods can be applied in flat board There are audio frequency and video to receive in the equipment and system played for computer, mobile phone, television set, onboard system etc., but be not limited to this.It is all It is accordingly to be regarded as according to the technology application for using for reference invention content in the application protection domain.What the embodiment of the present invention was proposed SPI Slave modules, its means of communication include but is not limited to CDR equipment/module as during slave unit with main equipment communicate, other Equipment is transmitted using which through row principal and subordinate data-/ command.It is also considered as in the application protection domain.

Described above is the preferred embodiment of the present invention, it is noted that for those skilled in the art For, on the premise of principle of the present invention is not departed from, some improvements and modifications can also be made, these improvements and modifications It should be regarded as protection scope of the present invention.

Claims (3)

1. a kind of SPI Slave communication modules, it is characterised in that including being posted for data cached 8byte FIFO, SPI_SR Storage；Wherein described SPI_SR registers be provided be used for identify the data that whether are stored with the 8byte FIFO RDF positions, be used for Identify whether that the TDE positions for the data for needing to send can be write into 8byte FIFO；Wherein described SPI Slave communication modules Also include being used for data cached inner buffer buffer, in addition to following aux control register：Receiving register SPI_RS_ NUM, transmitter register SPI_TS_NUM, asynchronous FIFO read register SPI_FIFO_RPTR, asynchronous FIFO write-in register SPI_FIFO_WPTR, and a SPI_CMD register for being used to receive the CMD orders that main side is sent, and return current The SPI_STATE registers of SPI Slave module status.

2. SPI Slave communication modules according to claim 1, it is characterised in that the SPI Slave modules are also useful It whether there is the RxOVRES flags for receiving data spilling, for identifying transmission FIFO and internal displacement deposit in identifying Whether device is sky TxEMPTY flags, the NSSR flags of NSS signal rising edges is selected for identifying SPI interface piece.

3. SPI Slave communication modules according to claim 1, it is characterised in that the SPI Slave modules are additionally provided with SPI_CR registers, the SPI_CR registers be provided be used for identify SPI clocks polarity and phase CPOL flags and CPHA flags, for identifying whether receive/send data IN_EN flags, OUT_EN flags.