CN201063161Y - Primary device for serial peripheral interface - Google Patents
Primary device for serial peripheral interface Download PDFInfo
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- CN201063161Y CN201063161Y CNU2007201541683U CN200720154168U CN201063161Y CN 201063161 Y CN201063161 Y CN 201063161Y CN U2007201541683 U CNU2007201541683 U CN U2007201541683U CN 200720154168 U CN200720154168 U CN 200720154168U CN 201063161 Y CN201063161 Y CN 201063161Y
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Abstract
The utility model relates to main equipment with serial peripheral interface, aiming at connection with a subordinate equipment to transmit data, which comprises a register group, a shift register and a control unit. The register group is used for storage and control of data transmitted from serial peripheral interface; the shift register is employed to input or output from the serial peripheral interface main equipment; the control unit is adopted to judge that whether the subordinate equipment connected with the serial peripheral interface is a serial peripheral interface memory or a traditional serial peripheral interface equipment according to equipment identification signals. The subordinate equipment is traditional serial peripheral interface equipment; according to poke parameter of the register group and the data control shift register, the same time as data output from the serial peripheral interface main equipment, the control unit receives data output from the traditional serial peripheral interface equipment.
Description
Technical field
The utility model relates to a kind of equipment of control data transmission, relates in particular to a kind of serial peripheral interface main equipment.
Background technology
Computer system often need connect multiple peripherals, yet the specification of each peripherals or different to some extent, for controlling multiple different peripherals, need there be an interface to manage data transmission between peripherals and computer system between two parties, wherein than dust head such as serial peripheral interface (Serial Peripheral interface, SPI).Compared to other transmission standard, SPI has preferable transfer efficiency, can support the full duplex data communication mode, and more easily realizes.SPI is mainly used in EEPROM, FLASH, and AD converter also has between digital signal processor and the digital signal code translator.
The SPI interface is with master-slave mode work, this pattern has a main equipment and one or more slave unit usually, its interface comprises following four kinds of signals: clock signal (SCK), main go out/from going into signal (Master Output/Slave Input, MOSI), lead/from going out signal (Master Input/Slave Output, MISO) with slave unit select signal (Slave Select, SS).Wherein, clock signal SCK is provided and is sent to slave unit by main equipment.Lead/go into from going into signal MOSI and master/from going out signal MISO then finishes data based on this clock signal SCK transmitted in both directions.Data see through mainly to go out/export slave unit from going into signal MOSI line to by main equipment, and data change when clock signal SCK upper edge or lower edge, are read in back to back lower edge or upper edge, and same principle is also used in input.Like this, in the change of at least 8 clock signals (upper edge and lower edge for once), just can finish the transmission of 8 bit data.Slave unit selects signal SS is whether the control slave unit is selected, that is to say when having only slave unit to select signal SS to be the enable signal of predesignating (noble potential or electronegative potential), and is just effective to the operation of this slave unit.This just allows to connect a plurality of SPI equipment on same bus become possibility.
SPI is generally used for connecting internal memory, and as flash memory (Flash ROM), Electrically Erasable Read Only Memory (EEPROM) etc., so the specification that the data transmission polygamy of its SPI main equipment closes internal memory designs.Figure 1 shows that serial peripheral interface (SPI) main equipment of prior art and the synoptic diagram that a SPI internal memory that serves as the SPI slave unit carries out data transmission.SPI main equipment 210 and SPI internal memory 220 respectively comprise a shift register 216,226 and a data buffer 215,225.SPI main equipment 210 also comprises a control module 217, and it is exported a slave unit and selects the transmission of the steering logic 227 of a signal SS and clock signal SCK to a SPI internal memory 220 with control data.(First In First Out, FIFO) impact damper are stored the data that SPI main equipment 210 and SPI internal memory 220 will send and the data of reception respectively for first in first out for data buffer 215,225.Usually, the data of data buffer 225 receptions of SPI internal memory 220 can write the main memory (main memory) of SPI internal memory 220 after finishing data transmission.Shift register 216,226 respectively according to clock signal SCK with the data that the receive output that moves to left or move to right.
Figure 2 shows that the sequential chart of SPI main equipment 210 from SPI internal memory 220 reading of data.As shown in Figure 2, when SPI main equipment 210 needed reading of data, control module 217 can at first drag down slave unit and select signal SS, and input operation command byte in regular turn and address byte are given data buffer 215 then.Shift register 216 goes out command byte and address byte/move into the shift register 226 from going into signal wire MOSI by the master under the control of clock signal SCK.At this moment, mainly go into/be high-impedance state from going out signal MISO.The steering logic 227 of SPI internal memory 220 starts immediately, and exports corresponding data according to the instruction and the address that receive, these data under the control of clock signal SCK by shift register 226 by mainly go into/move into shift register 216 from going out signal MISO.By above-mentioned description as can be known, only carry out unidirectional data transmission between SPI main equipment 210 and the SPI internal memory 220.Yet SPI main equipment 210 all needs to be connected to carry out exchanges data with conventional SPI slave unit in more applications.In this case, the deviser must design the SPI main equipment that goes for bidirectional data transfers in addition, the data of sending with the conventional SPI equipment of normal reception.
The utility model content
The purpose of this utility model is to provide a kind of serial peripheral interface main equipment, and it not only can connect with the serial peripheral interface internal memory, can also be connected with serial peripheral interface equipment to carry out exchanges data.
The utility model provides a kind of serial peripheral interface main equipment, and in order to be connected with a slave to carry out data transmission, described serial peripheral interface main equipment comprises: a registers group, storage control serial peripheral interface transmission parameters and data; One shift register is in order to move into or to shift out described serial peripheral interface main equipment with data; And a control module, judge that according to a recognition of devices signal slave that described serial peripheral interface main equipment is connected is a serial peripheral interface internal memory or a conventional serial peripheral interface equipment.If described slave is conventional serial peripheral interface equipment, described control module receives the data that described conventional serial peripheral interface equipment is sent according to the parameter and the Data Control shift register of described registers group poke when data being shifted out described serial peripheral interface main equipment.
Serial peripheral interface main equipment described in the utility model is provided with one first port and one second port, and described registers group comprises a control register, it defines a port and selects the position, in order to indicate described serial peripheral interface main equipment is to connect by described first port or by described second port and slave, wherein, when port is selected the position activation, indicating described serial peripheral interface main equipment is connected with described slave by first port, when port selects the position to lose efficacy, indicate serial peripheral interface main equipment and be connected with described slave by second port.
Serial peripheral interface main equipment described in the utility model, when described serial peripheral interface main equipment was connected with described slave by first port, described control module judged that according to described recognition of devices signal described slave is a serial peripheral interface internal memory or a conventional serial peripheral interface equipment.
Serial peripheral interface main equipment described in the utility model, when described serial peripheral interface main equipment was connected with described slave by second port, described control module thought that described slave is a conventional serial peripheral interface equipment.
Serial peripheral interface main equipment described in the utility model, described shift register comprises: one receives shift register, receives the data of slave output and moves into described registers group; And an Output Shift Register, the data in the registers group are shifted out described serial peripheral interface main equipment.
Serial peripheral interface main equipment described in the utility model, described registers group also comprises: a status register, the state parameter of storage serial peripheral interface transmission; One data buffer, the temporary data that will send shift register to reach the data that receive from shift register; One order register, the instruction of storage serial peripheral interface transmission data; And an address register, the address of storage serial peripheral interface transmission data.
Serial peripheral interface main equipment described in the utility model also is provided with a buffer between described shift register and the described data buffer.
Serial peripheral interface main equipment described in the utility model, described control register define a frequency division position, and described control module changes the frequency of serial peripheral interface transmission according to the value of described frequency division position.
The utility model provides a kind of serial peripheral interface main equipment, and in order to be connected with a slave to carry out data transmission, described serial peripheral interface main equipment comprises: a control register, storage control serial peripheral interface transmission parameters and data; One shift register is in order to move into or to shift out described serial peripheral interface main equipment with data; And a control module, judge that according to a recognition of devices signal slave that described serial peripheral interface main equipment is connected is a serial peripheral interface internal memory or a GPS receiver.If described slave is a GPS receiver, described control module receives the data that described GPS receiver is sent according to stored parameters in the control register and Data Control shift register when data being shifted out described serial peripheral interface main equipment.
Serial peripheral interface main equipment described in the utility model, when the slave that is connected when described serial peripheral interface main equipment was a GPS receiver, described control module was the parameter information that is used to dispose described GPS receiver by the data of shift register output.
Owing to before serial peripheral interface main equipment of the present utility model carrying out data transmission, can select position and recognition of devices signal to judge the type of the slave of its connection by port, and the transmission that comes control data according to judged result, thereby can compatiblely support multiple slave.
Serial peripheral interface main equipment described in the utility model can solve the SPI main equipment that can support the SPI internal memory in the prior art is connected possibility lost data when carrying out data transmission with conventional SPI equipment problem, and realizes easily.
Description of drawings
Fig. 1 is the synoptic diagram that conventional serial peripheral interface main equipment is connected with the serial peripheral interface internal memory.
Sequential chart when Fig. 2 carries out data transmission for conventional serial peripheral interface main equipment shown in Figure 1.
Fig. 3 is the synoptic diagram that the utility model serial peripheral interface main equipment is connected with slave unit.
Sequential chart when Fig. 4 carries out data transmission for the utility model serial peripheral interface main equipment shown in Figure 3.
Embodiment
By the description of carrying out below in conjunction with the accompanying drawing that an example exemplarily is shown, above-mentioned and other purposes of the present utility model and characteristics will become apparent.
The utility model provides a kind of SPI main equipment, and as shown in Figure 3, the one end is connected with a microprocessor 800, and the other end can connect to carry out unidirectional or two-way data transmission with a SPI slave unit.Further, SPI main equipment 40 of the present utility model can be judged the type of SPI slave unit before the log-on data transmission, and adjusts Data Transport Protocol according to judged result.
See also Fig. 3, in present embodiment, SPI main equipment 40 has 5 control signal wires: clock cable (SCK), main go out/from going into signal wire (Master Output/SlaveInput, MOSI), main go into/from go out signal (Master Input/Slave Output, MISO) and effective first slave unit of low level select signal wire (Slave Select) SS_1 and second slave unit to select signal wire SS_2.For convenience of description, suppose that present embodiment SPI main equipment 40 can be connected with two slave units, thereby SPI main equipment 40 is provided with 2 slave units and selects signal wires, yet, select signal wire if increase slave unit, can connect a plurality of slave units.In present embodiment, first slave unit selects first port of signal wire SS_1 correspondence to couple with SPI internal memory 50 or conventional SPI equipment 60, second slave unit selects second port of signal wire correspondence then can only couple with conventional SPI equipment 60, promptly when second slave unit was selected signal wire SS_2 activation, the slave unit that SPI main equipment 40 is connected was defaulted as conventional SPI equipment 60.
The SPI main equipment 40 of present embodiment comprises a control module 41, a registers group 42 and a shift register 43.Control module 41 can be realized by a state machine, is used for the data transmission between treatment S PI main equipment 40 and SPI internal memory 50 or the conventional SPI equipment 60.The registers group 42 of present embodiment comprises a data buffer 420, a status register 422, an address register 424, an order register 426 and a control register 428.Data buffer 420 can buffer memory moves into the data of SPI main equipments 40 by shift register 43, also can buffer memory be about to the data that shifted out by SPI main equipment 40.In data buffer 420, data are arranged, or have data by main go into/when going out signal wire MISO input, control module 41 starts shift registers 43, makes shift register 43 moving to left or moving to right one one of data under the control of clock signal SCK.In the present embodiment, shift register 43 receives shift register 432 by one and an Output Shift Register 430 is formed, be respectively applied for data are moved into SPI main equipment 40 and data are shifted out SPI main equipment 40, and the size that receives shift register 432 and Output Shift Register 430 all is 8 (bit).
Usually, before starting the SPI data transmission, the parameters of microprocessor 800 meeting groups of configuration registers 42 is so that the control module 41 of SPI main equipment 40 starts the SPI data transmission according to stored parameters in the registers group 42.Specifically, status register 422 store status parameters, as frequency finish, frequency carry out medium, to represent the transmission state of this frequency period.The appropriate address of address register 424 storage data in internal memory.Order register 426 storage SPI main equipments 40 carry out the instruction of which kind of operation, for example read the data of SPI internal memory 50 storages etc.Whether control register 428 stores controlled variable, as transmission frequency, data length, instruction pointer and frequency startup etc., have data to need transmission, data length to begin transmission etc. why, when to set this frequency period.Especially, the control register 428 of present embodiment is provided with a port and selects position 4280.Because hypothesis SPI main equipment 40 only is provided with two slave connectivity ports in the present embodiment, promptly first slave unit is selected first port of signal SS_1 correspondence, second slave unit is selected second port of signal SS_2 correspondence, so control register 428 has only a port to select position 4280.Suppose that herein it is that port is selected the value of position 4280 at 1 o'clock, first slave unit is selected signal wire SS_1 activation.Control register 428 also defines a frequency division position (ClockDivider Bit) 4281, so that control module 41 changes the frequency of the clock signal SCK of its output according to the value of frequency division position 4281, thereby reaches the purpose that changes data rate.
Please continue to consult Fig. 3, SPI internal memory 50 and conventional SPI equipment 60 comprise a shift register 51,61, a data buffer 52,62 and a steering logic 53,63 respectively.In addition, conventional SPI equipment 60 is equipped with clock signal pin SCK, data input pin SDI, data output pin SDO with SPI internal memory 50, go out with clock cable SCK, the master of SPI main equipment 40 respectively/from going into signal wire MOSI, leading/be connected from going out signal wire MISO.In present embodiment, first slave unit of SPI main equipment 40 selects signal wire SS_1 to be connected with the Enable Pin CS of SPI internal memory 50, and second slave unit selects signal wire SS_2 to be connected with the Enable Pin CS of conventional SPI equipment 60.
Below will describe the type how the SPI main equipment judges the SPI slave unit, and adjust Data Transport Protocol according to judged result.
Please consult Fig. 3 once more, suppose that microprocessor 800 or miscellaneous equipment want to read the data of SPI internal memory 50 storages, microprocessor 800 or special software can dispose control register 428, status register 422, address register 424 and the order register 426 of SPI main equipment 40.After register configuration was finished, control module 41 read the value of each parameter in the registers group 42, and selected the value of position 4280 to judge activation first slave unit selection signal wire SS_1 or second slave unit selection signal wire SS_2 according to port.For instance, because microprocessor 800 need read the data of SPI internal memory 50, port selects the value of position 4280 can be made as 1 when configuration, thereby control module 41 can know that SPI main equipment 40 needs to select signal SS_1 to be connected with slave unit by first slave unit.At this moment, control module 41 need be judged the model of the slave unit that first slave unit selection signal wire SS_1 is connected according to a recognition of devices signal DEVICE_TYPE.When supposing recognition of devices signal DEVICE_TYPE for " 0 ", the slave unit that expression is connected is conventional SPI equipment 60, and when recognition of devices signal DEVICE_TYPE was drawn high to " 1 ", the slave unit that expression is connected was a SPI internal memory 50.The value of recognition of devices signal DEVICE_TYPE is to control by a peripheral hardware pin, be changed to " 1 " in advance by chip production producer usually, and the user also can be changed to " 0 with it by the mode of wire jumper." in present embodiment; suppose that the recognition of devices signal DEVICE_TYPE that SPI main equipment 40 receives is changed to " 1 "; thus control module 41 can to judge the slave unit that is connected according to recognition of devices signal DEVICE_TYPE be SPI internal memory 50, and select the Enable Pin CS of signal wire SS_1 activation SPI internal memory 50 to transmit with log-on data by first slave unit.At this moment, control module 41 is according to parameter information activation one control signal 410 that reads, and sends operational order in the order register 426 and address register 424 address stored to Output Shift Register 430 in regular turn according to stored parameters in the control register 428.Output Shift Register 430 under the control of clock signal SCK and control signal 410, will instruct with a position, address by main go out/move into the shift register 51 of SPI internal memory 50 from going into signal wire MOSI.Like this, the steering logic 53 of SPI internal memory 50 can be passed through data buffer 52 reading command and address, and the pairing data in this address are put into data buffer 52, is moved out to the reception shift register 432 of SPI main equipment 40 by shift register 51 orders.The reception shift register 432 of SPI main equipment 40 deposits the data that receive in data buffer 420 subsequently one by one.Wait to receive after data that shift register 432 sends SPI internal memory 50 all receive, control module 41 makes first slave unit select signal SS_1 to lose efficacy, microprocessor 800 can be in data buffer 420 reading of data.
On the other hand, suppose SPI main equipment 40 need with conventional SPI devices exchange data.Similarly, before beginning SPI transmission, the parameter of the first configuration control register 428 of microprocessor 800 meetings, status register 422, address register 424 and order register 426, but parameter value can be slightly different, to adapt to the specification of concrete conventional SPI equipment.The data that microprocessor 800 also can transmit needs be written in the data buffer 420 of SPI main equipment 40 according to the order of sequence for transmission.At this moment, port selects the value of position 4280 to be made as 0 by microprocessor 800, so that control module 41 activations second slave unit is selected signal SS_2.As previously mentioned, second slave unit selects pairing second port of signal SS_2 only to support conventional SPI equipment, thereby when second slave unit was selected signal SS_2 activation, the slave unit that control module 41 can be given tacit consent to 40 connections of SPI main equipment was conventional SPI equipment 60.Need to prove that when port selected the value of position 4280 to be 0, the value of recognition of devices signal DEVICE_TYPE can not exert an influence to control module 41.Thereby control module 41 can select the Enable Pin CS of the conventional SPI equipment 60 of signal wire SS_2 activation to transmit with log-on data by second slave unit.Because all data that need transmit pre-deposit data buffer 420 by microprocessor 800, control module 41 will be ignored the parameter information in the address register 424 and instruction registers 426, only come control data transmission according to the parameter value in control register 428 and the status register 422.
As shown in Figure 3, Figure 4, when the type of slave unit is conventional SPI equipment 60, select signal SS_2 and control signal 410 at control module 41 activations second slave unit, Output Shift Register 430 sees through the data data buffer 420 under the control of control signal 410 immediately and leads/export the shift register 61 of conventional SPI equipment 60 to from going into signal wire MOSI.Meanwhile, conventional SPI equipment 60 be stored in data in the data buffer 62 see through mainly to go into by shift register 61/from going out the reception shift register 432 that signal wire MISO transfers to SPI main equipment 40, and be stored in regular turn in the data buffer 420.Because shift register 43 is made up of separate reception shift register 432 and Output Shift Register 430, thus shift register 43 when data are shifted out SPI main equipment 40 also can with independently go into/from going out the data immigration SPI main equipment 40 that signal wire MISO receives.Obviously, different with SPI internal memory 50, conventional SPI equipment 60 not necessarily must the ability output data be given the SPI main equipment after receiving instruction and address, but can give SPI main equipment 40 according to predefined host-host protocol (by the transmission parameter decision) output data in the data that reception SPI main equipment 40 transmits, promptly SPI main equipment 40 can carry out bidirectional data transfers with conventional SPI equipment 60.When SPI main equipment 40 transmits with conventional SPI equipment 60 according to agreement can be diversified, for example, can be defined in SPI main equipment 40 is invalid in two bytes that begin to receive most, thereby microprocessor 800 can directly read active data from the 3rd byte, and this host-host protocol can be set by software programming also can be by microprocessor 800 pre-configured finishing.
For instance, the conventional SPI equipment 60 in the present embodiment can be a GPS (GPS) receiver (Receiver), is used for the geographical location information that in real time it received, as longitude, and latitude, passback such as sea level elevation handles for microprocessor 800.Please in conjunction with shown in Figure 4, SPI main equipment 40 is when receiving the data of GPS receiver transmission, can go out by the master/give the GPS receiver from going into signal MOSI transmission parameter configuration data, for example, the GPS receiver is configured to send in real time data, and the data of transmission comprise date, system time, gps satellite number, longitude and latitude etc.After the GPS receiver was finished the SPI data transmission, microprocessor 800 extracted active data and handles and get final product in SPI main equipment 40.
As is known to the person skilled in the art, the host-host protocol between SPI main equipment and the SPI slave unit, promptly transfer instruction, address, data are realized by microprocessor 800 direct configuration data buffers 420.Data buffer 420, shift register 43 only are responsible for temporary various transmission contents, and do not distinguish the kind of transmission content.The parameters that address register 424 and instruction registers 426 are stored only is used for clearly informing that SPI internal memory 50 need read or write data, and the correspondence memory address of data, do not need and the direct communicate information of the equipment that is connected, thereby for the user, any SPI equipment all can see through SPI interface transmission data, is not subject to specification.In addition, if need the transmission lot of data, can between shift register 43 and data buffer 42, set up a buffer, for example one 8 first in first out (First In First Out, FIFO) impact damper is to avoid the transmitted in both directions of factor affecting data such as time delay.
Sum up and opinion, can solve the SPI main equipment that can support the SPI internal memory in the prior art is connected possibility lost data when carrying out data transmission with conventional SPI equipment problem by SPI main equipment of the present utility model, and realize easily.
The above only is the utility model preferred embodiment; so it is not in order to limit scope of the present utility model; any personnel that are familiar with this technology; in not breaking away from spirit and scope of the present utility model; can do further improvement and variation on this basis, so the scope that claims were defined that protection domain of the present utility model is worked as with the application is as the criterion.
Claims (10)
1. a serial peripheral interface main equipment in order to be connected to carry out data transmission with a slave, is characterized in that, described serial peripheral interface main equipment comprises:
One registers group, storage control serial peripheral interface transmission parameters and data;
One shift register is in order to move into or to shift out described serial peripheral interface main equipment with data; And
One control module, judge that according to a recognition of devices signal slave that described serial peripheral interface main equipment is connected is a serial peripheral interface internal memory or a conventional serial peripheral interface equipment, if described slave is conventional serial peripheral interface equipment, described control module receives the data that described conventional serial peripheral interface equipment is sent according to stored parameters in the described registers group and Data Control shift register when data being shifted out described serial peripheral interface main equipment.
2. serial peripheral interface main equipment according to claim 1, it is characterized in that, described serial peripheral interface main equipment is provided with one first port and one second port, and described registers group comprises a control register, it defines a port and selects the position, in order to indicate described serial peripheral interface main equipment is to connect by described first port or by described second port and slave, wherein, when port is selected the position activation, indicating described serial peripheral interface main equipment is connected with described slave by first port, when port selects the position to lose efficacy, indicate serial peripheral interface main equipment and be connected with described slave by second port.
3. serial peripheral interface main equipment according to claim 2, it is characterized in that, when described serial peripheral interface main equipment was connected with described slave by first port, described control module judged that according to described recognition of devices signal described slave is a serial peripheral interface internal memory or a conventional serial peripheral interface equipment.
4. serial peripheral interface main equipment according to claim 2, it is characterized in that, when described serial peripheral interface main equipment was connected with described slave by second port, described control module thought that described slave is a conventional serial peripheral interface equipment.
5. serial peripheral interface main equipment according to claim 1 is characterized in that, described shift register comprises:
One receives shift register, receives the data of slave output and moves into described registers group; And
One Output Shift Register shifts out described serial peripheral interface main equipment with the data in the registers group.
6. serial peripheral interface main equipment according to claim 1 is characterized in that, described registers group also comprises:
One status register, the state parameter of storage serial peripheral interface transmission;
One data buffer, the temporary data that will send shift register to reach the data that receive from shift register;
One order register, the instruction of storage serial peripheral interface transmission data; And
One address register, the address of storage serial peripheral interface transmission data.
7. serial peripheral interface main equipment according to claim 6 is characterized in that, also is provided with a buffer between described shift register and the described data buffer.
8. serial peripheral interface main equipment according to claim 1 is characterized in that, described control register defines a frequency division position, and described control module changes the frequency of serial peripheral interface transmission according to the value of described frequency division position.
9. a serial peripheral interface main equipment in order to be connected to carry out data transmission with a slave, is characterized in that, described serial peripheral interface main equipment comprises:
One control register, storage control serial peripheral interface transmission parameters and data;
One shift register is in order to move into or to shift out described serial peripheral interface main equipment with data; And
One control module, judge that according to a recognition of devices signal slave that described serial peripheral interface main equipment is connected is a serial peripheral interface internal memory or a GPS receiver, if described slave is a GPS receiver, described control module receives the data that described GPS receiver is sent according to stored parameters in the control register and Data Control shift register when data being shifted out described serial peripheral interface main equipment.
10. serial peripheral interface main equipment according to claim 9, it is characterized in that, when the slave that is connected when described serial peripheral interface main equipment was a GPS receiver, described control module was the parameter information that is used to dispose described GPS receiver by the data of shift register output.
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| CNU2007201541683U CN201063161Y (en) | 2007-06-08 | 2007-06-08 | Primary device for serial peripheral interface |
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| CNU2007201541683U CN201063161Y (en) | 2007-06-08 | 2007-06-08 | Primary device for serial peripheral interface |
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| CN101324873B (en) * | 2008-07-08 | 2010-04-21 | 锐迪科微电子（上海）有限公司 | Compatible type non-standard bit wide serial perimeter interface and data transmission method among interfaces |
| CN102270268A (en) * | 2010-12-31 | 2011-12-07 | 北京谊安医疗系统股份有限公司 | Information communication method and system, and medical equipment |
| CN102750241A (en) * | 2012-06-13 | 2012-10-24 | 中国科学院声学研究所 | Method and system for communication between upper computer and lower computer |
| CN101605081B (en) * | 2008-06-13 | 2013-12-18 | 威盛电子(中国)有限公司 | Data transmission device, data reception device and method for controlling data transmission |
| CN103838692A (en) * | 2012-11-27 | 2014-06-04 | 安凯(广州)微电子技术有限公司 | Method, main control equipment and system for reading data from digital image sensor |
| CN105718400A (en) * | 2014-12-05 | 2016-06-29 | 大陆汽车车身电子系统（芜湖）有限公司 | SPI based communication method |
| CN107015936A (en) * | 2017-03-13 | 2017-08-04 | 北京海尔集成电路设计有限公司 | A kind of SPISlave communication modules |
| CN107832250A (en) * | 2017-11-02 | 2018-03-23 | 北京中电华大电子设计有限责任公司 | A kind of master-slave communication timing method and method for reliable transmission based on SPI |
| CN109581927A (en) * | 2018-12-07 | 2019-04-05 | 庸博（厦门）电气技术有限公司 | The serial communication method and servo-driver of servo-driver |
| CN109918332A (en) * | 2019-03-14 | 2019-06-21 | 昆山龙腾光电有限公司 | SPI is from equipment and SPI equipment |
| TWI747416B (en) * | 2020-08-04 | 2021-11-21 | 新唐科技股份有限公司 | Enhanced serial peripheral interface transmission control device and method |
| CN114443524A (en) * | 2022-01-28 | 2022-05-06 | 山东云海国创云计算装备产业创新中心有限公司 | Data transmission method, system, storage medium and equipment |
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| CN101605081B (en) * | 2008-06-13 | 2013-12-18 | 威盛电子(中国)有限公司 | Data transmission device, data reception device and method for controlling data transmission |
| CN101324873B (en) * | 2008-07-08 | 2010-04-21 | 锐迪科微电子（上海）有限公司 | Compatible type non-standard bit wide serial perimeter interface and data transmission method among interfaces |
| CN102270268A (en) * | 2010-12-31 | 2011-12-07 | 北京谊安医疗系统股份有限公司 | Information communication method and system, and medical equipment |
| CN102270268B (en) * | 2010-12-31 | 2014-02-26 | 北京谊安医疗系统股份有限公司 | Information communication method and system, and medical equipment |
| CN102750241A (en) * | 2012-06-13 | 2012-10-24 | 中国科学院声学研究所 | Method and system for communication between upper computer and lower computer |
| CN103838692A (en) * | 2012-11-27 | 2014-06-04 | 安凯(广州)微电子技术有限公司 | Method, main control equipment and system for reading data from digital image sensor |
| CN105718400A (en) * | 2014-12-05 | 2016-06-29 | 大陆汽车车身电子系统（芜湖）有限公司 | SPI based communication method |
| CN107015936A (en) * | 2017-03-13 | 2017-08-04 | 北京海尔集成电路设计有限公司 | A kind of SPISlave communication modules |
| CN107832250A (en) * | 2017-11-02 | 2018-03-23 | 北京中电华大电子设计有限责任公司 | A kind of master-slave communication timing method and method for reliable transmission based on SPI |
| CN107832250B (en) * | 2017-11-02 | 2020-10-30 | 北京中电华大电子设计有限责任公司 | Master-slave communication time sequence method based on SPI |
| CN109581927A (en) * | 2018-12-07 | 2019-04-05 | 庸博（厦门）电气技术有限公司 | The serial communication method and servo-driver of servo-driver |
| CN109918332A (en) * | 2019-03-14 | 2019-06-21 | 昆山龙腾光电有限公司 | SPI is from equipment and SPI equipment |
| TWI747416B (en) * | 2020-08-04 | 2021-11-21 | 新唐科技股份有限公司 | Enhanced serial peripheral interface transmission control device and method |
| CN114443524A (en) * | 2022-01-28 | 2022-05-06 | 山东云海国创云计算装备产业创新中心有限公司 | Data transmission method, system, storage medium and equipment |
| CN114780029A (en) * | 2022-04-12 | 2022-07-22 | 荣耀终端有限公司 | Device identification method and related device |
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