TWI747416B - Enhanced serial peripheral interface transmission control device and method - Google Patents

Abstract

A transmission control device is disclosed, which includes a master device and plurality of slave devices. The master device includes a first serial peripheral interface, and each slave device includes at least a second serial peripheral interface, a frequency counter, and a register. The second selection signal terminal of each second serial peripheral interface is connected to the first selection signal terminal of the first serial peripheral interface and it has at least one common node. Each slave device receives a device identification signal transmitted by the master device, and its frequency counter analyzes whether the device identification signal is the device frequency set by the register.

Description

Enhanced serial peripheral interface transmission control device and method

The present invention relates to a transmission control device and method, in particular to an enhanced serial peripheral interface transmission control device and method.

The conventional serial peripheral interface (SPI) consists of the serial clock (SCLK) terminal, the master output slave input (MOSI) terminal, and the master input slave output (MISO) terminal. ) Terminal and select signal (slave selected, SS) terminal, and when a master device (master device) in a transmission control device is connected to a slave device (slave device) through a serial peripheral interface for data transmission , Each needs a selection signal terminal for one-to-one correspondence.

It can be seen from the above description that when multiple slave devices need to be connected, multiple selection signal terminals are inevitably required. In the case where the device has a limited number of pins, this action causes a waste of the number of pins.

To solve the above-mentioned conventional problems, the present invention discloses a transmission control device, which includes a master control device and a plurality of slave control devices. The master control device includes at least a first serial peripheral interface, wherein the first clock signal terminal of the first serial peripheral interface transmits the device identification signal, the first master output and the slave input output the first signal, or the first master input and slave output The end receives the second signal.

A plurality of slave control devices respectively include at least a second serial peripheral interface, a frequency counter, and a register. The second clock signal end of the second serial peripheral interface receives the device identification signal, and the second master output receives the first signal from the input end. One signal, the second main input and the second output output the second signal.

The frequency counter analyzes the device identification signal, the register sets the device frequency of the slave device, and the device frequency includes the frequency of the fault tolerance range. Among them, the device frequencies of a plurality of slave devices do not overlap, and the frequency range of the device identification signal transmitted by the master device includes the device frequency of each plurality of slave devices. When one of them communicates, the master device generates a device identification signal corresponding to the device frequency of the selected slave device, and the selected slave device determines whether to communicate with the master device according to the device identification signal.

According to the embodiment of the present invention, the sequence of the device identification signal transmission takes precedence over the first signal and the second signal.

According to an embodiment of the present invention, the device identification signal is represented by at least two clock signals.

According to an embodiment of the present invention, the first signal corresponds to the write signal, and the second signal corresponds to the read signal.

The present invention also provides a transmission control method, which is suitable for transmitting peripheral interfaces, which at least includes the following steps: the master control device passes through the first clock signal end of the first serial peripheral interface, and transmits the device identification signal to a plurality of slave control devices. Device.

The plurality of slave control devices respectively receive the device identification signal through the second clock signal end of the second serial peripheral interface, and respectively use the frequency counter analysis device to identify the signal.

The master device transmits the first signal to the slave device corresponding to the device identification signal, or the slave device corresponding to the device identification signal transmits the second signal to the master device.

According to an embodiment of the present invention, each slave device that does not correspond to the device identification signal is maintained in an idle state.

According to an embodiment of the present invention, the first data signal corresponds to the write signal and the second signal corresponds to the read signal.

In summary, the transmission control device and method of the present invention have the following advantages:

(1) One-to-many communication is completed by using only the clock signal terminal, the master-out-slave-in terminal, and the master-in-slave output terminal without using the selection signal terminal, so that the number of pins of the device can be reduced and waste is avoided.

(2) The master device transmits the device identification signal to each slave device, and the slave device analyzes the frequency of the device identification signal through the frequency counter, and then switches the selected signal end of the slave device corresponding to the device identification signal to the active State or idle state for data writing or reading. Such an operation method can correctly write data to a specific slave device or read data from a specific slave device in a plurality of slave control devices.

Hereinafter, the embodiments of the present invention will be described based on Figs. 1 to 5. The description is not intended to limit the implementation of the present invention, but merely an example of the present invention.

Refer to Figure 1, which is a schematic diagram of a transmission control device according to an embodiment of the present invention. As shown in the figure, the transmission control device 100 includes a master control device 110 and a plurality of slave control devices 120.

According to an embodiment of the present invention, the master control device 110 includes at least a first serial peripheral interface 111, a first clock signal terminal 112 of the first serial peripheral interface 111, a transmission device identification signal 116, and a first master output/slave input terminal 113 The first signal 117 is output, or the first main input and slave output 114 receives the second signal 118.

According to an embodiment of the present invention, each slave control device 120 includes at least a second serial peripheral interface 121, a frequency counter 122, and a register 123, respectively. The second clock signal terminal 124 of the second serial peripheral interface 121 receives the device identification signal 116 transmitted by the master control device 110 via the first clock signal terminal 112, and the second master-out-slave of the second serial peripheral interface 121 The input 125 receives the first signal 117 output by the main control device 110 via the first main output/slave input 113, or the first main input/slave output 114 of the main control device 110 receives the first signal 117 output via the second serial peripheral interface 121 The two main input and slave output terminals 126 output a second signal 118.

According to the embodiment of the present invention, the frequency counter 122 of each slave control device 120 analyzes the device identification signal 116 received by the second clock signal terminal 124. The register 123 of each slave control device 120 can set the device frequency of each slave control device 120, and each device frequency includes the fault tolerance range frequency.

According to the embodiment of the present invention, the device frequencies of each slave device 120 do not overlap, and the frequency range of the device identification signal 116 transmitted by the master device 110 includes the device frequency of each slave device 120. When the master device 110 selects When communicating with one of the slave devices 120, the master device 110 generates a device identification signal 116 corresponding to the device frequency of the selected slave device 120, and the selected slave device 120 determines whether it is with the master according to the device identification signal 116. The device 110 communicates.

The above-mentioned master control device, slave control device and the serial peripheral interfaces contained therein are mostly used for high-speed data communication between internal components of electronic products, such as data transmission between large-capacity storage devices. Refer to Figures 2 and 3, where Figure 2 is a schematic diagram of the prior art serial peripheral interface structure, and Figure 3 is a schematic diagram of the prior art serial peripheral interface data transmission. As shown in Figure 2, the communication between serial peripheral interfaces is in full-duplex mode, usually with four reserved logic signal interfaces, that is, the aforementioned clock signal terminal, master out and slave in, and master in and slave out. Terminal, and select the signal terminal. As shown in Figure 3, the signal transmitted by the master output and slave input of the master control device corresponds to the above-mentioned first signal, and the signal transmitted by the master input and slave output of the slave control device corresponds to the second signal mentioned above, and the master The signal sent by the clock signal end of the device is the regular clock signal.

Refer to FIG. 4, which is a schematic diagram of data transmission of a serial peripheral interface according to an embodiment of the present invention. As shown in the figure, the sequence of the device identification signal 116 transmitted by the clock signal terminal 112 of the master device 110 has priority over the first signal 117 and the second signal 118 mentioned above. This means that when the master device 110 wants to transmit data with the slave device 120, it must first send the device identification signal 116 to each slave device 120, and the master device 110 will use this to perform data transfer to which slave device 120 The action of the transmission. After the master control device 110 determines which slave control device 120 to transmit data to, the first data 117 or the second data 118 is transmitted.

According to the embodiment of the present invention, the device identification signal 116 transmitted by the clock signal terminal 112 of the main control device 110 can be represented by at least two clock signals. The frequency counter 122 of each slave control device 120 mentioned above can analyze the two clock signals, for example, determine the time difference between the rising edge or the falling edge of the two clock signals, and then calculate What is the frequency corresponding to the device identification signal 116?

According to the embodiment of the present invention, the first signal 117 transmitted after the device identification signal 116 can represent that the master control device 110 transmits the write signal through the first master output and slave input 113 of the first serial peripheral interface 111. In addition, data is written into the slave control device 120 via the second master-out-slave-in terminal 125 of the second serial peripheral interface 121.

According to the embodiment of the present invention, the second signal 118 transmitted after the device identification signal 116 can represent that the master control device 110 receives the second signal through the second serial peripheral interface 111 through the first master input and slave output 114 of the first serial peripheral interface 111. The reading signal transmitted by the second main input and slave output end 126 of the serial peripheral interface 121 reads the data from the slave control device 120.

According to the embodiment of the present invention, the device frequency set by the register 123 of each slave control device 120 does not overlap with each other in frequency ranges, and the device identification signal transmitted by the master control device 110 to each slave control device 120 The frequency range of 116 includes the device frequency range set by each register 123. Therefore, it can be ensured that the device identification signal 116 transmitted by the master control device 110 can identify each slave device 120, and the identification error of the slave control device 120 will not occur due to the overlap of the device frequency of each slave control device 120.

Refer to FIG. 5, which is a flowchart of the steps of a transmission control method according to an embodiment of the present invention. As shown in the figure, the transmission control method of the present invention is suitable for serial peripheral interfaces, and it includes at least the following steps (S1~S4):

Step S1: The master device 110 in the transmission control device 100 transmits the device identification signal 116 to the plurality of slave devices 120 via the first clock signal terminal 112 of the first serial peripheral interface 111.

Step S2: Each slave device 120 receives the device identification signal 116 via the second clock signal terminal 124 of the second serial peripheral interface 121, and analyzes the device identification signal 116 through the frequency counter 122 of each slave device 120 respectively.

Step S3: The master control device 110 transmits the first signal 117 to the slave control device 120 via the first master output/slave input 113 of the first serial peripheral interface 111, and the first signal 117 is transmitted via the second serial peripheral interface 121 The second main output is received from the input 125.

According to the embodiment of the present invention, or the first master-in-slave end 114 of the first serial peripheral interface 111 of the master control device 110 receives the second master-in-slave end 114 of the second serial peripheral interface 121 of the slave control device 120 The second signal 118 transmitted by the output terminal 126.

According to the embodiment of the present invention, after the frequency counter 122 of each slave control device 120 analyzes the received device identification signal 116, if the frequency corresponding to the device identification signal 116 is different from the device frequency set by the register 123 of the slave control device 120 If yes, the slave control device 120 is maintained in an idle state, as in step S4.

According to the embodiment of the present invention, the first signal 117 corresponds to a write signal for the master device 110 to perform a write operation on the slave device 120 through the first master-out-slave-in terminal 113 of the first serial peripheral interface 111.

According to an embodiment of the present invention, the second signal 118 corresponds to the read signal for the master device 110 to perform a read operation on the slave device 120 through the first master input and slave output port 114 of the first serial peripheral interface 111 .

Based on the above description, there is only one master control device 110 in the transmission control device 100 of the present invention, and there is more than one slave control device 120. The master control device 110 can identify the signal 116 to a plurality of slave control devices 120 through the output device. The slave control device 120 determines whether to respond to the master control device 110. The selection signal terminal between the serial peripheral interface and the traditional serial peripheral interface requires a one-to-one connection, so that each additional slave device 120 requires one more pin. The connection method is different.

The master device 110 of the present invention transmits the device identification signal 116 to each slave device 120 through the clock signal end of the first serial peripheral interface 111 before reading or writing data to any slave device 120 Each slave device 120 analyzes the device identification signal 116 through the frequency counter 122 to obtain the frequency corresponding to the device identification signal 116.

For example, if the system frequency of the frequency counter 122 is 200MHz, the frequency counter 122 detects the number of cycles corresponding to adjacent rising or falling edges of the input signal. If the calculated number is 40, it represents the number of cycles of the input signal. The frequency is 5MHz. If the calculated number is 10, it means that the frequency of the input signal is 20MHz.

In this way, the register 123 of each slave control device 120 is then used to set a device frequency value to represent the code of each slave control device 120. For example, the frequency counter 122 is at two adjacent rising edges or falling edges of the device identification signal 116. The calculated number of cycles is 40 (representing a frequency of 5 MHz), which represents a certain slave control device 120.

The device frequency set by the register 123 includes a fault-tolerant range frequency. For example, the number of cycles calculated by the frequency counter 122 is 36 to 44 (representing a frequency between 4.54MHz and 5.56MHz), which corresponds to the same slave control装置120. Table 1 lists the frequency ranges that each slave device can correspond to when there is more than one slave device.

Table 1: Frequency Range Slave 1 (5MHz) frequency 4.54MHz 5MHz 5.56MHz count 44 40 36 Slave 2 (6.6MHz) frequency 5.88MHz 6.6MHz 7.69MHz count 34 30 26 Slave 3 (10MHz) frequency 8.3MHz 10MHz 12.5MHz count twenty four 20 16 Slave 4 (20MHz) frequency 14.28MHz 20MHz 33.3MHz count 14 10 6

Then, the master control device 110 writes data to the slave control device 120, or reads data from the slave control device 120. When writing data, the frequency corresponding to the data signal is transmitted to the slave device 120 via the first clock signal terminal 112 of the first serial peripheral interface 111, and the data signal is transmitted from the input terminal 113 through the first master output To the slave control device 120.

Conversely, when reading data, the frequency corresponding to the data signal is transmitted to the slave device 120 through the first clock signal terminal 112 of the first serial peripheral interface 111, and the data signal is transmitted through the second serial peripheral interface 121 The second main input of is read from the output terminal 126 to the main control device 110.

As a non-limiting example, the methods and systems described herein can be used in various applications, such as in secure memory applications, Internet of Things (IoT) applications, embedded applications, or automotive applications, to name just a few examples.

100: Transmission control device 110: Master control device 111: The first serial peripheral interface 112: The first clock signal terminal 113: The first master out from the incoming end 114: The first main input from the output end 116: Device identification signal 117: First Signal 118: The second signal 120: Slave control device 121: The second serial peripheral interface 122: frequency counter 123: register 124: The second clock signal terminal 125: Second main out and slave in 126: Second main input from output S1~S4: steps

In order to make the above and other objects, features, advantages and embodiments of the present invention more comprehensible, the description of the attached drawings is as follows: Figure 1 is a schematic diagram of a transmission control device according to an embodiment of the present invention. Figure 2 is a schematic diagram of the prior art serial peripheral interface architecture. Figure 3 is a schematic diagram of data transmission of the serial peripheral interface of the prior art. FIG. 4 is a schematic diagram of data transmission of a serial peripheral interface according to an embodiment of the present invention. Figure 5 is a flow chart of the steps of a transmission control method according to an embodiment of the present invention.

100: Transmission control device

110: Master control device

111: The first serial peripheral interface

112: The first clock signal terminal

113: The first master out from the incoming end

114: The first main input from the output end

116: Device identification signal

117: First Signal

118: The second signal

120: Slave control device

121: The second serial peripheral interface

122: frequency counter

123: register

124: The second clock signal terminal

125: Second main out and slave in

126: The second main input from the output

Claims (7)

A transmission control device, which includes: A master device, which includes at least: A first serial peripheral interface (SPI), a first clock (SCLK) signal terminal transmits a device identification signal, and a first master output slave input (MOSI) The terminal outputs a first signal or a first master input slave output (master input slave output, MISO) terminal receives a second signal; and A plurality of slave devices, each of which includes at least: A second serial peripheral interface, a second clock signal terminal of which receives the device identification signal, a second master output and slave input terminal receives the first signal, and a second master input and slave output terminal outputs the second signal; A frequency counter that analyzes the device identification signal; and A register, which sets a device frequency of the slave device, and the device frequency includes a fault-tolerant range frequency; Wherein, the device frequencies of a plurality of slave devices do not overlap, and the frequency range of the device identification signal transmitted by the master device includes the device frequency of each of the plurality of slave devices, when the master device selects and When one of a plurality of slave devices communicates, the master device generates a device identification signal corresponding to the device frequency of the selected slave device, and the selected slave device determines whether it is with the master based on the device identification signal The device communicates. The transmission control device according to claim 1, wherein the sequence of the device identification signal transmission has priority over the first signal and the second signal. The transmission control device according to claim 2, wherein the device identification signal is represented by at least two clock signals. The transmission control device according to claim 2, wherein the first signal corresponds to a write signal, and the second signal corresponds to a read signal. A transmission control method suitable for serial peripheral interfaces, which includes at least the following steps: A master control device transmits a device identification signal to a plurality of slave control devices via a first clock signal end of a first serial peripheral interface; The plurality of slave devices receive the device identification signal through a second clock signal end of a second serial peripheral interface, and analyze the device identification signal by a frequency counter respectively; and The master control device transmits a first signal to the slave control device corresponding to the device identification signal, or the slave control device corresponding to the device identification signal transmits a second signal to the master control device. The transmission control method according to claim 5, wherein each slave control device that does not correspond to the device identification signal is maintained in an idle state. The transmission control method according to claim 5, wherein the first signal corresponds to a write signal and the second signal corresponds to a read signal.

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