TWI767234B - Method for increasing transmission rate of serial peripheral interface, data transmission circuit and information processing device - Google Patents

Abstract

The present invention mainly discloses a method for increasing the transmission rate of a serial peripheral interface, which is applied in a data transmission circuit. The data transmission circuit includes a master chip, a slave chip, and a chip coupled to the master chip. A serial peripheral interface with the controlled end chip. By implementing the method for increasing the transmission rate of the serial peripheral interface of the present invention and applying it to the data transmission circuit, the master chip can determine a delay parameter and configure the delay parameter to the slave chip, thereby The method ensures that the serial data transmitted through the MISO channel of the serial peripheral interface will not have transmission errors due to time delay, so that the serial peripheral interface can meet the requirements between the host chip and the slave chip. high-speed transmission requirements.

Description

Method for increasing transmission rate of serial peripheral interface, data transmission circuit and information processing device

The present invention relates to the technical field of data transmission between chips, in particular to a method for increasing the transmission rate of a serial peripheral interface (SPI).

It is known that various electronic chips for performing different tasks are configured in different types of electronic products. Therefore, it is very important to efficiently transmit data between two electronic chips. At present, the two serial (serial) interfaces, IIC and SPI, are proposed by Philips and Motorola, respectively, which allow microcontrollers and their peripheral chips to achieve chip-to-chip communication while greatly reducing the use of pins. Communication (data transfer) between devices, such as sensors, analog-to-digital converters, digital-to-analog converters, shift registers, static random access memory, flash memory, etc.

FIG. 1 is a first block diagram of a conventional data transmission circuit. As shown in FIG. 1, in a conventional data transmission circuit using a serial peripheral interface (SPI) for data transmission, a master end chip 1a has a first pin 11a , a second pin 12a, a third pin 13a, and a fourth pin 14a, and a slave end chip 2a also has a first pin 21a, a second pin 22a, A third pin 23a, and a fourth pin 24a. In the serial peripheral interface transmission protocol, the first pin 11a of the master chip 1a transmits a serial clock signal (Serial clock, SCK) and a chip select signal (Chip select, CS) to the slave chip 1a respectively. The first pin 21a and the second pin 22a of 2a.

Through the third pin 13a, the master chip 1a can transmit (drive) a first serial data in the master register 10a to a MOSI channel, so that the slave chip 2a uses the third pin Bit 23a receives the first serial data through the MOSI channel. The MOSI referred to here refers to the output of the master terminal (Master out) and the input of the slave terminal (Slave in). On the other hand, when reading (sampling) a second serial data from the controlled end chip 2a, the controlled end chip 2a sends a second serial data in the controlled end register 20a through the fourth pin 24a It is transmitted (driven) to a MISO channel, so that the host chip 1a receives (samples) the second serial data through the MISO channel with its fourth pin 14a. The MISO here refers to the input of the master (Master in) and the output of the slave (Slave out).

FIG. 2 is a first operation timing diagram of a signal transmitted through a conventional serial peripheral interface. As shown in Table 1 below, according to the clock polarity (Clock polarity, CPOL) and the clock phase (Clock phase, CPHA), the conventional serial peripheral interface can have four data transmission modes. Table 1) model CPOL CPHA Serial data driving and/or sampling 0 0 0 Sampling on SCK rising edge Driven on SCK falling edge 1 0 1 Sampling on SCK falling edge Driven on SCK rising edge 2 1 0 Sampling on SCK falling edge Driven on SCK rising edge 3 1 1 Sampling on SCK rising edge Driven on SCK falling edge

FIG. 3 is a second block diagram of a conventional data transmission circuit. As shown in FIG. 3, in practical applications, the controlled end chip 2a may be disposed on a controlled end plate member 3a, wherein a first electrical contact 31a of the controlled end plate member 3a, a The second electrical contact 32a, a third electrical contact 33a, and a fourth electrical contact 34a are used for coupling to a first electrical contact 41a and a second electrical contact of a main control end board 4a, respectively 42a, a third electrical contact 43a, and a fourth electrical contact 44a.

Please also refer to the second operation timing diagram of the signal transmitted through the conventional line peripheral interface shown in FIG. 4 . As shown in FIG. 3 and FIG. 4 , in practical applications, the board-to-board (B2B) delay will occur when the serial clock signal SCK passes through the first electrical circuit of the main control end board 4a. This occurs during the transfer of the contact 41a to the first electrical contact 31a of the controlled end plate member 3a. At the same time, the Board to Device (B2D) delay will be transmitted to the second terminal chip 2a via the first electrical contact 31a of the controlled terminal board 3a when the serial clock signal SCK is transmitted. occurs during the course of a pin 21a. Further, in the case of reading data from the controlled end chip 2a, the device to board (D2B) delay will occur when the serial data passes through the fourth pin 24a of the controlled end chip 2a This occurs during transmission to the fourth electrical contact 34a of the controlled end plate member 3a. At the same time, the board-to-board transmission time delay (B2B delay) is also transmitted to the fourth electrical connection of the master control end board 4a via the fourth electrical contact 34a of the controlled end board 3a. occurs during point 44a.

Further, if the internal transmission time delay (Trans_delay) also occurs at the controlled end chip 2a at the same time, the calculation method of the time delay (Time delay) that occurs during the signal transmission process through the serial peripheral interface is: (B2B delay )+(B2D delay)+(Trans_delay)+(D2B delay)+(B2B delay). Assuming that the operating frequency of the serial clock signal SCK is f, its corresponding period is T. As shown in FIG. 4 , when the time delay (Time delay) is greater than T/2, the serial data transmitted in the MISO channel will have a data error phenomenon. Practical experience points out that when the operating frequency of the serial clock signal SCK is higher, the bandwidth of data transmission is also larger, so that the rate of data transmission is also faster. Unfortunately, with the increase of the data rate, the time delay phenomenon in the signal transmission process becomes more and more obvious, which makes the conventional serial peripheral interface unable to transmit the data at the ideal rate.

It can be seen from the above description that there is an urgent need in the art for a method for increasing the transmission rate of a serial peripheral interface.

The main purpose of the present invention is to provide a method for increasing the transmission rate of a serial peripheral interface, which is applied in a data transmission circuit including a master chip, a slave chip and a serial peripheral interface, so that the master The control end chip can configure a delay parameter to the controlled end chip to ensure that the serial data transmitted through the serial peripheral interface will not have transmission errors due to time delay, so as to satisfy the requirements of the control end chip and the controlled end chip. High-speed transfer requirements between end wafers.

In order to achieve the above object, the present invention provides an embodiment of the method for increasing the transmission rate of the serial peripheral interface, which includes:

(1) X test registers are set inside a controlled end chip, and X is a positive integer;

(2) Make a host chip write a serial data for testing to the ith of the X test registers through a serial peripheral interface, and then from the ith of the test registers through the serial peripheral interface Read out the serial data for the test; wherein, the initial value of i is 1, and i≦X;

(3) Perform a data correctness check on the read serial data for testing, and perform the following step (4) if the data correctness check fails, and when the data correctness check is In the case of passing, perform the following steps (5);

(4) configuring a delay parameter to the slave chip through the master chip, and then repeating the step (2); and

(5) In the case that i is less than X, the host chip writes a test serial data to the i+1 th of the X test registers through the serial peripheral interface, and then passes the serial The peripheral interface reads the test serial data from the i+1th test register, and then repeats the step (3); and when i is equal to X, the X test registers have all completed the test With the data correctness check of the serial data, the delay parameter is confirmed to be valid.

In one embodiment, the method for increasing the transmission rate of the serial peripheral interface further includes the following steps:

(6) The host chip and the slave chip start to transmit at least one serial data through the serial peripheral interface.

In one embodiment, when the host chip reads the test serial data from the test register through the serial peripheral interface, it does not use a first bit of the read test serial data The group (bytes) performs this data correctness check.

In one embodiment, each of the X test registers has a register address, and the X number of the register addresses are set by the host chip.

In one embodiment, the register addresses are different from each other, and the serial data for testing are the same or different from each other.

The present invention also provides a data transmission circuit comprising a master chip, at least one slave chip, and at least one serial peripheral interface coupled between the master chip and the at least one slave chip; It is characterized in that, X test registers are set inside the controlled end chip, and the master control end chip executes a transmission rate improvement method to increase the transmission rate of a serial data transmission of the serial peripheral interface; the transmission Rate boosting methods include:

(1) Make the host chip write a serial data for testing to the selected slave chip of the at least one slave chip through a selected serial peripheral interface of the at least one serial peripheral interface The ith of the X test registers of the end chip, and then read the serial data for testing from the ith test register through the serial peripheral interface; wherein, X is a positive integer, and the initial value of i is 1, and i≦X;

(2) Perform a data correctness check on the read serial data for testing, and execute the following step (3) if the data correctness check fails, and when the data correctness check is In the case of passing, perform the following steps (4);

(3) configuring a delay parameter to the selected controlled end chip through the master chip, and then repeating the step (2);

(4) In the case that i is less than X, the host chip writes a test serial data to the i+1 th of the X test registers through the selected serial peripheral interface, and then passes the selected serial data The serial peripheral interface reads the test serial data from the i+1th test register, and then repeats the step (3); and in the case where i is equal to X, the X test registers have all been completed The data correctness of the test serial data is checked, and the delay parameter is confirmed to be valid; and

(5) The host chip and the selected slave chip start to transmit at least one serial data through the selected serial peripheral interface.

In an embodiment of the data transmission circuit of the present invention, when the host chip reads out the test serial data from the test register through the selected serial peripheral interface, the test of the readout is not performed. The data correctness check is performed with a first tuple of one of the serial data.

In an embodiment of the data transmission circuit of the present invention, each of the X test registers has a register address, each of the register addresses is different from each other, and each of the test serial data is the same or different from each other.

The present invention also provides an information processing device having a central processing unit and the data transmission circuit of the present invention as described above, wherein the central processing unit is used for communicating with the data transmission circuit.

In a feasible embodiment, the information processing device may be a smart phone, a tablet computer, a notebook computer, an all-in-one computer, a smart watch or an access control device.

In order to enable your examiners to further understand the structure, characteristics, purpose, and advantages of the present invention, drawings and detailed descriptions of preferred embodiments are attached as follows.

FIG. 5 is a block diagram of a data transmission circuit applying a method for increasing the transmission rate of a serial peripheral interface of the present invention. As shown in FIG. 5 , in a data transmission circuit for data transmission through a serial peripheral interface (SPI), a host chip 1 has a first pin 11 , a second pin 12 , a first pin The three pins 13 and a fourth pin 14 are internally provided with at least one master shift register 10 . In addition, in practical applications, the host chip 1 can be configured to have a first electrical contact 41 , a second electrical contact 42 , a third electrical contact 43 , and a fourth electrical contact 44 on a main control end plate 4. As shown in FIG. 5, in the data transmission circuit, a controlled end chip 2 also has a first pin 21, a second pin 22, a third pin 23, and a fourth pin twenty four. In addition, in practical applications, the controlled end chip 2 can be set to have a first electrical contact 31 , a second electrical contact 32 , a third electrical contact 33 , and a fourth electrical contact 34 of a controlled end plate 3.

In the serial peripheral interface transmission protocol, the master chip 1 transmits a serial clock signal (Serial clock, SCK) and a chip select signal (Chip select, CS) to the slave chip with its first pin 11 respectively. 2's first pin 21 and second pin 22. In addition, through the third pin 13, the master chip 1 can transmit (drive) a first serial data in the master register 10 to a MOSI channel, so that the slave chip 2 uses its first serial data to transmit (drive) a MOSI channel. Pin 23 receives the first serial data through the MOSI channel. The MOSI referred to here refers to the output of the master terminal (Master out) and the input of the slave terminal (Slave in).

In addition, when the master chip 1 reads (samples) a second serial data from the slave chip 2 through the serial peripheral interface, the slave chip 2 sends its slave register 20 through the fourth pin 24 One of the second serial data is transmitted (driven) to a MISO channel, so that the host chip 1 with its fourth pin 14 receives (samples) the second serial data through the MISO channel. The MISO here refers to the input of the master (Master in) and the output of the slave (Slave out).

According to FIG. 3 and FIG. 4 , it can be understood that a time delay (Time delay) occurs in the process of using the serial peripheral interface for signal transmission, and the calculation method of the time delay is: (B2B delay)+(B2D delay) +(Trans_delay)+(D2B delay)+(B2B delay). Among them, B2B delay is Board to Board (B2B) delay, B2D delay is Board to Device (B2D) delay, D2B delay is device pair The transit time delay of the board (Device to Board (D2B) delay), and Trans_delay is the internal transit time delay of the controlled end chip 2. Therefore, a method for increasing the transmission rate of a serial peripheral interface of the present invention is applied to a data transmission circuit using the serial peripheral interface (SPI) for data transmission, so that the host chip 1 of the data transmission circuit executes the The method of the present invention can effectively improve the transmission rate of a serial data transmission of the serial peripheral interface.

FIG. 6 is a flowchart of a method for increasing the transmission rate of a serial peripheral interface according to the present invention. As shown in FIG. 5 and FIG. 6 , the method for increasing the transmission rate of the serial peripheral interface of the present invention firstly executes steps S1 and S2 : setting X test registers 25 in a controlled-end chip 2 , and then making a host-end chip 1. Write a test serial data to the ith of the X test registers 25 through a serial peripheral interface, and then read the test serial data from the ith test register 25 through the serial peripheral interface row data; where X is a positive integer, the initial value of i is 1, and i≦X. Preferably, in one embodiment, X is 4. That is, four test registers 25 are arranged on the controlled-side wafer 2 .

In more detail, the master chip 1 drives the test serial data to a MOSI channel through its third pin 13 , so that the slave chip 2 passes through the MOSI through its third pin 23 The channel receives serial data for this test. When reading (sampling) the test serial data, the controlled end chip 2 transmits the test serial data in the controlled end register 20 through the fourth pin 24 (driving). ) to a MISO channel, so that the host chip 1 with its fourth pin 14 receives (samples) the serial data for testing through the MISO channel.

Continuingly, the method flow is to perform step S3: perform a data correctness check on the read serial data for testing, and perform the subsequent step S4 in the case that the data correctness check fails, and in all If the above-mentioned data correctness check is passed, the subsequent step S5 is executed. In other words, after a write/read operation of a test serial data is performed on the first one of the plurality of test registers 25 , the host chip 1 can read a test serial data with an original setting and the read data. The serial data for the test is compared, and the correctness of the serial data for the test is checked in this way.

Therefore, in the case that the data correctness check fails, the method flow then executes step S4: configure a delay parameter to the slave chip 2 through the master chip 1, and then repeat the steps S2 and the Step S3. After configuring the delay parameter to the controlled end chip 2, if the data correctness check is passed, the subsequent step S5 can be performed. On the other hand, if it still fails, after adjusting the value of the delay parameter, the step S2 and the step S3 are then repeatedly executed.

After the data correctness check of the test serial data of the first test register 25 is determined to be passed, the same data correctness check procedure must be performed on all other test registers 25, so the method flow then executes step S5: When i is less than X, the host chip 1 writes a test serial data to the i+1 th of the X test registers 25 through the serial peripheral interface, and then passes the serial peripheral interface The interface reads the test serial data from the i+1th test register 25, and then repeats the step (3); and when i is equal to X, the X test registers 25 have all completed the test The data correctness check of the serial data is used for testing, and the delay parameter is confirmed to be valid.

In other words, only after all the test registers 25 have completed the data correctness check of the test serial data, the specially set delay parameter will be regarded as valid. After that, the host chip 1 and the slave chip 2 can start to transmit at least one serial data through the serial peripheral interface. FIG. 7 is a first operation timing diagram of signals transmitted by the serial peripheral interface of the present invention. As shown in FIG. 7 , the master chip 1 and the slave chip 2 use the SPI mode0 protocol for data transmission, and after applying the method for increasing the transmission rate of the serial peripheral interface of the present invention, the value of the delay parameter is set to 1 . As can be seen from Figure 7, the calculation method of the time delay (Time delay) that occurs in the process of signal transmission through the MISO channel of the Serial Peripheral Interface (SPI) is: (B2B delay)+(B2D delay)+(Trans_delay)+ (D2B delay)+(B2B delay)-(N*T/2) < T/2. In the preceding formula, N is the delay parameter. To put it simply, in the case of applying the method for increasing the transmission rate of the serial peripheral interface of the present invention, the time delay is adjusted from the original greater than T/2 to less than T/2, so as to ensure the transmission between the MISO channels. There is no data error phenomenon in the serial data in the serial interface, so that the serial peripheral interface can meet the needs of high-speed transmission.

Of course, in the case where the types of the master chip 1 and/or the slave chip 2 are different, after completing the data correctness check process using the serial data for testing, it may still be unnecessary to send the data to the slave chip 2. Configure delay parameters. FIG. 8 is a second operation timing diagram of the signal transmitted by the serial peripheral interface applying the method for increasing the transmission rate of the serial peripheral interface of the present invention. As shown in FIG. 8 , the master chip 1 and the slave chip 2 use the SPI mode0 protocol for data transmission and after applying the method for increasing the transmission rate of the serial peripheral interface of the present invention, the result shows that there is no direction to the controlled The end chip 2 configures the need for delay parameters (ie, N=0).

It is added that, in the process of applying the method for increasing the transmission rate of the serial peripheral interface of the present invention, when the host chip 1 reads the test serial data from the test register 25 through the serial peripheral interface , the so-called data correctness check is not performed on one of the first bytes of the read-out serial data for testing. The main reason is that when reading (sampling) serial data from the controlled-end chip 2 , the controlled-end chip 2 may transmit (drive) the serial data in its test register 25 to the MISO channel in advance. Therefore, in order to avoid misjudgment when performing the data correctness check, it is necessary to use the first byte of the read serial data for testing as dummy data, and not perform data correctness on it. examine.

On the other hand, each of the X test registers 25 disposed inside the slave chip 2 has a register address, and the X register addresses are set by the master chip 1 . In one embodiment, the register addresses are different from each other, eg, addr:0xaa, addr:0x55, addr:0x5a, addr:0xa5, and so on. Meanwhile, the serial data for testing is also set through the host chip 1, and the serial data for testing can be the same or different from each other. For example, data:aaaaaa, data:555555, data:5a5a5a, data:a5a5a5, etc.

In this way, the above has completely and clearly described a method for increasing the transmission rate of a serial peripheral interface of the present invention; and, from the above, it can be known that the present invention has the following advantages:

(1) The present invention discloses a method for increasing the transmission rate of a serial peripheral interface, which can be applied to a data transmission circuit. The data transmission circuit includes a master chip, a slave chip, and a chip coupled to the master chip. A serial peripheral interface between the control end chip and the controlled end chip. A method for increasing the transmission rate of a serial peripheral interface of the present invention is applied to the data transmission circuit, so that the master chip configures a delay parameter to the slave chip by executing the method of the present invention, so as to ensure that the The serial data transmitted by the MISO channel of the serial peripheral interface will not have errors due to time delay, so that the serial peripheral interface can meet the high-speed transmission requirement between the master chip and the slave chip.

(2) The present invention also discloses a data transmission circuit, which has a master chip, at least one slave chip, and at least one string coupled between the master chip and the at least one slave chip A peripheral interface is performed; wherein, the host chip executes the method for increasing the transmission rate of the serial peripheral interface of the present invention, thereby increasing the transmission rate of a serial data transmission of the serial peripheral interface.

(3) The present invention also provides an information processing device having a central processing unit and the data transmission circuit of the present invention as described above, wherein the central processing unit is used for communication with the data transmission circuit. Moreover, the information processing device can be a smart phone, a tablet computer, a notebook computer, an all-in-one computer, a smart watch, or an access control device.

It must be emphasized that the above-mentioned disclosure in this case is a preferred embodiment, and any partial changes or modifications originating from the technical ideas of this case and easily inferred by those who are familiar with the art are within the scope of the patent of this case. category of rights.

To sum up, regardless of the purpose, means and effect of this case, it shows that it is completely different from the conventional technology, and its first invention is practical, and it does meet the patent requirements of the invention. Society is to pray for the best.

1a: main control chip 10a: Master register 11a: first foot position 12a: second foot position 13a: The third foot 14a: Fourth foot 2a: Controlled end chip 20a: Controlled end register 21a: first foot position 22a: second foot position 23a: third foot 24a: Fourth foot 3a: Controlled end plate 31a: first electrical contact 32a: second electrical contact 33a: The third electrical contact 34a: Fourth electrical contact 4a: Main control end board 41a: first electrical contact 42a: second electrical contact 43a: The third electrical contact 44a: Fourth electrical contact 1: Main control chip 10: Master register 11: The first foot 12: The second pin 13: The third foot 14: Fourth foot 2: Controlled end chip 20: Controlled end register 21: The first foot 22: The second foot 23: The third foot 24: Fourth foot 25: Test register 3: Controlled end plate 31: The first electrical contact 32: The second electrical contact 33: The third electrical contact 34: Fourth electrical contact 4: Main control end board 41: The first electrical contact 42: The second electrical contact 43: The third electrical contact 44: Fourth electrical contact S1: Set X test registers inside a controlled end chip S2: Make a host chip write a test serial data to the ith of the X test registers through a serial peripheral interface, and then read from the ith test register through the serial peripheral interface Output the serial data for the test; the initial value of i is 1, and i≦X S3: Execute a data correctness check on the read serial data for testing. If the data correctness check fails, execute the following step S4, and if the data correctness check is passed, execute the following steps. The following step S5 S4: Configure a delay parameter N to the controlled end chip through the master chip, and then repeat the step S2 S5: In the case that i is less than X, the host chip writes a test serial data to the i+1 th of the X test registers through the serial peripheral interface, and then passes the serial peripheral interface The interface reads out the test serial data from the i+1th test register, and then repeats the step S3; and in the case where i is equal to X, all the X test registers have completed the test serial data The correctness of the data is checked, and the delay parameter N is confirmed to be valid.

1 is a first block diagram of a conventional data transmission circuit; 2 is a first operation timing diagram of a signal transmitted through a conventional line peripheral interface; 3 is a second block diagram of a conventional data transmission circuit; FIG. 4 is a second operation timing diagram of a signal transmitted through a conventional line peripheral interface; 5 is a block diagram of a data transmission circuit applying a method for increasing the transmission rate of a serial peripheral interface of the present invention; 6 is a flowchart of a method for increasing the transmission rate of a serial peripheral interface according to the present invention; FIG. 7 is a first operation timing diagram of signals transmitted by the serial peripheral interface applying the present invention; and FIG. 8 is a second operation timing diagram of the signal transmitted by the serial peripheral interface applying the present invention.

S1: Set X test registers inside a controlled end chip

S2: Make a host chip write a test serial data to the ith of the X test registers through a serial peripheral interface, and then read from the ith test register through the serial peripheral interface Output the serial data for the test; the initial value of i is 1, and i≦X

S3: Execute a data correctness check on the read serial data for testing. If the data correctness check fails, execute the following step S4, and if the data correctness check is passed, execute the following steps. The following step S5

S4: Configure a delay parameter N to the controlled end chip through the master chip, and then repeat the step S2

S5: In the case that i is less than X, the host chip writes a test serial data to the i+1 th of the X test registers through the serial peripheral interface, and then passes the serial peripheral interface The interface reads the test serial data from the i+1th test register, and then repeats the step S3; and in the case that i is equal to X Next, the X test registers have all completed the data correctness check of the test serial data, and the delay parameter N is confirmed to be valid

Claims (10)

A method for increasing the transmission rate of a serial peripheral interface, comprising: (1) setting X test registers inside a controlled end chip, where X is a positive integer; (2) making a master control end chip write a serial peripheral interface Input a serial data for testing into the ith of the X test registers, and then read out the serial data for testing from the ith test register through the serial peripheral interface; wherein, the initial value of i is 1, and i≦X; (3) perform a data correctness check on the read serial data for testing, and perform the following step (4) if the data correctness check fails, and If the data correctness check is passed, execute the following step (5); (4) adjust a delay parameter to the slave chip through the master chip, and then repeat the step (2); (5) ) In the case that i is less than X, the host chip writes a test serial data to the i+1 th of the X test registers through the serial peripheral interface, and then passes the serial peripheral interface Read out the test serial data from the i+1th test register, and then repeat the step (3); and when i is equal to X, all X test registers have completed the test serial data The data correctness check of the data is performed, and the delay parameter is confirmed to be valid; wherein, the delay parameter is used to adjust the signal transmission delay between the controlled end chip and the master control end chip. The method for increasing the transmission rate of a serial peripheral interface as claimed in claim 1, further comprising the following steps: (6) the host chip and the slave chip start to perform at least one serial data through the serial peripheral interface transmission operation. The method for increasing the transmission rate of a serial peripheral interface according to claim 1, wherein, when the host chip reads the test serial data from the test register through the serial peripheral interface, it does not The test performs the data correctness check with a first tuple of serial data. The method for increasing the transmission rate of a serial peripheral interface according to claim 1, wherein each of the X test registers has a register address, and the X register addresses are set by the host chip. The method for increasing the transmission rate of a serial peripheral interface according to claim 4, wherein the register addresses are different from each other, and the serial data for testing are the same or different from each other. A data transmission circuit, comprising a master chip, at least one slave chip, and at least one serial peripheral interface coupled between the master chip and the at least one slave chip; characterized in that: Each of the controlled end chips is internally provided with X test registers, and the host chip executes a transmission rate improvement method to increase the transmission rate of a serial data transmission of the serial peripheral interface; the transmission rate improvement method Including: (1) making the host chip write a serial data for testing to the selected one of the at least one slave chip through the serial peripheral interface selected by the at least one serial peripheral interface The ith of the X test registers of the controlled end chip, and then the serial data for testing is read out from the ith test register through the serial peripheral interface; wherein, X is a positive integer, starting from i The initial value is 1, and i≦X; (2) Perform a data correctness check on the read serial data for testing, and perform the following steps (3) if the data correctness check fails , and if the data correctness check is passed, execute the following step (4); (3) adjust a delay parameter to the selected slave chip through the master chip, and then repeat the step (2) ); (4) In the case that i is less than X, the host chip writes a test serial data to the i+1th of the X test registers through the selected serial peripheral interface, and then passes The selected serial peripheral interface reads the test serial data from the i+1th test register, and then repeats the step (3); and when i is equal to X, the X test registers are all The data correctness check of the serial data for the test has been completed, and the delay parameter is confirmed to be valid; and (5) the host chip and the selected slave chip start to pass through the selected serial peripheral interface Carry out at least one serial data transmission operation; Wherein, the delay parameter is used to adjust the signal transmission delay between the controlled end chip and the master control end chip. The data transmission circuit of claim 6, wherein when the host chip reads the test serial data from the test register through the selected serial peripheral interface, the read test serial data is not The first tuple of one of the row data performs the data correctness check. The data transmission circuit of claim 6, wherein each of the X test registers has a register address, each of the register addresses is different from each other, and each of the test serial data is the same or different from each other. An information processing device has a central processing unit and the data transmission circuit according to any one of the claims 6 to 8, wherein the central processing unit is used for communicating with the data transmission circuit. The information processing device according to claim 9, which is an electronic device selected from the group consisting of a smart phone, a tablet computer, a notebook computer, an all-in-one computer, a smart watch and an access control device.

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