CN114443524A - Data transmission method, system, storage medium and equipment - Google Patents
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Abstract
The invention provides a data transmission method, a system, a storage medium and a device, wherein the method comprises the following steps: writing data to be sent into the main equipment, dividing the data to be sent into a plurality of data groups, setting an initial count value of a counter based on the number of the plurality of data groups, and sequentially moving the plurality of data groups into a first FIFO memory; in response to the current data group being moved to the first FIFO memory, decrementing the count value of the counter by one and moving the current data group out of the first FIFO memory and to the slave device; in response to receiving the current data set from the device, moving the current data set into a second FIFO memory and processing the current data set in the second FIFO memory; transmitting, by the slave device, a process complete signal to the master device in response to the process being complete; in response to the master device receiving the process complete signal, the count value of the counter is incremented by one. The invention improves the efficiency and reliability of data transmission.
Description
Technical Field
The present invention relates to the field of information transmission technologies, and in particular, to a data transmission method, system, storage medium, and device.
Background
A Serial Peripheral Interface (SPI) is a full-duplex synchronous Serial communication protocol, and is composed of a master device and one or more slave devices, where the master device starts synchronous communication with the slave devices to complete data exchange. The standard SPI uses only 4 pins to control data transmission, saving the pin count of the chip, and simultaneously saving space in layout for a PCB (Printed Circuit Board). Due to this simple and easy-to-use feature, SPI technology is now increasingly integrated on a chip.
The SPI specifies that communication between two SPI devices must be controlled by a Master device (Master) to a Slave device (Slave). A Master device can control a plurality of slave devices by providing a clock and chip-selecting the slave devices, the SPI protocol also provides that the clock of the slave devices is provided to the slave devices by the Master device through the SCK pin, the slave devices themselves cannot generate or control the clock, and the slave devices cannot normally operate without the clock. The SPI interface operates in a master-slave mode, which typically has a master device and one or more slave devices, and includes the following four signals:
(1) SDO/MOSI: master device data out, slave device data in;
(2) SDI/MISO: master device data input, slave device data output;
(3) SCLK: a clock signal generated by the master device;
(4) NSS/CS/SS: the slave device enabling signal is controlled by the master device, when a plurality of slave devices exist, because each slave device has a chip selection pin connected to the master device, when the master device communicates with a certain slave device, the level of the chip selection pin corresponding to the slave device needs to be pulled down or pulled up.
In 4 signal lines CS, CLK, MISO and MOSI between SPI master-slave devices, data transmission is carried out on MISO and MOSI, both sides are shift registers, the master device sends one bit of data and receives one bit of data at the same time, and when 8 bit of data transmission is finished, 8 bit of data is also received. Intuitively, the 8-bit shift registers on two sides exchange data, but each exchange is one-bit data, and 8 cycles complete the transmission of 8-bit data; moreover, a credit mechanism is lacked between the master device and the slave device, and the reliability of data transmission is difficult to guarantee.
Disclosure of Invention
In view of this, an object of the present invention is to provide a data transmission method, a system, a storage medium and a device, so as to solve the problems in the prior art that the data transmission efficiency between a master device and a slave device in an SPI protocol is low and the reliability is difficult to guarantee.
Based on the above purpose, the present invention provides a data transmission method, which comprises the following steps:
writing data to be sent into the main equipment, dividing the data to be sent into a plurality of data groups, setting an initial count value of a counter based on the number of the plurality of data groups, and sequentially moving the plurality of data groups into a first FIFO memory;
in response to the current data group being moved to the first FIFO memory, decrementing the count value of the counter by one and moving the current data group out of the first FIFO memory and to the slave device;
in response to receiving the current data set from the device, moving the current data set into a second FIFO memory and processing the current data set in the second FIFO memory;
transmitting, by the slave device, a process complete signal to the master device in response to the process being complete;
in response to the master device receiving the process complete signal, the count value of the counter is incremented by one.
In some embodiments, dividing the data to be transmitted into a plurality of data groups comprises:
the data to be transmitted is divided into a plurality of data groups based on the size of the data to be transmitted and the channel width of the first shift register of the master device.
In some embodiments, sequentially shifting the plurality of data groups into the first FIFO memory comprises:
the plurality of data groups are sequentially shifted into the first FIFO memory through the first shift register.
In some embodiments, shifting out and transmitting the current data group from the first FIFO memory to the slave device comprises:
the current data burst is shifted out of the first FIFO memory by the first shift register and transmitted to the slave device via the MISO pin.
In some embodiments, shifting the current data group into the second FIFO memory comprises:
the current data set is shifted into the second FIFO memory by means of a second shift register of the slave device.
In some embodiments, the method further comprises:
in response to the count value of the counter being zero, the master device no longer moves the data groups into the first FIFO memory.
In some embodiments, the method further comprises:
in response to receiving the current data set from the device, determining whether the current data set is correct;
in response to the current data group error, moving the erroneous current data group into the second FIFO memory and sending a data error signal to the master device;
the count value of the counter is maintained in response to the master device receiving the data error signal.
In another aspect of the present invention, a data transmission system is further provided, including:
the data group moving module is configured to write data to be sent into the main device, divide the data to be sent into a plurality of data groups, set an initial count value of the counter based on the number of the plurality of data groups, and sequentially move the plurality of data groups into the first FIFO memory;
a data set transfer module configured to decrement the count value of the counter by one and to move the current data set out of the first FIFO memory and transfer it to the slave device in response to the current data set being moved to the first FIFO memory;
a processing module configured to, in response to receiving a current data set from the device, move the current data set into the second FIFO memory and process the current data set in the second FIFO memory;
a signal sending module configured to send a processing completion signal to the master device by the slave device in response to the processing completion; and
and the counting value adding module is configured for responding to the receiving of the processing completion signal by the main equipment and adding one to the counting value of the counter.
In yet another aspect of the present invention, a computer-readable storage medium is also provided, storing computer program instructions, which when executed by a processor, implement the above-described method.
In yet another aspect of the present invention, a computer device is further provided, which includes a memory and a processor, the memory storing a computer program, which when executed by the processor performs the above method.
The invention has at least the following beneficial technical effects:
the data to be transmitted is divided into a plurality of data groups, namely the data is transmitted by taking the groups as units, and the FIFO memory is added in the data transmission process, so that the data transmission efficiency is improved, and the reliability of data transmission is ensured by utilizing the FIFO memory; through setting up the counter, can carry out two-way control to the data that master equipment sent and the data that slave unit received to guarantee data accurate transmission, not missed.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
Fig. 1 is a schematic diagram of a data transmission method according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a data transmission system provided according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a computer-readable storage medium for implementing a data transmission method according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a hardware structure of a computer device for executing a data transmission method according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two non-identical entities with the same name or different parameters, and it is understood that "first" and "second" are only used for convenience of expression and should not be construed as limiting the embodiments of the present invention. Furthermore, the terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements does not include all of the other steps or elements inherent in the list.
In view of the above object, a first aspect of the embodiments of the present invention provides an embodiment of a data transmission method. Fig. 1 is a schematic diagram illustrating an embodiment of a data transmission method provided by the present invention. As shown in fig. 1, the embodiment of the present invention includes the following steps:
step S10, writing data to be sent into the main device, dividing the data to be sent into a plurality of data groups, setting an initial count value of a counter based on the number of the data groups, and sequentially moving the data groups into a first FIFO memory;
step S20, in response to the current data group being moved to the first FIFO memory, decrementing the count value of the counter by one, and moving the current data group out of the first FIFO memory and transmitting to the slave device;
step S30, in response to receiving the current data group from the device, moving the current data group into the second FIFO memory, and processing the current data group in the second FIFO memory;
step S40, responding to the completion of the processing, the slave device sends a processing completion signal to the master device;
step S50, in response to the master device receiving the processing completion signal, increments the count value of the counter by one.
FIFO (First Input First output) refers to First-in First-out in short. Due to the rapid development of microelectronic technology, the capacity of a new generation FIFO chip is larger and smaller, and the price is cheaper and cheaper. As a novel large-scale integrated circuit, the FIFO chip is gradually and widely applied to high-speed data acquisition, high-speed data processing, high-speed data transmission and multi-machine processing systems due to the characteristics of flexibility, convenience and high efficiency. FIFO memories are widely used in system design for the purpose of increasing data transmission rates, processing a large number of data streams, and matching systems having different transmission rates, thereby improving system performance. The FIFO memory is a first-in first-out double-port buffer, i.e. the first data that enters it is shifted out first, one of which is the input port of the memory and the other is the output port of the memory. For monolithic FIFOs, there are two main structures: a trigger guide structure and a zero guide transmission structure. The FIFO of the burst oriented transmission structure is formed of a register array, and the FIFO of the zero oriented transmission structure is formed of a dual-port RAM (Random Access Memory) having read and write address pointers. The FIFO memory is divided into a write-only area and a read-only area. The read operation and the write operation can be performed asynchronously, and the data written on the write area is read from the area at the read end in the order of writing, similar to a buffer that absorbs the speed difference between the write end and the read end.
The embodiment of the invention divides the data to be transmitted into a plurality of data groups, namely, the data is transmitted by taking the groups as units, and the FIFO memory is added in the data transmission process, so that the data transmission efficiency can be improved and the reliability of the data transmission can be ensured by utilizing the FIFO memory; through setting up the counter, can carry out two-way control to the data that master equipment sent and the data that slave unit received to guarantee data accurate transmission, not missed.
In some embodiments, dividing the data to be transmitted into a plurality of data groups comprises: the data to be transmitted is divided into a plurality of data groups based on the size of the data to be transmitted and the channel width of the first shift register of the master device.
In this embodiment, the channel width of the first shift register may be 8 bits, or may be set according to other data transmission requirements. By dividing the data to be transmitted into data groups according to the channel width of the first shift register, the data to be transmitted can be transmitted or received in units of data groups, which is beneficial to improving the data transmission efficiency.
In some embodiments, sequentially shifting the plurality of data groups into the first FIFO memory comprises: the plurality of data groups are sequentially shifted into the first FIFO memory through the first shift register.
In some embodiments, shifting out and transmitting the current data group from the first FIFO memory to the slave device comprises: the current data burst is shifted out of the first FIFO memory by the first shift register and transmitted to the slave device via the MISO pin.
In the above embodiments, the data in the first FIFO memory is shifted in and out by means of the first shift register.
MISO (Master In & Slave Out) is applied In SPI. The SPI (Serial Peripheral Interface) is a synchronous, full-duplex, master-slave Interface, and data from the master or slave is synchronized at the rising or falling edge of the clock, and the master and slave can transmit data at the same time. The SPI interface can be a 3-wire type or a 4-wire type, and a 4-wire SPI interface is commonly used. The 4-wire SPI device has four signals: clocks (SPI CLK, SCLK), Chip Select (CS), master output & slave input (MOSI), master input & slave output (MISO). The device that generates the clock signal is called the host. Data transmitted between the master and the slave is synchronized with a clock generated by the master. The SPI interface can have only one master, but can have one or more slaves. The chip select signal from the master is used to select the slave.
MOSI and MISO are data lines. The MOSI sends data from the master to the slave, and the MISO sends data from the slave to the master. To start SPI communication, the master must send a clock signal and select a slave by enabling the CS signal. The chip select is typically an active low signal. Therefore, the master must send a logic 0 on this signal to select the slave. The SPI is a full duplex interface, and the master and slave can simultaneously transmit data through MOSI and MISO lines, respectively. During SPI communication, data is transmitted (serially shifted out onto MOSI/SDO bus) and received (data on MISO/SDI bus sampled or read in) simultaneously.
In some embodiments, shifting the current data group into the second FIFO memory comprises: the current data set is shifted into the second FIFO memory by means of a second shift register of the slave device.
In this embodiment, the data in the second FIFO memory is shifted in and out by means of the second shift register.
In some embodiments, the method further comprises: in response to the count value of the counter being zero, the master device no longer moves the data groups into the first FIFO memory.
In this embodiment, if the count value of the counter is zero, the master device does not send any more data and therefore does not move data groups into the first FIFO memory.
In some embodiments, the method further comprises: in response to receiving the current data set from the device, determining whether the current data set is correct; in response to the current data group error, moving the erroneous current data group into the second FIFO memory and sending a data error signal to the master device; the count value of the counter is maintained in response to the master device receiving the data error signal.
In this embodiment, if the current data group is erroneous, the current data group may be cached in the local FIFO (i.e. the second FIFO memory), or a memory dedicated to storing erroneous data may be provided, and the erroneous current data group may be stored in the memory.
The following is a specific embodiment of the data transmission method of the present invention:
before Data is transmitted, the Data to be transmitted is written into the Tx-Data register of the master device, the Data is shifted into the FIFO by the shift register according to the channel width, then the Data is shifted out by the shift register and is transmitted to the MOSI pin of the slave device through the MISO pin, and the shift register of the slave device shifts the received Data into the FIFO of the slave device. At the same time, the data in the FIFO of the slave device is transmitted to the MISO of the master device through the MISO of the slave device according to the size (Channel-Width) of the data received each time, and the shift register of the master device shifts the data received from the MISO of the master device into the FIFO.
Specifically, each time a plurality of 8-bit data are buffered, a counter is designed at the master device, and after each 8-bit data is transmitted, the counter is decremented by 1, and the counter is transmitted at most for how many times. When the counter is 0, indicating no credit, the master can no longer send data. For example, a start counter of 4 indicates that the master can send four times a burst. Similarly, each time the slave device finishes processing data, the slave device raises a processing completion signal to the master device, and when the master device finds that the signal is raised, the counter is increased by 1, which indicates that the master device can send data once again at the moment. Thus, the efficiency of data transmission can be improved through the pipeline operation.
This process complete signal may be sent when the received data is correct. When the received data is wrong, a data error signal is returned so as to record which data is wrong during transmission, so that the wrong data can be processed later. When data is wrong, the wrong data can be cached in the local FIFO, when the next data comes again, the wrong data at the last time can be covered to ensure the available cache space, or the wrong data can be removed, or the wrong data can be directly thrown away without being cached in the FIFO.
In a second aspect of the embodiments of the present invention, a data transmission system is further provided. Fig. 2 is a schematic diagram of an embodiment of a data transmission system provided in the present invention. As shown in fig. 2, a data transmission system includes: a data group moving module 10 configured to write data to be sent into the main device, divide the data to be sent into a plurality of data groups, set an initial count value of the counter based on the number of the plurality of data groups, and sequentially move the plurality of data groups into the first FIFO memory; a data group transfer module 20 configured to decrement the count value of the counter by one in response to the current data group being moved to the first FIFO memory, and to move the current data group out of the first FIFO memory and transfer to the slave device; a processing module 30 configured to, in response to receiving a current data set from the device, move the current data set into the second FIFO memory and process the current data set in the second FIFO memory; a signal transmitting module 40 configured to transmit a process completion signal from the slave device to the master device in response to completion of the process; and a count value incrementing module 50 configured to increment a count value of the counter in response to the master device receiving the processing complete signal.
In some embodiments, the data group moving module 10 includes a data dividing module configured to divide the data to be transmitted into a plurality of data groups based on the size of the data to be transmitted and the channel width of the first shift register of the master device.
In some embodiments, the data group shifting module 10 comprises a shift-in first FIFO memory module configured to sequentially shift the plurality of data groups into the first FIFO memory through the first shift register.
In some embodiments, the data burst transfer module 20 comprises a slave device transfer module configured to shift the current data burst out of the first FIFO memory by the first shift register and transfer to the slave device through the MISO pin.
In some embodiments, the processing module 30 comprises a shift-in second FIFO memory module configured to shift the current data group into the second FIFO memory through a second shift register of the slave device.
In some embodiments, the system further comprises a count clear module configured to respond to the count value of the counter being zero, the master device no longer moving the data group into the first FIFO memory.
In some embodiments, the system further includes a dataset error module configured to determine, in response to receiving the current dataset from the device, whether the current dataset is correct; in response to the current data group error, moving the erroneous current data group into the second FIFO memory and sending a data error signal to the master device; the count value of the counter is maintained in response to the master device receiving the data error signal.
In a third aspect of the embodiment of the present invention, a computer-readable storage medium is further provided, and fig. 3 illustrates a schematic diagram of a computer-readable storage medium implementing a data transmission method according to an embodiment of the present invention. As shown in fig. 3, the computer-readable storage medium 3 stores computer program instructions 31. The computer program instructions 31 when executed by a processor implement the steps of:
writing data to be sent into the main equipment, dividing the data to be sent into a plurality of data groups, setting an initial count value of a counter based on the number of the plurality of data groups, and sequentially moving the plurality of data groups into a first FIFO memory;
in response to the current data group being moved to the first FIFO memory, decrementing the count value of the counter by one and moving the current data group out of the first FIFO memory and to the slave device;
in response to receiving the current data set from the device, moving the current data set into a second FIFO memory and processing the current data set in the second FIFO memory;
transmitting, by the slave device, a process complete signal to the master device in response to the process being complete;
in response to the master device receiving the process complete signal, the count value of the counter is incremented by one.
In some embodiments, dividing the data to be transmitted into a plurality of data groups comprises: the data to be transmitted is divided into a plurality of data groups based on the size of the data to be transmitted and the channel width of the first shift register of the master device.
In some embodiments, sequentially shifting the plurality of data groups into the first FIFO memory comprises: the plurality of data groups are sequentially shifted into the first FIFO memory through the first shift register.
In some embodiments, shifting out and transmitting the current data group from the first FIFO memory to the slave device comprises: the current data burst is shifted out of the first FIFO memory by the first shift register and transmitted to the slave device via the MISO pin.
In some embodiments, shifting the current data group into the second FIFO memory comprises: the current data set is shifted into the second FIFO memory by means of a second shift register of the slave device.
In some embodiments, the method further comprises: in response to the count value of the counter being zero, the master device no longer moves the data groups into the first FIFO memory.
In some embodiments, the method further comprises: in response to receiving the current data set from the device, determining whether the current data set is correct; in response to the current data group error, moving the erroneous current data group into the second FIFO memory and sending a data error signal to the master device; the count value of the counter is maintained in response to the master device receiving the data error signal.
It shall be understood that all embodiments, features and advantages set forth above with respect to the data transmission method according to the invention apply equally, without conflict with each other, to the data transmission system and to the storage medium according to the invention.
In a fourth aspect of the embodiments of the present invention, there is further provided a computer device, including a memory 402 and a processor 401 as shown in fig. 4, where the memory 402 stores therein a computer program, and the computer program, when executed by the processor 401, implements the method of any one of the above embodiments.
Fig. 4 is a schematic diagram of a hardware structure of an embodiment of a computer device for executing the data transmission method according to the present invention. Taking the computer device shown in fig. 4 as an example, the computer device includes a processor 401 and a memory 402, and may further include: an input device 403 and an output device 404. The processor 401, memory 402, input device 403, and output device 404 may be connected by a bus or other means, as exemplified by the bus connection in fig. 4. The input device 403 may receive input numeric or character information and generate key signal inputs related to user settings and function control of the data transmission system. The output device 404 may include a display device such as a display screen.
The memory 402, which is a non-volatile computer-readable storage medium, may be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as program instructions/modules corresponding to the data transmission method in the embodiments of the present application. The memory 402 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created by use of a data transmission method, and the like. Further, the memory 402 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some embodiments, memory 402 may optionally include memory located remotely from processor 401, which may be connected to local modules over a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The processor 401 executes various functional applications of the server and data processing, i.e., implements the data transmission method of the above-described method embodiment, by running the nonvolatile software program, instructions, and modules stored in the memory 402.
Finally, it should be noted that the computer-readable storage medium (e.g., memory) herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of example, and not limitation, nonvolatile memory can include Read Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM), which can act as external cache memory. By way of example and not limitation, RAM is available in a variety of forms such as synchronous RAM (DRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to comprise, without being limited to, these and other suitable types of memory.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.
The various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed with the following components designed to perform the functions herein: a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP, and/or any other such configuration.
The foregoing are exemplary embodiments of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items. The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (10)
1. A data transmission method, comprising the steps of:
writing data to be sent into main equipment, dividing the data to be sent into a plurality of data groups, setting an initial count value of a counter based on the number of the data groups, and sequentially moving the data groups into a first FIFO memory;
in response to a current data group being moved to the first FIFO memory, decrementing the count value of the counter by one and moving the current data group out of the first FIFO memory and to a slave device;
in response to receiving the current data set from the slave device, moving the current data set into a second FIFO memory and processing the current data set in the second FIFO memory;
transmitting, by the slave device, a process complete signal to the master device in response to completion of the process;
in response to the master device receiving the process complete signal, incrementing a count value of the counter by one.
2. The method of claim 1, wherein dividing the data to be transmitted into a plurality of data groups comprises:
and dividing the data to be transmitted into a plurality of data groups based on the size of the data to be transmitted and the channel width of a first shift register of the master device.
3. The method of claim 2, wherein sequentially shifting the plurality of data groups into a first FIFO memory comprises:
the plurality of data groups are sequentially shifted into a first FIFO memory through the first shift register.
4. The method of claim 2 or 3, wherein the moving the current data set out of the first FIFO memory and to a slave device comprises:
the current data group is shifted out of the first FIFO memory by the first shift register and transmitted to the slave device through the MISO pin.
5. The method of claim 1, wherein shifting the current data group into a second FIFO memory comprises:
shifting the current data group into a second FIFO memory through a second shift register of the slave device.
6. The method of claim 1, further comprising:
in response to the count value of the counter being zero, the master device no longer moves data groups into the first FIFO memory.
7. The method of claim 1, further comprising:
in response to the slave device receiving the current data set, determining whether the current data set is correct;
in response to the current data set error, moving the erroneous current data set into the second FIFO memory and sending a data error signal to the master device;
maintaining the count value of the counter unchanged in response to the master device receiving the data error signal.
8. A data transmission system, comprising:
the data group moving module is configured to write data to be sent into the main device, divide the data to be sent into a plurality of data groups, set an initial count value of a counter based on the number of the plurality of data groups, and sequentially move the plurality of data groups into the first FIFO memory;
a data set transfer module configured to decrement a count value of the counter by one and to move a current data set out of the first FIFO memory and transfer the current data set to a slave device in response to the current data set being moved to the first FIFO memory;
a processing module configured to move the current data group into a second FIFO memory and process the current data group in the second FIFO memory in response to the slave device receiving the current data group;
a signal transmission module configured to transmit, by the slave device, a process completion signal to the master device in response to completion of the process; and
a count value adding module configured to add one to the count value of the counter in response to the master device receiving the processing completion signal.
9. A computer-readable storage medium, characterized in that computer program instructions are stored which, when executed by a processor, implement the method according to any one of claims 1-7.
10. A computer device comprising a memory and a processor, characterized in that the memory has stored therein a computer program which, when executed by the processor, performs the method according to any one of claims 1-7.
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