CN100386861C - 用于例如集成电路的薄层的制造方法 - Google Patents
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Abstract
通过3个步骤方法形成用于比如铁电容器等结构的层，这些步骤包括：(i)在一部分或整个结构(21)上涂布润湿(23)；(ii)在润湿层(23)上涂布第二种材料形成的第二层(25)；以及(iii)通过化学反应将第二种材料进行转化。在一个实施例中，此第二种材料是Al，而步骤(iii)包括将Al层(25)氧化，形成Al2O3层(27)。优选用即使在基片的高宽高比区也具有良好阶梯覆盖性的方法涂布此润湿层(21)，即使该方法的沉积速度可能比较低。优选由第二种材料在其上面具有高迁移率的材料形成润湿层(21)，这样使得铝层和随后的Al2O3层具有比较均匀的厚度。在步骤(iii)之前可以有一个提高第二种材料的侧向迁移率的步骤，比如通过热处理。
Description
技术领域
本发明涉及在比如集成电路的器件中具有很高保形性的层的制造技术，还涉及包括由此方法形成的层的器件。
背景技术
在设计集成电路时有许多情况下希望制造一层材料层。比如，已知在集成电路中提供一层氧化铝Al2O3层作为比如阻隔化合物的不希望出现的扩散的层，这些化合物是例如副产物，如在包括铁电容器(ferro-capacitor)在内的半导体器件“后端加工”过程中形成的氢。通常使用Al2O3靶通过直接溅镀来涂布此Al2O3。然而，这个技术的缺点是，在具有陡度(即具有高宽高比)的集成电路区难以产生厚度均匀的阻隔层。
在图1中说明了这个问题，该图示意性地显示出一部分集成电路的横截面，该集成电路具有至少一个通常在图1的水平方向上展开的晶片(未显示)表面上形成的铁电容器(一般还有许多其它元件)。该铁电容器包括夹在两层导体层3、5之间的一层铁电材料1。该层3与触点7接触。该结构的部分9、13是由SiO2形成的，提供两层Al2O3层16、17作为阻隔层。层16、17的厚度在部分15处急剧减少，在这里它所覆盖的表面相对于晶片平面具有最大的陡度，所以在此区域，阻隔效果最差。不幸的是，比较薄的部分15位于对铁电容器操作十分关键的区域，这样就存在着为氢气向电容器中扩散提供通道的风险。
保证在所有区域内层16、17的厚度都适当的一个简单的方法就是使层16、17在整个表面上更厚。然而，由于这样会在制造集成电路时对后续加工引起不希望的副作用，因此形成厚层16，17有其不利之处。比如，在刻蚀触点7的接触孔的过程中进行反应离子刻蚀(RIE)时会有困难。
发明内容
本发明力图解决如上所述的问题，具体而言是要提供一个有用的新方法，用来在比如集成电路等器件中制造Al2O3层。
一般说来，本发明建议，通过3步方法得到此Al2O3层，这些步骤包括(i)在结构(它可以是集成电路基片或在基片上形成的元件)的至少一部分上涂布第一种材料形成的第一层；(ii)在第一层上涂布第二种材料形成的第二层，以及(iii)将第二种材料进行改性。
因此，本发明涉及形成一个层以覆盖至少一部分结构的方法，该方法依次包括如下步骤：
(i)形成第一种材料形成的底层覆盖在至少一部分结构上，其中被覆盖的所述一部分结构包括在基片上形成的至少一个元件，其中底层的沉积通过在包括至少一个元件的陡峭区的被覆盖的所述一部分结构上提供良好阶梯覆盖的方法进行；
(ii)在所述底层上形成第二种材料形成的第二层，所述第二层相对于底层具有高表面迁移速率，因此使第二层在包括所述至少一个元件的陡峭区的被覆盖的所述一部分结构上具有基本均匀厚度，以及
(iii)通过化学反应将第二种材料进行改性以在包括所述至少一个元件的陡峭区的被覆盖的所述一部分结构上形成具有基本均匀厚度的扩散路径阻隔层。
在一个优选实施方案中，所述底层通过高保形性层沉积方法形成，优选所述底层通过原子层沉积法或平行校正溅镀法形成。
在此，第一层叫做“润湿”层，因为它能增强沉积在其上的材料的侧向迁移率，这很象促进水在一个疏水表面上迁移的层。因此，涂布第二层不需要导致高度阶梯式覆盖的方法，比如它可能是一种较低成本的方法。由润湿层所引发的侧向迁移效果是原则上决定第二种材料阶梯式覆盖性的因素，而不是决定如何涂布第二层的因素。因此，润湿层优选通过即使在基片的陡峭区也具有良好阶梯式覆盖效果的方法涂布，比如用具有高平行校正的沉积方法。平行校正是一种溅镀方法，在此方法中，材料以相对于晶片表面垂直的角度到达晶片上。材料可通过厚蜂窝栅极进行校准，此栅极阻挡了角度偏离的金属原子，或者通过使这些金属原子电离并将它们吸引到晶片上。
在步骤(iii)之前可以任选地加入一个步骤，在此步骤中通过比如提高温度、曝露在光子当中等方法来提高第二种材料的侧向迁移率。
可以用具有比较低沉积速度的方法(比如，在本发明中，该润湿层可以形成为不厚于大约
(10nm)，优选厚度为大约
(5nm))来形成此润湿层，还优选在基片上形成比较均匀的润湿层。此润湿层优选选择为使第二种材料在其表面上具有高表面迁移速度的材料。
在本发明的一个特定的实施例中，第二种材料是Al，而步骤(iii)是Al被氧化形成Al2O3。在此情况下，润湿层优选选择为使Al在其表面上具有高表面迁移速度的材料，比如Ti或Nb或者这两种的结合。
优选通过溅镀形成此Al层。由于Al在润湿层上具有高的侧向迁移率，形成的Al层可以比较均匀。其厚度可以在
(10～30nm)的范围内，或者更优选为大约
(20nm)。
优选在高温下，比如在大约450℃下进行此氧化步骤。
附图说明
下面将参照如下的附图，仅作为说明而详细地叙述成为本发明一个实施方案的一种方法，其中：
图1显示一种已知的铁电容器结构的构造；
图2显示在本实施方案的第一步中沉积润湿层；
图3显示在本实施方案的第二步中，在该润湿层上沉积Al层；以及
图4显示在本实施方案的第三步中，Al层进行氧化。
具体实施方式
图2显示了在其至少一部分上形成Al2O3层的结构21(比如任选具有诸如在其上面形成的铁电容器等元件的基片)。
如图2所示，在本实施方案的第一步中，在基本整个基片21上形成具有大约5nm的均匀厚度的诸如Ti或Nb等材料形成的底层23(润湿层)。可以通过溅镀法、MOCVD(金属有机物化学气相沉积法)或ALD(原子层沉积法)进行此沉积。具体而言，可通过平行校正的方法来进行，因为虽然平行校准法一般会降低沉积速度，但底层23的厚度是无须太厚的。虽然优选使用Ti或Nb，但也可以使用其他材料，优选是Al在其表面上具有高表面迁移率的材料。
如图3所示，在本实施方案的第二步中，在底层23上沉积一层Al(或者更一般地包括金属Al组分)层25。可以通过溅镀法、或通过MOCVD、LPCVD或等离子体CVD进行此沉积。因为润湿层23具有高表面迁移率，即使在该结构的陡峭区上，Al层25也具有基本上均匀的大约20nm的厚度。优选以比形成底层23时的沉积速度更高的速度进行此沉积。
在本实施方案的第三步中，通过将其曝露在高温，比如在450℃的含氧气氛下，将Al层25氧化，转化为在底层23和结构21上具有低迁移率的Al2O3层27。底层一般将经受此处理。
虽然仅叙述了本发明的一个实施方案，对于具有专业技能的读者不言而喻的是，在本发明的范围内，许多变化都是可能的。
Claims (12)
1.形成一个层以覆盖至少一部分结构的方法，该方法依次包括如下步骤：
(i)形成第一种材料形成的底层覆盖在至少一部分结构上，其中被覆盖的所述一部分结构包括在基片上形成的至少一个元件，其中底层的沉积通过在包括至少一个元件的陡峭区的被覆盖的所述一部分结构上提供良好阶梯覆盖的方法进行；
(ii)在所述底层上形成第二种材料形成的第二层，该第二种材料以高于第一种材料的沉积速度通过溅镀沉积，所述第二层相对于底层具有高表面迁移速率，因此使第二层在包括所述至少一个元件的陡峭区的被覆盖的所述一部分结构上具有基本均匀厚度，以及
(iii)通过氧化反应将第二种材料进行改性以在包括所述至少一个元件的陡峭区的被覆盖的所述一部分结构上形成具有基本均匀厚度的扩散路径阻隔层。
2.根据权利要求1所述的方法，该方法在步骤(iii)的前面进一步包括提高第二种材料在第一种材料上的侧向迁移率的步骤。
3.根据权利要求2所述的方法，其中所述提高第二种材料在第一种材料上的侧向迁移率的步骤包括提高温度。
4.根据权利要求2所述的方法，其中所述提高第二种材料在第一种材料上的侧向迁移率的步骤包括将第二种材料曝露在光子中。
5.根据权利要求1所述的方法，其中所述第二种材料包括Al，而步骤(iii)包括使此Al层氧化，以形成Al2O3层。
6.根据权利要求1所述的方法，其中所述底层通过高保形性层沉积方法形成。
7.根据权利要求6所述的方法，其中所述底层通过原子层沉积法形成。
8.根据权利要求6所述的方法，其中所述底层通过平行校正溅镀法形成。
9.根据权利要求1所述的方法，其中所述第一种材料包括Ti和Nb中的至少一种。
10.一种集成电路，其特征在于其包括用根据权利要求1所述的方法形成的层。
11.一种集成电路，其特征在于其包括用根据权利要求5所述的方法形成的Al2O3层。
12.根据权利要求11所述的集成电路，其中所述Al2O3层覆盖在至少一部分铁电电容器上。
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/279,743 | 2002-10-23 | ||
| US10/279,743 US20040087080A1 (en) | 2002-10-23 | 2002-10-23 | Methods for producing thin layers, such as for use in integrated circuits |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1497706A CN1497706A (zh) | 2004-05-19 |
| CN100386861C true CN100386861C (zh) | 2008-05-07 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2003101017389A Expired - Fee Related CN100386861C (zh) | 2002-10-23 | 2003-10-22 | 用于例如集成电路的薄层的制造方法 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US20040087080A1 (zh) |
| CN (1) | CN100386861C (zh) |
| DE (1) | DE10349747B4 (zh) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5055158A (en) * | 1990-09-25 | 1991-10-08 | International Business Machines Corporation | Planarization of Josephson integrated circuit |
| US5877087A (en) * | 1995-11-21 | 1999-03-02 | Applied Materials, Inc. | Low temperature integrated metallization process and apparatus |
| CN1222765A (zh) * | 1998-01-06 | 1999-07-14 | 三星电子株式会社 | 半导体器件的电容器及其形成方法 |
| CN1267912A (zh) * | 1999-03-23 | 2000-09-27 | 株式会社东芝 | 半导体装置及其制造方法 |
| CN1310477A (zh) * | 2000-02-22 | 2001-08-29 | 松下电子工业株式会社 | 半导体存储器件 |
| US6307267B1 (en) * | 1997-12-26 | 2001-10-23 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
| KR20020006086A (ko) * | 2000-07-11 | 2002-01-19 | 박종섭 | 알루미나 스퍼터링 증착을 이용한 반도체 메모리 소자제조 방법 |
-
2002
- 2002-10-23 US US10/279,743 patent/US20040087080A1/en not_active Abandoned
-
2003
- 2003-10-22 CN CNB2003101017389A patent/CN100386861C/zh not_active Expired - Fee Related
- 2003-10-23 DE DE10349747A patent/DE10349747B4/de not_active Expired - Fee Related
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5055158A (en) * | 1990-09-25 | 1991-10-08 | International Business Machines Corporation | Planarization of Josephson integrated circuit |
| US5877087A (en) * | 1995-11-21 | 1999-03-02 | Applied Materials, Inc. | Low temperature integrated metallization process and apparatus |
| US6307267B1 (en) * | 1997-12-26 | 2001-10-23 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
| CN1222765A (zh) * | 1998-01-06 | 1999-07-14 | 三星电子株式会社 | 半导体器件的电容器及其形成方法 |
| CN1267912A (zh) * | 1999-03-23 | 2000-09-27 | 株式会社东芝 | 半导体装置及其制造方法 |
| CN1310477A (zh) * | 2000-02-22 | 2001-08-29 | 松下电子工业株式会社 | 半导体存储器件 |
| KR20020006086A (ko) * | 2000-07-11 | 2002-01-19 | 박종섭 | 알루미나 스퍼터링 증착을 이용한 반도체 메모리 소자제조 방법 |
Also Published As
| Publication number | Publication date |
|---|---|
| DE10349747B4 (de) | 2007-02-15 |
| US20040087080A1 (en) | 2004-05-06 |
| CN1497706A (zh) | 2004-05-19 |
| DE10349747A1 (de) | 2004-05-13 |
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