CN100378956C - Method of manufacturing dielectric layer of grid - Google Patents
Method of manufacturing dielectric layer of grid Download PDFInfo
- Publication number
- CN100378956C CN100378956C CNB2005100920438A CN200510092043A CN100378956C CN 100378956 C CN100378956 C CN 100378956C CN B2005100920438 A CNB2005100920438 A CN B2005100920438A CN 200510092043 A CN200510092043 A CN 200510092043A CN 100378956 C CN100378956 C CN 100378956C
- Authority
- CN
- China
- Prior art keywords
- dielectric layer
- layer
- substrate
- voltage circuit
- manufacture method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 35
- 238000000034 method Methods 0.000 claims abstract description 88
- 239000000758 substrate Substances 0.000 claims abstract description 64
- 238000000059 patterning Methods 0.000 claims abstract description 16
- 229920002120 photoresistant polymer Polymers 0.000 claims description 31
- 238000005530 etching Methods 0.000 claims description 20
- 230000003647 oxidation Effects 0.000 claims description 18
- 238000007254 oxidation reaction Methods 0.000 claims description 18
- 230000004888 barrier function Effects 0.000 claims description 17
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 5
- 235000011114 ammonium hydroxide Nutrition 0.000 claims description 3
- 238000004140 cleaning Methods 0.000 claims description 3
- 238000003701 mechanical milling Methods 0.000 claims description 3
- 239000011259 mixed solution Substances 0.000 claims description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 17
- 238000002955 isolation Methods 0.000 description 16
- 239000000463 material Substances 0.000 description 11
- 230000000694 effects Effects 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229910052814 silicon oxide Inorganic materials 0.000 description 7
- 210000003323 beak Anatomy 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical group 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- -1 therefore Chemical compound 0.000 description 1
Images
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The method includes steps: first, the provided substrate can at least be divided into region of high voltage circuit and region of low voltage circuit; next, forming first dielectric layer on substrate, and the first dielectric layer is in use for grid dielectric layer in region of high voltage circuit; then, forming mask layer on the first dielectric layer, patterning the mask layer, the first dielectric layer, and the substrate in order to form groove in the substrate; forming insulating layer on the substrate to fill in the groove; removing the mask layer, and partial insulating layer to expose surface of the first dielectric layer; removing the first dielectric layer in region of low voltage circuit to expose surface of the substrate; forming second dielectric layer in substrate of the region of low voltage circuit' the thickness of the second dielectric layer is smaller than the first dielectric layer.
Description
Technical field
The present invention relates to a kind of manufacture method of semiconductor element, particularly relate to a kind of manufacture method of gate dielectric layer.
Background technology
Along with the fast development of integrated circuit fields, high-effect, high integration, low cost, the compact design of electronic products that become are made institute's pursuing target.For present semiconductor industry,, often need on same chip, produce the element of multiple function in order to meet above-mentioned target.
High voltage device and low voltage component are incorporated on the same chip, are a kind of methods that can reach above-mentioned requirements.For example use low voltage component to come the production control circuit, use high voltage device to make programmble read only memory PROM (Electrically Programmable Read-Only Memory; EPROM), flash memory (Flash Memory) or drive circuit of LCD or the like.
Yet in order to bear higher puncture voltage (breakdown voltage), the thickness of gate oxide often need be thicker than the thickness of gate oxide in the low voltage component far away greater than 200 dusts in the high voltage device.In such event, all difficult problems appear with making in the middle of the integrated process of high voltage device and low voltage component.
Figure 1A to Fig. 1 F illustrates the manufacturing process profile of existing gate oxide.Please refer to Figure 1A, prior to forming pad oxide 110 and mask layer 120 and then patterning pad oxide 110 and mask layer 120 in the common substrate 100 in high voltage circuit area 101 and low-voltage circuit district 102.
Then, please refer to Figure 1B, is mask with mask layer 120, etches groove 130 in substrate 100.Then, in substrate 100, form silicon oxide layer 140 and fill up groove 130, and cover substrate 100.Afterwards, remove silicon oxide layer 140,, define active area 145 simultaneously up to exposing mask layer 120.
Then, please refer to Fig. 1 C, carry out wet etch process, to remove mask layer 120 and pad oxide 110.Yet in the process that removes mask layer 120 and pad oxide 110, the employed etching solution of wet etch process can corrode silicon oxide layer 140, and causes the edge of groove 130 to form depression (divot) 150.
Then, please refer to Fig. 1 D, in substrate 100, form the thicker high voltage grid oxidation layer 160 of one deck.Because the formation of aforesaid depression 150 is arranged, then when forming gate oxide 160, the depression 150 of fleet plough groove isolation structure corner peripheral part can influence oxidation rate.So can be thinner than the thickness of active area 145 formed high voltage grid oxidation layers 160 at the thickness of the formed high voltage grid oxidation layer 160 of fleet plough groove isolation structure corner peripheral part, and cause the problem of uneven thickness, that is so-called gate oxide thinning (gateoxide thinning).This phenomenon can cause the electrical problem of element, reduces the reliability (reliability) of gate oxide, does not see for institute in the semiconductor technology is happy.
Afterwards, please refer to Fig. 1 E, form photoresist layer 165 and cover high voltage circuit area 101, is mask with photoresist layer 165, removes the high voltage grid oxidation layer 160 in low-voltage circuit district 102.In the high voltage grid oxidation layer 160 that removes low-voltage circuit district 102, because the material of silicon oxide layer 140 and the material of high voltage grid oxidation layer 160 are all silica, therefore, silicon oxide layer 140 also can be subjected to etching.Thus, make the fleet plough groove isolation structure (silicon oxide layer 140) in the low-voltage circuit district 102 to produce recessed 168.
Next, please refer to Fig. 1 F, remove photoresist layer 165, in substrate 100, form thin low pressure gate oxide 170 with thermal oxidation method.Continue it, in substrate 100, form doped polysilicon layer 180.After doped polysilicon layer 180 formed, the position of the fleet plough groove isolation structure corner depression 150 of high voltage circuit area 101 can produce parasitic transistor, made normal memory when operation, and leaky can take place.That is depression 150 meeting stored charges cause the inferior of element to open beginning leakage current (sub-threshold leakage current) then in integrated circuit, and form so-called neck knot effect (kink effect).Neck knot effect will reduce the quality of element, and reduces the stability and the reliability of element, also can cause the rate of finished products of technology to reduce.And in the low-voltage circuit district 102,, can cause doped polycrystalline silicon to insert recessed 168 zone because recessed 168 existence is arranged, and junction leakage problems such as (junction leakages) takes place, not only improve power consumption, and elongated the arithmetic speed of element.
Summary of the invention
In view of this, purpose of the present invention is exactly that a kind of manufacture method of gate dielectric layer is being provided, and can avoid the thinning phenomenon of gate dielectric layer in the fleet plough groove isolation structure edge, and then improves the reliability and the stability of element.
Another object of the present invention provides a kind of manufacture method of gate dielectric layer, can solve the recessed problem of fleet plough groove isolation structure in the low-voltage circuit district, prevents the generation of junction leakage, and reaches effects such as low power consuming, high-speed computation.
The present invention proposes a kind of manufacture method of gate dielectric layer.The method for example provides substrate, and high voltage circuit area and low-voltage circuit district are divided in substrate at least, forms first dielectric layer in substrate, and first dielectric layer is as the usefulness of gate oxide in the high voltage circuit area.Afterwards, form mask layer on first dielectric layer, patterned mask layer, first dielectric layer and substrate are to form groove in substrate.Then, in substrate, form insulating barrier to fill up groove.Then, remove partial insulative layer and mask layer, expose the surface of first dielectric layer.Then, remove first dielectric layer and the partial insulative layer in low-voltage circuit district, expose the surface of substrate.Then, form second dielectric layer in the substrate in low-voltage circuit district, the thickness of second dielectric layer is less than the thickness of first dielectric layer.
According to the manufacture method of the described gate dielectric layer of the preferred embodiments of the present invention, before above-mentioned formation first dielectric layer, comprise that also the mixed solution that uses ammoniacal liquor and hydrogen peroxide carries out a cleaning step.The thickness of first dielectric layer for example is between 200～1000 dusts, and the method that forms first dielectric layer for example is a thermal oxidation method.The thickness of second dielectric layer can be between 15～150 dusts, and the method that forms second dielectric layer for example is a thermal oxidation method.
According to the manufacture method of the described gate dielectric layer of the preferred embodiments of the present invention, the above-mentioned method that removes first dielectric layer in low-voltage circuit district for example is: form the photoresist floor in the substrate of high voltage circuit area.With the photoresist layer is mask, first dielectric layer in etching low-voltage circuit district.Remove the photoresist layer then.Wherein the method for first dielectric layer in etching low-voltage circuit district for example is a wet etching.
Manufacture method according to the described gate dielectric layer of the preferred embodiments of the present invention, above-mentioned patterned mask layer, first dielectric layer and substrate, with the method that in substrate, forms groove for example be: on mask layer, form patterning photoresist layer, and be mask with this patterning photoresist layer, etching mask layer, first dielectric layer and substrate are to form groove in substrate.Remove patterning photoresist layer then.The method of etching mask layer, first dielectric layer and substrate for example is the dry-etching method.
According to the manufacture method of the described gate dielectric layer of the preferred embodiments of the present invention, on be set forth in the step that forms groove after, can also form lining oxide layer in the sidewall of groove.The method that forms lining oxide layer for example is a thermal oxidation method.
According to the manufacture method of the described gate dielectric layer of the preferred embodiments of the present invention, the method for above-mentioned formation insulating barrier for example is the high density plasma CVD method.If partial insulative layer exceeds the mask layer surface, also comprise and carry out chemical mechanical milling tech, be that stop layer removes the insulating barrier on the mask layer with the mask layer.The method that removes this mask layer for example is an isotropic etching.
The present invention is because of form the gate oxide of high voltage circuit area earlier in substrate, and is different with the practice of the existing pad oxide of formation earlier.Therefore can solve the recessed problem of fleet plough groove isolation structure in the low-voltage circuit district, prevent the generation of junction leakage, and reach effects such as low power consuming, high-speed computation.In addition, when the lining oxide layer in groove generates,, can avoid the thinning phenomenon of gate dielectric layer, and then improve the reliability and the stability of element in the fleet plough groove isolation structure edge prior to the beak of groove edge formation silica.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. is described in detail below.
Description of drawings
Figure 1A to Fig. 1 F is the manufacturing process profile that illustrates existing gate oxide.
Fig. 2 A to Fig. 2 F is the manufacturing process profile that illustrates a kind of gate dielectric layer of one embodiment of the present invention.
Fig. 3 is a kind of part enlarged drawing of manufacturing process profile of gate dielectric layer that illustrates one embodiment of the present invention of Fig. 2 C.
The simple symbol explanation
100,200: substrate
101,201: high voltage circuit area
102,202: the low-voltage circuit district
110: pad oxide
120,220: mask layer
130,230: groove
140: silicon oxide layer
145: active area
150,250: depression
160: high voltage grid oxidation layer
165,245: the photoresist layer
168; Recessed
170: the low pressure gate oxide
180: doped polysilicon layer
210,260: dielectric layer
225: patterning photoresist layer
235: lining oxide layer
237: beak
240: insulating barrier
255: fleet plough groove isolation structure
270: conductor layer
Embodiment
Fig. 2 A to Fig. 2 F is the manufacturing process profile that illustrates a kind of gate dielectric layer of one embodiment of the present invention.
Please refer to Fig. 2 A, this manufacture method for example is that substrate 200 is provided earlier, and substrate 200 can be divided into high voltage circuit area 201 and low-voltage circuit district 202 at least.Again with for example RCA solution (ammoniacal liquor NH
4OH and hydrogen peroxide H
2O
2Mixed solution) cleaning step is carried out in substrate 200.Afterwards, in substrate 200, form one dielectric layer 210.Dielectric layer 210 is as the usefulness of gate dielectric layer in the high voltage circuit area 201, so the more existing pad oxide of dielectric layer 210 thickness is thick, and the thickness of dielectric layer 210 is about between 200～1000 dusts.The formation method of dielectric layer 210 for example is a thermal oxidation method.
Afterwards, please refer to Fig. 2 B, form one deck mask layer 220 on dielectric layer 210, the material of mask layer 220 for example is a silicon nitride, and its formation method for example is a chemical vapour deposition technique, and the thickness of mask layer 220 for example is between 800～2000 dusts.
Then, on mask layer 220, form one deck patterning photoresist layer 225, and be mask, etching mask layer 220 and dielectric layer 210 with this patterning photoresist layer 225.The material of patterning photoresist layer 225 for example is positive photoresist, and its formation method for example is earlier to form one deck photo anti-corrosion agent material layer (not illustrating) in the rotary coating mode on mask layer 220, carries out the development of pattern and form it after exposing.Etching mask layer 220 for example is the dry-etching method with the method for dielectric layer 210.
Next, please refer to Fig. 2 C, remove patterning photoresist layer 225.The method that removes patterning photoresist layer 225 for example is that dry type is delustered and caused resist or wet type and deluster and cause resist.Afterwards, be mask with mask layer 220, etching substrate 200 is to form groove 230 in substrate 200.Groove 230 is the groove in the follow-up fleet plough groove isolation structure.The method of etching substrate 200 for example is the dry-etching method.Then, in order to repair groove 230 surfaces, in sidewall formation one deck lining oxide layer (liner oxide) 235 of groove 230 because of the lattice defect that dry-etching caused.The formation method of lining oxide layer 235 for example is a thermal oxidation method, and its thickness for example approximately is 80～500 dusts.
Among Fig. 2 C, in formation lining oxide layer 235, the edge of groove can produce beak 237, please refer to Fig. 3, and Fig. 3 is the enlarged drawing of beak 237.Because the formation of beak 237 has thickened the thickness of the silica of edge, can avoid having now in high voltage circuit area the gate oxide thinning phenomenon that can produce.
Then, please refer to Fig. 2 D, form insulating barrier 240 in substrate 200, insulating barrier 240 fills up groove 230 and covers substrate 200.Insulating barrier 240 is promptly as the usefulness of isolation structure in the follow-up fleet plough groove isolation structure.The material of insulating barrier 240 for example is silica or other suitable insulation material, and its formation method for example is the high density plasma CVD method, and it for example is 4000～7000 dusts that the thickness of formed insulating barrier 240 is started at by groove 230 bottoms.Then remove mask layer 220, to form fleet plough groove isolation structure 255.The method that removes mask layer 220 for example is to carry out isotropic etching.Wherein, if partial insulative layer 240 exceeds mask layer 220 surfaces, then can carry out chemical mechanical milling tech before removing mask layer 220, be stop layer with mask layer 220, removes the insulating barrier 240 on the mask layer 220.
Among Fig. 2 D,, have the phenomenon of undercutting, and make that depression 250 takes place in meeting between insulating barrier 240 and the dielectric layer 210, as the depression 150 of Fig. 1 C in the prior art owing to remove mask layer 220 employed isotropic etchings.Yet both seem identical, are distinct actually.Because the depression 150 among Fig. 1 C is in close proximity to substrate 100, expose a part of substrate 100, and the substrate 100 follow-up doped regions (source/drain) that will form of this part; And among Fig. 2 D of the present invention since dielectric layer 210 than existing be thick, so depression 250 only contacts with dielectric layer 210, can't expose substrate 200.This that is to say, the position of depression 250 there is no fear of forming so-called parasitic transistor, therefore exempted and opened the neck knot effect that electric current is caused for existing time, so can improve the reliability and the stability of element, and increase the rate of finished products of product.
Afterwards, please refer to Fig. 2 E, remove the dielectric layer 210 in low-voltage circuit district 202, expose the surface of substrate 200.The method that removes the dielectric layer 210 in low-voltage circuit district 202 for example is prior to forming one deck photoresist floor 245 in the substrate 200 of high voltage circuit area 201, is mask with photoresist layer 245 then, the dielectric layer 210 in etching low-voltage circuit district 202.Wherein, the material of photoresist layer 245 for example is positive photoresist, its formation method for example is earlier to form one deck photo anti-corrosion agent material layer (not illustrating) in the rotary coating mode in substrate 200, carries out the development of pattern and form photoresist layer 245 after exposing.The method of the dielectric layer 210 in etching low-voltage circuit district 202 comprises wet etching.
In the above-described embodiments, because the material of insulating barrier 240 is identical with the material of dielectric layer 210, so in the time of the dielectric layer 210 that removes low-voltage circuit district 202, partial insulative layer 240 also can be removed in the lump.Yet Fig. 1 D in Fig. 2 E more of the present invention and the prior art can obviously find out, the disclosed gate dielectric layer manufacture method of the present invention can't in low-voltage circuit district 202, form recessed as shown in Fig. 1 D.This is because the present invention has formed one dielectric layer 210 earlier in substrate 200, and the existing pad oxide of the thickness of dielectric layer 210 is thick.Moreover the present invention need not need remove pad oxide earlier as prior art, and after formation is applicable to the oxide layer of high voltage circuit area, removes the oxide layer in the low-voltage circuit district again.Therefore, during the dielectric layer 210 of the present invention on removing low-voltage circuit district 202, can't make that the insulating barrier 240 in the isolation structure can produce recessed phenomenon, and then can prevent the generation of junction leakage (junction leakage), reach and reduce element operation energy consumption, the effect of the speed that speeds operations.
Then, please refer to Fig. 2 F, remove the photoresist layer 245 on the high voltage circuit area 201, its method for example is that wet type is delustered and caused resist or dry type and deluster and cause resist.Then, form one dielectric layer 260 in substrate 200, the formation method of dielectric layer 260 for example is a thermal oxidation method.The thickness of dielectric layer 260 is less than the thickness of dielectric layer 210, and the thickness of dielectric layer 260 for example is between 15～150 dusts.In addition, the formation method of dielectric layer 260 also can be the photoresist layer 245 that keeps earlier on the high voltage circuit area 201, and directly with chemical vapour deposition technique, forms dielectric layer 260 in substrate 200.Remove photoresist layer 245 afterwards again.
Continue it, please continue F, on dielectric layer 260 and dielectric layer 210, form conductor layer 270 with reference to Fig. 2.The material of conductor layer 270 for example is a doped polycrystalline silicon, its formation method for example is to form one deck undoped polycrystalline silicon layer (not illustrating) with chemical vapour deposition technique earlier, the mode of injecting with ion forms it again, certainly, also can utilize the mode of injecting when participating in the cintest, form doped polysilicon layer with chemical vapour deposition technique.As for follow-up technology, look the element that the institute desire forms and have differently, it is known to should be those skilled in the art institute, repeats no more in this.
In sum, the present invention directly forms the gate oxide of high voltage circuit area in substrate, but not as the existing pad oxide that forms earlier, removes this pad oxide afterwards again.Not only step is simpler on technology, can save cost and process time, and can solve the recessed problem of fleet plough groove isolation structure in the low-voltage circuit district, prevents the generation of junction leakage, and then reaches effects such as low power consuming, high-speed computation.In addition, when the lining oxide layer in groove generates, prior to the beak of groove edge formation silica, can avoid the thinning phenomenon of gate dielectric layer, and improve the reliability and the stability of element in the fleet plough groove isolation structure edge.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art can do a little change and retouching without departing from the spirit and scope of the present invention, thus protection scope of the present invention should with accompanying Claim the person of being defined be as the criterion.
Claims (15)
1. the manufacture method of a gate dielectric layer comprises:
One substrate is provided, and a high voltage circuit area and a low-voltage circuit district are divided in this substrate at least;
Form one first dielectric layer in this substrate, this first dielectric layer is as the usefulness of the gate dielectric layer in this high voltage circuit area;
On this first dielectric layer, form a mask layer;
This mask layer of patterning, this first dielectric layer and this substrate are to form a groove in this substrate;
In this substrate, form an insulating barrier to fill up this groove;
Remove this mask layer, expose the surface of this first dielectric layer;
Remove this first dielectric layer in this low-voltage circuit district, expose the surface of this substrate; And
Form one second dielectric layer in this substrate in this low-voltage circuit district, the thickness of this second dielectric layer is less than the thickness of this first dielectric layer.
2. the manufacture method of gate dielectric layer as claimed in claim 1, wherein the thickness of this first dielectric layer is between 200～1000 dusts.
3. the manufacture method of gate dielectric layer as claimed in claim 1, the method that wherein forms this first dielectric layer comprises thermal oxidation method.
4. the manufacture method of gate dielectric layer as claimed in claim 1 wherein removes the method for this first dielectric layer in this low-voltage circuit district, comprising:
In this substrate of this high voltage circuit area, form a photoresist layer;
With this photoresist layer is mask, this first dielectric layer in this low-voltage circuit district of etching; And
Remove this photoresist layer.
5. the manufacture method of gate dielectric layer as claimed in claim 4, wherein the method for this first dielectric layer in this low-voltage circuit district of etching comprises wet etching.
6. the manufacture method of gate dielectric layer as claimed in claim 1, wherein this mask layer of patterning, this first dielectric layer and this substrate comprises with the method that forms this groove in this substrate:
On this mask layer, form a patterning photoresist layer;
With this patterning photoresist layer is mask, and this mask layer of etching, this first dielectric layer and this substrate are to form this groove in this substrate; And
Remove this patterning photoresist layer.
7. the manufacture method of gate dielectric layer as claimed in claim 6, wherein the method for this mask layer of etching, this first dielectric layer and this substrate comprises the dry-etching method.
8. the manufacture method of gate dielectric layer as claimed in claim 1, wherein after the step that forms this groove, the sidewall that also is included in this groove forms a lining oxide layer.
9. the manufacture method of gate dielectric layer as claimed in claim 8, the method that wherein forms this lining oxide layer comprises thermal oxidation method.
10. the manufacture method of gate dielectric layer as claimed in claim 1 wherein exceeds this mask layer surface as if this insulating barrier of part, also comprises:
Carrying out a chemical mechanical milling tech, is that stop layer removes this insulating barrier on this mask layer with this mask layer.
11. the manufacture method of gate dielectric layer as claimed in claim 1, the method that wherein removes this mask layer comprises isotropic etching.
12. the manufacture method of gate dielectric layer as claimed in claim 1, the method that wherein forms this insulating barrier comprises the high density plasma CVD method.
13. the manufacture method of gate dielectric layer as claimed in claim 1 wherein forms before this first dielectric layer, also comprises using the mixed solution of ammoniacal liquor and hydrogen peroxide to carry out a cleaning step.
14. the manufacture method of gate dielectric layer as claimed in claim 1, wherein the thickness of this second dielectric layer is between 15～150 dusts.
15. the manufacture method of gate dielectric layer as claimed in claim 1, the method that wherein forms this second dielectric layer comprises thermal oxidation method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100920438A CN100378956C (en) | 2005-08-16 | 2005-08-16 | Method of manufacturing dielectric layer of grid |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100920438A CN100378956C (en) | 2005-08-16 | 2005-08-16 | Method of manufacturing dielectric layer of grid |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1917173A CN1917173A (en) | 2007-02-21 |
| CN100378956C true CN100378956C (en) | 2008-04-02 |
Family
ID=37738120
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100920438A Expired - Fee Related CN100378956C (en) | 2005-08-16 | 2005-08-16 | Method of manufacturing dielectric layer of grid |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100378956C (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102263062B (en) * | 2010-05-28 | 2013-05-01 | 无锡华润上华半导体有限公司 | Method for forming side walls of multiple-unit semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1404155A (en) * | 2001-09-03 | 2003-03-19 | 世界先进积体电路股份有限公司 | Non-volatile memory element and its manufacture |
| US20040126972A1 (en) * | 2002-12-26 | 2004-07-01 | Hynix Semiconductor Inc. | Method of manufacturing flash memory device |
-
2005
- 2005-08-16 CN CNB2005100920438A patent/CN100378956C/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1404155A (en) * | 2001-09-03 | 2003-03-19 | 世界先进积体电路股份有限公司 | Non-volatile memory element and its manufacture |
| US20040126972A1 (en) * | 2002-12-26 | 2004-07-01 | Hynix Semiconductor Inc. | Method of manufacturing flash memory device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1917173A (en) | 2007-02-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100459724B1 (en) | Semiconductor device having a SiN etch stopper by low temperature ALD and fabricating method the same | |
| US7763928B2 (en) | Multi-time programmable memory | |
| CN210272309U (en) | Semiconductor structure | |
| CN100440484C (en) | Method of fabricating flash memory device | |
| KR100368594B1 (en) | Split Gate Flash Memory Device | |
| KR20090108917A (en) | Semiconductor device and method for fabricating the same | |
| TWI506726B (en) | Superior integrity of high-k metal gate stacks by capping sti regions | |
| KR100397176B1 (en) | Method of planarizing non-volatile memory device | |
| US20150214234A1 (en) | Semiconductor device and method for fabricating the same | |
| CN111199911B (en) | Shallow trench isolation structure and manufacturing method thereof | |
| KR20000011820A (en) | Method of manufacturing a semiconductor device | |
| CN100378956C (en) | Method of manufacturing dielectric layer of grid | |
| JP2008021935A (en) | Electronic device and manufacturing method thereof | |
| KR100480894B1 (en) | A method for manufacturing of merged memory logic in semiconductor device | |
| JP4082280B2 (en) | Semiconductor device and manufacturing method thereof | |
| KR20000020382A (en) | Semiconductor device having trench isolation region and method for fabricating thereof | |
| KR100305026B1 (en) | Manufacturing method of semiconductor device | |
| JP2008135765A (en) | Semiconductor device | |
| KR100281144B1 (en) | Semiconductor device and manufacturing method | |
| KR100317491B1 (en) | Method of manufacturing a flash memory device | |
| KR100958632B1 (en) | Fabricating Method of Flash Memory Device | |
| EP1312113A1 (en) | Trench formation and oxide etching process | |
| KR100459928B1 (en) | Method of manufacture semiconductor device | |
| KR100939429B1 (en) | Semiconductor device and manufacturing method thereof | |
| KR20080062557A (en) | Method of manufacturing semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080402 |