CN210272309U - Semiconductor structure - Google Patents
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- CN210272309U CN210272309U CN201921429212.6U CN201921429212U CN210272309U CN 210272309 U CN210272309 U CN 210272309U CN 201921429212 U CN201921429212 U CN 201921429212U CN 210272309 U CN210272309 U CN 210272309U
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Abstract
A semiconductor structure, the semiconductor structure comprising: a substrate; the connecting through holes are arranged on the substrate at intervals; the bit line structure is positioned in the connecting through hole and is partially connected with the connecting through hole; the passivation layer is positioned on the surface of the bit line structure; and the isolation layer is positioned on the surface of the passivation layer. The performance of the semiconductor structure is improved.
Description
Technical Field
The utility model relates to the field of semiconductor technology, especially, relate to a semiconductor structure.
Background
The development of memories pursues high speed, high integration density, low power consumption, and the like. With the shrinking structure size of semiconductor devices, especially in the manufacturing process of DRAM with critical dimension less than 20nm, there are higher requirements for the insulating material between the conductive lines, such as wider bandwidth to ensure good insulating performance, lower dielectric constant to ensure small parasitic capacitance, and small coupling effect, and various low-k dielectric materials are widely used in semiconductor manufacturing. The air layer structure of silicon nitride-air layer-silicon nitride is one of the most suitable low-K dielectric material structures, and because the air layer in the middle can ensure good insulating property and the air layer has the lowest dielectric constant, the increasingly stringent low-K requirements of semiconductors can be met.
As semiconductor critical dimensions continue to shrink, the integration of device structures has become higher and higher, and in the prior art, SADP (self-aligned dual patterning) technology is generally used to reduce the critical dimension of bit lines. However, the bit line size is reduced, which leads to an increase of the aspect ratio of the pattern, and during the process of forming the bit line by etching, the bit line mask layer is easily deformed or collapsed, so that the mask layer pattern is abnormal, and it is difficult to further continue to shrink the critical dimension of the bit line by directly etching.
How to further reduce the critical dimension of the bit line is a problem to be solved.
SUMMERY OF THE UTILITY MODEL
The utility model aims to solve the technical problem that a semiconductor structure is provided, semiconductor structure's performance is improved.
In order to solve the above problem, the technical scheme of the utility model provides a semiconductor structure, include: a substrate; the connecting through holes are arranged on the substrate at intervals; the bit line structure is positioned in the connecting through hole and is partially connected with the connecting through hole; the passivation layer is positioned on the surface of the bit line structure; and the isolation layer is positioned on the surface of the passivation layer.
Optionally, the passivation layer is further formed on the sidewall of the connection via, and the isolation layer is filled between the passivation layer on the sidewall of the connection via and the passivation layer on the surface of the bit line structure.
Optionally, the bit line structure further includes an isolation dielectric layer located on the top of the bit line structure, and the passivation layer covers a surface of the isolation dielectric layer.
Optionally, the bit line structure includes a bit line contact and a metal conductive layer on top of the bit line contact.
Optionally, the widths of the bit line contact, the metal conductive layer and the isolation dielectric layer are the same.
Optionally, the metal conductive layer includes a first metal conductive layer and a second metal conductive layer.
Optionally, the passivation layer is an oxide layer or a nitride layer.
In order to solve the above problem, the technical solution of the present invention further provides a semiconductor structure, including: a substrate; the connecting through holes are arranged on the substrate at intervals, and passivation layers are arranged on the side wall surfaces of the connecting through holes; the bit line structure is positioned in the connecting through hole and is partially connected with the connecting through hole; an isolation layer covering the substrate, the bit line structure, and the connection via; an air gap between the bit line structure and the isolation layer.
Optionally, the passivation layer is an oxide layer or a nitride layer. Optionally, the top of the air gap is closed by a membrane layer.
The utility model discloses a semiconductor construction's bit line structure surface is formed with the passivation layer, the passivation layer is the rete that the reactivity processed the formation, makes the critical dimension of bit line structure dwindles.
Furthermore, the critical dimension of the bit line structure is reduced, so that an air gap is formed between the bit line structure and the isolation layer, and the parasitic capacitance between the bit line structures of the semiconductor structure can be reduced.
Drawings
Fig. 1 to 12 are schematic structural diagrams illustrating a process of forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
The following describes in detail a semiconductor structure and a method for forming the same according to the present invention with reference to the accompanying drawings.
Please refer to fig. 1 to 12, which are schematic structural views illustrating a forming process of a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 1, a substrate 100 is provided, a dielectric layer 112 is formed in the substrate 100, the dielectric layer 112 and the substrate 100 are etched, a plurality of connecting through holes arranged at intervals are formed, and the connecting through holes are filled to form a bit line contact layer 111; forming a metal conductive layer covering the surface of the dielectric layer 112, a first sacrificial material layer 115, and a bit line mask structure 120 on the surface of the first sacrificial material layer 115; the metal conductive layers include a second metal conductive layer 113 and a first metal conductive layer 114.
The semiconductor substrate 100 may include, but is not limited to, a single crystal silicon substrate, a polycrystalline silicon substrate, a gallium nitride substrate, or a sapphire substrate, and when the semiconductor substrate 100 is a single crystal substrate or a polycrystalline substrate, it may also be an intrinsic silicon substrate or a lightly doped silicon substrate, and further, it may be an N-type polycrystalline silicon substrate or a P-type polycrystalline silicon substrate.
Isolation structures (not shown) are also formed in the substrate 100 to isolate active regions in the substrate 100. The isolation structure can be formed by forming a trench in the substrate and then filling the trench with an isolation material layer. The material of the isolation structure may include silicon nitride or silicon oxide, etc. The isolation structure can isolate a plurality of active regions in an array distribution or other distribution types from the substrate.
The substrate 100 may have a MOS transistor (not shown) formed in an active region thereof, the MOS transistor including a gate, and a source and a drain on both sides of the gate. Word lines arranged in parallel may also be formed in the substrate 100 and connected to the gates of the MOS transistors. The extending direction of the word line may intersect the active region.
The bit line contact layer 111 is partially buried in an active region of the substrate 100, and is in contact with a source or a drain of a MOS transistor in the active region. The bit line contact layers 111 are formed in the respective active regions in the substrate 100. The material of the bit line contact layer 111 includes, but is not limited to, a conductive material such as polysilicon. In this embodiment, the bit line contact layer 111 is made of doped polysilicon.
The dielectric layer 112 covers the substrate 100 and has a surface flush with the top of the bit line contact layer 111. The material of the dielectric layer 112 includes, but is not limited to, an insulating dielectric material such as silicon nitride or silicon oxide.
The metal conductive layer covers the dielectric layer 112 and the bit line contact layer 111. The metal layers include a first metal conductive layer 114 and a second metal conductive layer 113. The material of the second metal conductive layer 113 includes, but is not limited to, TiN or WN, and the material of the first metal conductive layer 114 includes, but is not limited to, W. The first metal conductive layer 114 and the second metal conductive layer 113 are made of different materials. In other embodiments, the metal conductive layer may include only a single metal layer.
In this embodiment, the material of the first sacrificial material layer 115 is the same as the material of the bit line contact layer 111, and includes, but is not limited to, a conductive material such as polysilicon. In this embodiment, the material of the first sacrificial material layer 115 may be doped polysilicon.
In other embodiments, the first sacrificial material layer 115 may be formed directly on the surfaces of the bit line contact layer 111 and the dielectric layer 112 without forming the metal conductive layer.
The bit line mask structure 120 includes a first mask layer 121, a second mask layer 122, an etch stop layer 123, and a pattern layer 124. The material of the first mask layer 121 includes but is not limited to silicon oxide or silicon nitride, and the material of the second mask layer 122 is a hard mask material, which may be carbon; the material of the etch stop layer 123 includes, but is not limited to, silicon nitride or silicon oxynitride; the pattern layer 124 includes several bit line structure patterns, and specific materials may include, but are not limited to, silicon oxide or polysilicon.
Referring to fig. 2a, the bit line mask structure 120 is used as a mask to sequentially etch the first sacrificial material layer 115, the first metal conductive layer 114, the second metal conductive layer 113, the dielectric layer 112 and the bit line contact layer 111, so as to form a plurality of first semiconductor structures 200 arranged at intervals on the substrate 100, where the first semiconductor structures 200 include the bit line structures 110 and first sacrificial layers 1151 located at the tops of the bit line structures 110. The bit line structure 110 includes a bit line contact 1111, a metal conductive layer on the bit line contact 1111. The metal conductive layer includes: the second metal conductive layer 1131 and the first metal conductive layer 1141 further have a patterned dielectric layer 1121 between adjacent bit line contacts 1111.
In one embodiment, the bit line structure 110 may include only the bit line contact 1111, and the first sacrificial layer 1151 may be of the same material as the bit line contact 1111. Alternatively, in another embodiment, the bit line structure 110 further includes a metal conductive layer, which may be selected to be the same material as the first sacrificial layer 1151. In this embodiment, the metal conductive layer includes a first metal conductive layer 1141 and a second metal conductive layer 1131, and the metal layer includes a first metal conductive layer 1141 and a second metal conductive layer 1131. The material of the second metal conductive layer 1131 includes, but is not limited to, TiN or WN, and the material of the first metal conductive layer 1141 includes, but is not limited to, W.
Since the active regions in the substrate 100 are usually staggered at an angle, the cross-sectional structures of the bit line structures 200 in different columns at the same cross-section are different, please refer to fig. 2 b; FIG. 2a is a cross-sectional view along the cut line AA' in FIG. 2b, and the bottom of the bit line structure 200 in FIG. 2a only shows the dielectric layer 1121 between the adjacent bit line contacts 1111. The bit line contact 1111 sidewall has a gap with the substrate 100
Referring to fig. 3, the dielectric layer 1121 and the second metal conductive layer 1131 are laterally etched.
In this embodiment, the dielectric layer 1121 is made of silicon nitride, and the second metal conductive layer 1131 is made of TiN, and in this embodiment, the widths of the dielectric layer 1121 and the second metal conductive layer 1131 may be reduced by a lateral etching process. Specifically, the lateral etching process may be implemented by controlling an etching selection ratio, for example, a wet etching process is adopted, for example, a hot phosphoric acid solution is adopted to laterally etch the dielectric layer 1121, and a mixed solution of sulfuric acid and hydrogen peroxide is used to laterally etch the second metal conductive layer 1131. The widths of the etched dielectric layer 1121a and the second metal conductive layer 1131a are consistent with the width of a second semiconductor structure to be formed later.
Referring to fig. 4, a passivation layer 400 is formed on the surface of the first semiconductor structure 200 to cover at least a portion of the sidewall of the first semiconductor structure 200.
It should be noted that the passivation treatment referred to in the embodiments of the present invention means that the structure itself reacts with the reactive agent to form a passivation film attached to the surface of the structure. Such as oxidation, nitridation or other reactive processes. In the following description, an oxide layer is formed by a passivation process, but in other specific embodiments, a nitride layer may be formed by a passivation process.
In a specific embodiment, the passivation process is performed by a thermal oxidation process, which specifically includes: the first sacrificial layer 1151, the first metal conductive layer 1141 and the bit line contact 1111 are thermally oxidized, so that a surface portion of the thickness of the material layer is oxidized and consumed to form an oxide layer. The widths of the first sacrificial layer 1151a, the first metal conductive layer 1141a and the bit line contact 1111a, which have the oxidized surface, are reduced. In this specific embodiment, the first sacrificial layer 1151a is made of polysilicon, and the oxide layer 401 on the surface of the first sacrificial layer 1151a is made of silicon oxide; the first metal conductive layer 1141a is made of W, and the oxide layer 402 is made of tungsten oxide; the bit line contact 1111a is made of polysilicon, and the oxide layer 403 is made of silicon oxide. An oxide layer 404 is also formed on the surface of the substrate 100, and the material of the oxide layer 404 is silicon oxide.
Since the first sacrificial layer 1151 and the bit line contact 1111 have the same oxidation rate under the same oxidation condition in this embodiment, the oxide layer 403 and the oxide layer 401 have the same thickness. The oxidation rate of the first metal conductive layer 1141 is close to or the same as the oxidation rate of the first sacrificial layer 1151 and the bit line contact 1111, so that the thicknesses of the oxide layers 401, 402 and 403 are substantially the same, and thus the widths of the oxidized first sacrificial layer 1151a and the oxidized first metal conductive layer 1141a and the bit line contact 1111a are substantially the same. Moreover, the thickness of each oxide layer is the same as the width of the second metal conductive layer 1131a and the dielectric layer 1121a that are laterally etched, so that the widths of the first sacrificial layer 1151a, the first metal conductive layer 1141a, the second metal conductive layer 1131a, the bit line contact 1111a and the dielectric layer 1121a are substantially or completely the same.
In other embodiments, the control of the thickness of the oxide layer on the surface of the bit line contact 1111, the first metal conductive layer 1141 and the first sacrificial layer 1151 can be achieved by a plurality of thermal oxidation and cleaning processes.
In other embodiments, the oxidation degree of the first metal conductive layer 1141, the first sacrificial layer 1151 and the bit line contact 1111 does not need to be the same, because the desired thickness can be obtained by controlling the selection ratio when etching the second metal conductive layer 1131 and the dielectric layer 1121.
In other embodiments, the second metal conductive layer 1131a and the dielectric layer 1121a may be made of a material that is easily thermally oxidized, and the step shown in fig. 3 may be omitted, and the oxidation process is directly performed to oxidize the surface of each material layer of the entire first semiconductor structure 200, so as to form an oxide layer with a substantially uniform thickness.
In other embodiments, the step of fig. 3 may also be omitted directly, since the materials of the second metal conductive layer 1131 and the dielectric layer 1121 are not easily oxidized, an oxide layer cannot be formed on the sidewall, so that the widths of the second metal conductive layer 1131 and the dielectric layer 1121 in the second semiconductor structure formed subsequently are greater than the widths of the other material layers.
Referring to fig. 5, the oxide layer is removed, so that the size of the first bit line structure 200 is reduced, and a second semiconductor structure 500 is formed.
Etching and removing the oxide layers 401-404 by adopting a wet etching process to form the second semiconductor structure 500, wherein the second semiconductor structure 500 comprises a bit line structure 110a and a first sacrificial layer 1151a positioned at the top of the bit line structure 110 a; the bit line structure 110a includes a first metal conductive layer 1141a, a second metal conductive layer 1131a, a bit line contact 1111a and a dielectric layer 1121 a.
The utility model discloses an among the concrete implementation manner, can reduce the critical dimension of the bit line structure of final formation through above-mentioned method, at the in-process that forms first bit line structure 200 through the sculpture, can suitably increase the window of bit line sculpture, avoid because critical dimension undersize leads to the unusual problem of figure sculpture.
Referring to fig. 6, a second sacrificial layer 600 is formed at least covering the sidewalls of the second semiconductor structure 500.
The material of the second sacrificial layer 600 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, and the like. The second sacrificial layer 600 may be formed using a chemical vapor deposition process or an atomic layer deposition process. In this embodiment, the second sacrificial layer 600 is formed by an atomic layer deposition process, so as to accurately control the thickness of the second sacrificial layer 600. The thickness of the second sacrificial layer 600 determines the width of the air gap that is ultimately formed.
The second sacrificial layer 600 covers the top and sidewalls of the entire second semiconductor structure 500, as well as the surface of the substrate 100.
In another embodiment, the steps shown in fig. 5 and fig. 6 may be omitted, and the oxide layers 401 to 404 formed in the step shown in fig. 4 may be directly used as a second sacrificial layer, where the second sacrificial layer covers at least a portion of the sidewalls of the second semiconductor structure 500.
Referring to fig. 7, an isolation layer 700 is formed covering the second semiconductor structure 500 and the second sacrificial layer 600.
Before forming the isolation layer 700, the method further includes removing a portion of the second sacrificial layer 600 covering the top of the second semiconductor structure 500 and on horizontal surfaces of the substrate 100 by an anisotropic etching process to expose a top surface of the first sacrificial layer 1151 a.
The isolation layer 700 covers the second semiconductor structure 500 and also fills the gap between the sidewall of the bit line contact 1111a at the bottom of the second semiconductor structure 500 and the substrate 100. The material of the isolation layer 700 includes, but is not limited to, silicon nitride, silicon oxynitride, silicon oxide, etc., and a material with a higher dielectric constant may be selected as the material of the isolation layer 700 to improve the isolation performance between the second semiconductor structure 500 and an external conductor. The isolation layer 700 is made of a material different from that of the second sacrificial layer 600, and has a higher selectivity for the second sacrificial layer 600 when the second sacrificial layer 600 is removed.
The isolation layer 700 may be formed by an atomic layer deposition process so as to control the thickness of the isolation layer 700. In other embodiments, other processes, such as a physical vapor deposition process, a chemical vapor deposition process, a plasma enhanced vapor deposition process, etc., may be used to form the isolation layer 700.
Referring to fig. 8, a filling layer 800 is formed on the surface of the isolation layer 700 to fill the space between the second semiconductor structures 500.
The material of the filling layer 800 may include any suitable insulating material such as silicon oxide, silicon nitride, and silicon oxynitride. The filling layer 800 fills the gap between the adjacent bit line structures 110 and covers the bit line structures 110. The filling layer 800 may be formed by a spin coating process, and the material of the filling layer 800 may include, but is not limited to, SOD or SOC.
Referring to fig. 9, the first sacrificial layer 1151a is used as a stop layer, and the filling layer 700 is planarized to expose the top of the first sacrificial layer 1151 a.
The planarization process may be a dry etching process or a chemical mechanical polishing process, and the first sacrificial layer 1151a, the second sacrificial layer 600 and the isolation layer 700 are exposed by planarizing the filling layer 700 to the top of the first sacrificial layer 1151 a.
Referring to fig. 10a, the first sacrificial layer 1151a (see fig. 10) is removed to form a void on the second sacrificial layer 700 and the bit line structure 110 a; and filling an isolation dielectric layer 1010 in the gap.
The first sacrificial layer 1151a may be selectively removed by a wet etching process, and the opening is filled with an isolation dielectric layer 1010 by a deposition process. The material of the first sacrificial layer 1151a includes, but is not limited to, silicon nitride, silicon oxynitride, silicon oxide layer, or the like. And, the isolation dielectric layer 1010 is planarized by dry etching or chemical mechanical polishing, so as to expose the second sacrificial layer 600, the isolation layer 700, and the filling layer 800.
Referring to fig. 10b, in another embodiment, the oxide layer 401, the oxide layer 402, and the oxide layer 404 may also be retained, and each oxide layer is used as a second sacrificial layer; the isolation layer 700 covers the oxide layers and the second metal conductive layer 1131 a.
Referring to fig. 11, the second sacrificial layer 600 is removed, forming an air gap 1101 between the second semiconductor structure 500 and the isolation layer 700.
A wet etching process may be used to etch the second sacrificial layer 600 along the exposed top of the second sacrificial layer 600 until reaching the surface of the substrate 100, so as to form an air gap 1101 between the second semiconductor structure 500 and the isolation layer 700. In this embodiment, the material of the second sacrificial layer 600 is the same as the material of the filling layer 800, and the filling layer 800 is removed together with the removal of the second sacrificial layer 600. In other specific embodiments, the material of the second sacrificial layer 600 and the material of the filling layer 800 are respectively different, and only the second sacrificial layer 600 is removed while the filling layer 800 is remained.
In this embodiment, the second sacrificial layer 600 covers the entire sidewall of the second semiconductor structure 500, and thus the air gap 1101 is located between the entire sidewall of the second semiconductor structure 500 and the isolation layer 700.
In other embodiments, the air gap 1101 may be only located between the isolation dielectric layer 1010 and the isolation layer 700; or the air gap 1101 is located between the isolation dielectric layer 1010, the first metal conductive layer 1141a and the isolation layer 700.
Referring to fig. 12, the air gap 1101 is closed.
Specifically, the film layer 1202 is deposited on the surface of the filling layer, and since the size of the air gap 1101 is small, the material of the film layer 1202 is not filled into the air gap 1101, and the top opening of the air gap 1101 is closed, so as to form the sealed air gap 1101.
The film 1202 may be a material with poor pore-filling capability, such as silicon nitride. In other embodiments, other insulating dielectric materials may be used. The membrane layer 1202 also covers the isolation layer 700 (not shown).
In the method for forming a semiconductor structure according to the above embodiment, after the passivation layer is formed by oxidizing the surface of the initially formed first semiconductor structure, the passivation layer is removed, so that the critical dimension (width) of the bit line structure can be reduced. And, through removing the second sacrificial layer, form the structure of the air gap isolation, thus obviously reduce the parasitic capacitance between bit line structures.
The specific embodiment of the utility model provides a semiconductor structure still is provided.
Please refer to fig. 10b, which is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention.
The semiconductor structure includes: a substrate 100; the connecting through holes are arranged on the substrate at intervals; a bit line structure 110a, wherein the bit line structure 110a is located in the connecting via, and the bit line structure 110a is partially connected with the connecting via; and a passivation layer on the surface of the bit line structure 110 a.
The bit line structure 110a includes: includes a first metal conductive layer 1141a, a second metal conductive layer 1131a, a bit line contact 1111a and a dielectric layer 1121 a. An isolation dielectric layer 1010 is further formed on the top of the bit line structure 110 a. In this embodiment, the passivation layer is a thermal oxide layer, and specifically includes an oxide layer 401 located on a sidewall of the isolation dielectric layer 1010, an oxide layer 402 located on a sidewall of the first metal conductive layer 1141a, an oxide layer 403 located on a sidewall of the second metal conductive layer 1131a, and an oxide layer 404 located on a sidewall of the bit line contact 1111 a. An isolation layer 700 is also included on the surface of the oxide layer.
The oxide layer 404 is further formed on the sidewall of the via, and the isolation layer 700 is filled between the oxide layer 404 on the sidewall of the via and the oxide layer 403 on the surface of the bit line structure 110 a.
The filling layer 800 is filled between the adjacent bit line structures 110a and the isolation dielectric layer 1010.
The passivation layer is formed by performing thermal oxidation on the bit line structure, so that the line width of the bit line structure can be reduced. In other embodiments, the passivation layer may also be a nitride layer or other reactive treatment.
Please refer to fig. 12, which is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention.
The semiconductor structure includes: the substrate 100 is provided with a plurality of connecting through holes which are arranged at intervals; a bit line structure 110a located in the connection via, wherein the bit line structure 110a is partially connected to the connection via; the bit line structure 110a includes a bit line contact 1111a, a metal conductive layer on the bit line contact 1111a, and an isolation dielectric layer 1010 on top of the metal conductive layer. The metal conductive layer includes a second metal conductive layer 1131a and a first metal conductive layer 1141a located on a surface of the second metal conductive layer 1131 a.
The semiconductor substrate 100 may include, but is not limited to, a single crystal silicon substrate, a polycrystalline silicon substrate, a gallium nitride substrate, or a sapphire substrate, and when the semiconductor substrate 100 is a single crystal substrate or a polycrystalline substrate, it may also be an intrinsic silicon substrate or a lightly doped silicon substrate, and further, it may be an N-type polycrystalline silicon substrate or a P-type polycrystalline silicon substrate.
Isolation structures (not shown) are also formed in the substrate 100 to isolate active regions in the substrate 100. The isolation structure can be formed by forming a trench in the substrate and then filling the trench with an isolation material layer. The material of the isolation structure may include silicon nitride or silicon oxide, etc. The isolation structure can isolate a plurality of active regions in an array distribution or other distribution types from the substrate.
The substrate 100 may have a MOS transistor (not shown) formed in an active region thereof, the MOS transistor including a gate, and a source and a drain on both sides of the gate. Word lines arranged in parallel may also be formed in the substrate 100 and connected to the gates of the MOS transistors. The extending direction of the word line may intersect the active region.
The bit line contact 1111a of the bit line structure is partially located in the substrate 100 and contacts the source or drain of the MOS transistor in the active region. The bit line contacts 1111a are formed in respective active regions in the substrate 100. The bit line contact 1111a includes, but is not limited to, a conductive material such as polysilicon. The bit line structure further includes a dielectric layer 1121a located between adjacent bit line contacts 1111a on the surface of the substrate 100, and the material of the dielectric layer 1121a includes, but is not limited to, an insulating dielectric material such as silicon nitride or silicon oxide.
The material of the second metal conductive layer 1131a includes, but is not limited to, TiN or WN, and the material of the first metal conductive layer 1141a includes, but is not limited to, W.
The material of the isolation dielectric layer 1010 includes, but is not limited to, silicon nitride, silicon oxynitride, silicon oxide layer, or the like.
The semiconductor structure further includes an isolation structure covering the substrate 100 and the bit line structure 110a, and an air gap 1101 is formed between the isolation structure, the bit line structure 110a, and an isolation dielectric layer 1010. In one embodiment, the air gap 1101 is at least between the isolation dielectric layer 1010 and the isolation structure. In another specific embodiment, the air gap 1101 is located between the entire sidewall of the bitline structure and the isolation structure.
In this embodiment, the isolation structure includes an isolation layer 700 opposite the sidewalls of the bit line structure and a film layer 1202 closing the top opening of the air gap. The materials of the isolation layer 700 and the film layer 1202 include, but are not limited to, silicon nitride, silicon oxynitride, silicon oxide, etc., and materials with higher dielectric constants may be selected as the materials of the isolation layer 700 and the film layer 1202 to improve the isolation performance between the bit line structure and the external conductor.
The bit line contact 1111a has a gap with the substrate 100, which is filled with the isolation layer 700. In this embodiment, a passivation layer 1201 is further formed on the sidewall of the connecting via, and the isolation layer 700 is filled between the passivation layer 1201 on the sidewall of the connecting via and the bit line structure. The passivation layer 1201 may be a film formed by a reactive process, such as an oxide layer or a nitride layer.
The air gap 1101 formed on the sidewall of the bit line structure of the semiconductor structure can reduce the parasitic capacitance of the bit line structure.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of improvements and decorations can be made without departing from the principle of the present invention, and these improvements and decorations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A semiconductor structure, comprising:
a substrate;
the connecting through holes are arranged on the substrate at intervals;
the bit line structure is positioned in the connecting through hole and is partially connected with the connecting through hole;
the passivation layer is positioned on the surface of the bit line structure;
and the isolation layer is positioned on the surface of the passivation layer.
2. The semiconductor structure of claim 1, wherein the passivation layer is further formed on the connecting via sidewall, and the isolation layer is filled between the passivation layer on the connecting via sidewall and the passivation layer on the bit line structure surface.
3. The semiconductor structure of claim 1, further comprising an isolation dielectric layer on top of the bit line structure, the passivation layer covering a surface of the isolation dielectric layer.
4. The semiconductor structure of claim 3, wherein the bit line structure comprises a bit line contact and a metal conductive layer on top of the bit line contact.
5. The semiconductor structure of claim 4, wherein widths of the bit line contact, the metal conductive layer, and the isolation dielectric layer are the same.
6. The semiconductor structure of claim 4, wherein the metal conductive layer comprises a first metal conductive layer and a second metal conductive layer.
7. The semiconductor structure of claim 4, wherein the passivation layer is an oxide layer or a nitride layer.
8. A semiconductor structure, comprising:
a substrate;
the connecting through holes are arranged on the substrate at intervals, and passivation layers are arranged on the side wall surfaces of the connecting through holes;
the bit line structure is positioned in the connecting through hole and is partially connected with the connecting through hole;
an isolation layer covering the substrate, the bit line structure, and the connection via;
an air gap between the bit line structure and the isolation layer.
9. The semiconductor structure of claim 8, wherein the passivation layer is an oxide layer or a nitride layer.
10. The semiconductor structure of claim 8, wherein the top of the air gap is closed by a membrane layer.
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