KR20080062557A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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Publication number
KR20080062557A
KR20080062557A KR1020060138498A KR20060138498A KR20080062557A KR 20080062557 A KR20080062557 A KR 20080062557A KR 1020060138498 A KR1020060138498 A KR 1020060138498A KR 20060138498 A KR20060138498 A KR 20060138498A KR 20080062557 A KR20080062557 A KR 20080062557A
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KR
South Korea
Prior art keywords
gate
layer
film
gate conductive
etch stop
Prior art date
Application number
KR1020060138498A
Other languages
Korean (ko)
Inventor
권혁
임지민
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020060138498A priority Critical patent/KR20080062557A/en
Publication of KR20080062557A publication Critical patent/KR20080062557A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A method for manufacturing a semiconductor device is provided to uniformly form a conductive layer for a gate without topology by preventing a bending upon forming of the conductive layer for a gate. A groove(H) is formed on a gate forming region of a semiconductor substrate(400). A gate dielectric(412), a first gate conduction layer(414), and an etch stop layer(416) are formed in turn on the semiconductor substrate. A second gate conduction layer(418) is formed to gap-fill the groove on the etch stop layer. CMP(Chemical Mechanical Polishing) is performed on the second gate conduction layer until the etch stop layer is exposed. A part of the exposed etch stop layer is removed. A second gate conduction layer is formed on the resultant substrate of which the exposed part of the etch stop layer is removed. A fourth gate conduction layer and a hard mask layer are formed in turn on the third gate conduction layer. The hard mask layer, the fourth gate conduction layer, the third gate conduction layer, the second gate conduction layer, and the gate dielectric are patterned to form a recess gate.

Description

Method of manufacturing semiconductor device

1A to 1D are cross-sectional views of processes for describing a method of manufacturing a semiconductor device having a recess gate according to the related art.

3 and 4 are photographs showing a problem of a recess gate formed by a method of manufacturing a semiconductor device according to the prior art.

4A through 4G are cross-sectional views of processes for describing a method of manufacturing a semiconductor device, according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

400: semiconductor substrate 402: device isolation film

404: pad oxide film 406: polysilicon film

408: recess mask 410: mask pattern

412: gate insulating film 414: first gate conductive film

416: etch stop film 418: second gate conductive film

420: third gate conductive film 422: fourth gate conductive film

424 hard mask H: home

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of preventing the gate from falling down.

As semiconductor devices are highly integrated, channel lengths of transistors are decreasing, and ion implantation concentrations into junction regions (source / drain regions) are increasing.

As a result, a so-called short channel effect is generated in which interference between the source / drain regions increases, control of the gate decreases, and the threshold voltage Vt rapidly decreases. In addition, a problem arises in that the refresh characteristic is deteriorated due to an increase in the junction leakage current due to an increase in the electric field of the junction region. Therefore, the structure of a transistor having a conventional planar channel structure has reached its limit in overcoming the problems associated with the high integration.

As a result, researches on ideas and actual process development researches on how to implement a MOSFET device having various types of recess channels capable of securing an effective channel length have been actively conducted.

Hereinafter, a method of manufacturing a semiconductor device having a recess gate according to the related art will be described with reference to FIGS. 1A to 1D.

Referring to FIG. 1A, a recess mask 108 having a stacked structure of a pad oxide film 104 and a polysilicon film 106 on a semiconductor substrate 100 having an isolation layer 102 defining an active region is provided. Is formed and the recess mask 108 is patterned to expose the recess gate formation region.

Referring to FIG. 1B, a portion of the substrate 100 exposed by the recess mask 108 is etched to form a recess gate groove, the recess mask 108 is removed, and then the substrate 100 including the groove. A gate insulating film 110 is formed on the surface. Here, the groove is formed through a dry etching process, and the gate insulating film 110 is usually formed of an oxide film by a thermal oxidation process.

Referring to FIG. 1C, a gate conductive layer 112 is deposited to completely fill a groove on the gate insulating layer 110, and then a metal based layer 114 and a hard mask layer 116 are formed on the gate conductive layer 112. E). In this case, the gate conductive layer 112 is usually formed of a polysilicon layer, the metal layer 114 is formed of a tungsten layer or a tungsten silicide layer, and the hard mask layer 116 is formed of a nitride layer.

Referring to FIG. 1D, the layers 110, 112, 114, and 116 are patterned in order to form a recess gate 118 on the groove, and spacers 120 may be formed on both sidewalls of the recess gate 118. Next, the source / drain regions 122 are formed in the surface of the substrate 100 on both sides of the recess gate 118.

Subsequently, although not shown, a subsequent known step is sequentially performed to manufacture a semiconductor device having a recess gate.

However, in the manufacturing of the semiconductor device according to the related art, the gate conductive film is processed twice in order to prevent the generation of the gate conductive film seam due to the structure problem of the recess gate and the movement of the conductive film seam in the subsequent thermal process. As a result of the deposition, the bending of the gate conductive layer occurs as shown in FIG. 3 in the region where the recess gate is formed.

As a result, as shown in FIG. 4, the bending of the gate conductive layer and the gate conductive layer cause the gate to fall.

Therefore, the reliability of the semiconductor device is lowered due to the collapse of the gate as described above.

Accordingly, the present invention provides a method of manufacturing a semiconductor device that can prevent the gate from falling and improve the reliability of the semiconductor device.

In one embodiment, a method of manufacturing a semiconductor device includes: sequentially forming a gate insulating film, a first gate conductive film, and an etch stop film on a semiconductor substrate having grooves formed in a gate formation region; Forming a second gate conductive layer to fill the groove on the etch stop layer; CMPing the second gate conductive layer until the etch stop layer is exposed; Removing the exposed etch stop layer; Forming a third gate conductive layer on a substrate resultant from which the exposed etch stop layer is removed; Sequentially forming a fourth gate conductive film and a hard mask film on the third gate conductive film; And forming a recess gate by patterning the hard mask layer, the fourth gate conductive layer, the third gate conductive layer, the second gate conductive layer, and the gate insulating layer.

The gate insulating film is formed to a thickness of 20 to 150 GPa.

The etch stop layer is characterized in that the oxide film.

The first gate conductive film is formed of a polysilicon film having a thickness of 50 to 500 GPa.

The second gate conductive film is formed of a polysilicon film having a thickness of 300 to 2000 GPa.

The third gate conductive film is formed of a polysilicon film having a thickness of 50 to 2000 GPa.

The fourth gate conductive film is formed of a polysilicon film.

The slurry is made of a material having an etching selectivity between the gate poly and the oxide layer of 100: 1 or more.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

According to an embodiment of the present invention, a gate insulating film, a first gate conductive film, and an etch stop film are sequentially deposited on the groove surface on a semiconductor substrate having a groove, which is a gate formation region, and a second gate conductive film is formed on the etch stop film to form the second gate. The conductive film is CMP until the etch stop film is exposed, and then a third gate conductive film is deposited again on the second gate conductive film to form a gate.

In this way, unlike the conventional method of forming a gate conductive film by performing a two-step process to prevent seam generation and seam movement of the gate conductive film when the recess gate is formed, Depositing a gate conductive film and an etch stop film, and forming a second gate conductive film so as to fill the groove on the etch stop film, and planarizing the upper portion of the groove by CMP until the etch stop film is exposed. By doing so, it is possible to prevent the bending in the gate conductive film.

Accordingly, the gate conductive film can be formed uniformly without a topology, thereby preventing the gate from falling down.

As a result, the reliability of the semiconductor element can be improved.

In detail, FIGS. 4A to 4G are cross-sectional views for each process for describing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 4A, a recess mask 408 is formed on a semiconductor substrate 400 having an isolation layer 402 defining an active region. Subsequently, a mask pattern 410 exposing a recess gate formation region is formed on the recess mask 408. In general, the recess mask 408 includes a pad oxide film 404 and a polysilicon film 406. It is formed in a laminated structure of).

Referring to FIG. 4B, the recess mask is etched using the mask pattern 410 as an etch barrier, and then the mask pattern 410 is removed. Subsequently, a portion of the substrate exposed by the etched recess mask 408 is etched to form a recess gate groove H, and then a gate insulating film (not shown) is formed on the surface of the groove H by an oxidation process. 412). Here, the gate insulating film 412 is formed of an oxide film with a thickness of 20 ~ 150Å.

Referring to FIG. 4C, the first gate conductive layer 414 and the etch stop layer 416 are formed on the semiconductor substrate 400 including the groove H surface on which the gate oxide layer 412 is formed. At this time, the first gate conductive film 414 is formed to have a thickness of 50 to 500 kPa. In addition, the etch stop layer 416 may be formed of an oxide layer.

Referring to FIG. 4D, a second gate conductive layer 418 is formed on the etch stop layer 416 to completely fill the grooves H. Referring to FIG. At this time, the second gate conductive film 418 is formed to a thickness of 300 ~ 2000Å.

Referring to FIG. 4E, the CMP process may be performed to planarize the exposed portion of the substrate 400 on which the second gate conductive layer 418 is formed until the etch stop layer 416 is exposed. In this case, the planarization process using the CMP process may be performed using a slurry made of a material having an etch selectivity of an etch stop film made of the same material as the gate conductive film and the oxide film of 100: 1 or more.

 Referring to FIG. 4F, a third gate conductive film 420 is formed on the semiconductor substrate 400 planarized by the CMP process. At this time, the third gate conductive film 420 is formed to a thickness of 50 ~ 2000Å.

Referring to FIG. 4G, a fourth gate conductive film 422 and a hard mask film 422 are formed on the third gate conductive film 420, and the hard mask film 422 and the fourth gate conductive film ( 422 and the third gate conductive layer 420 are sequentially patterned to form a gate.

In this case, according to the present invention, bending of the conductive film for the gate occurs by planarization by a CMP process after forming the etch stop film and the second gate conductive film formed in the groove on the semiconductor substrate for forming the gate. The gate conductive film can be formed uniformly without the topology.

Therefore, the gate conductive film can be formed uniformly as described above, thereby preventing the gate from falling down and improving the reliability of the semiconductor device.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

As described above, according to the present invention, in forming the recess gate in various steps, the gate stop is formed by the CMP process after forming the etch stop film and the second gate conductive film formed on the first gate conductive film. It is possible to prevent the occurrence of bending when forming the conductive film.

In addition, the present invention prevents bending when the gate conductive film is formed as described above, so that the gate conductive film can be uniformly formed without a topology.

Therefore, the present invention can uniformly form the gate conductive film as described above, thereby preventing the gate from falling down and improving the reliability of the semiconductor device.

Claims (8)

Sequentially forming a gate insulating film, a first gate conductive film, and an etch stop film on the semiconductor substrate having grooves formed in the gate formation region; Forming a second gate conductive layer to fill the groove on the etch stop layer; CMPing the second gate conductive layer until the etch stop layer is exposed; Removing the exposed etch stop layer; Forming a third gate conductive layer on a substrate resultant from which the exposed etch stop layer is removed; Sequentially forming a fourth gate conductive film and a hard mask film on the third gate conductive film; And Forming a recess gate by patterning the hard mask layer, the fourth gate conductive layer, the third gate conductive layer, the second gate conductive layer, and the gate insulating layer; Method of manufacturing a semiconductor device comprising a. The method of claim 1, And the gate insulating film is formed to a thickness of 20 to 150 k ?. The method of claim 1, The etch stop layer is a semiconductor device manufacturing method, characterized in that the oxide film. The method of claim 1, The first gate conductive film is formed of a polysilicon film having a thickness of 50 to 500 GPa. The method of claim 1, The second gate conductive film is formed of a polysilicon film having a thickness of 300 to 2000 GPa. The method of claim 1, The third gate conductive film is formed of a polysilicon film having a thickness of 50 to 2000 GPa. The method of claim 1, The fourth gate conductive film is formed of a polysilicon film. The method of claim 1, The slurry is a method of manufacturing a semiconductor device, characterized in that the etching selectivity between the gate poly and the oxide film is made of 100: 1 or more.
KR1020060138498A 2006-12-29 2006-12-29 Method of manufacturing semiconductor device KR20080062557A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9023703B2 (en) 2011-11-21 2015-05-05 SK Hynix Inc. Method of manufacturing semiconductor device using an oxidation process to increase thickness of a gate insulation layer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9023703B2 (en) 2011-11-21 2015-05-05 SK Hynix Inc. Method of manufacturing semiconductor device using an oxidation process to increase thickness of a gate insulation layer

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