KR100753410B1 - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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KR100753410B1
KR100753410B1 KR1020050058568A KR20050058568A KR100753410B1 KR 100753410 B1 KR100753410 B1 KR 100753410B1 KR 1020050058568 A KR1020050058568 A KR 1020050058568A KR 20050058568 A KR20050058568 A KR 20050058568A KR 100753410 B1 KR100753410 B1 KR 100753410B1
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region
gate
peripheral region
field oxide
oxide layer
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KR20070002871A (en
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김용수
장세억
오재근
손현철
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

Abstract

본 발명은 반도체 소자의 제조방법에 관한 것으로서 셀영역과 주변영역으로 구획되고 활성영역을 한정하는 필드산화막이 구비된 반도체기판을 제공하는 단계와, 상기 주변영역 상에 형성된 필드산화막 부분을 리세스하여 주변영역의 활성영역 측면을 노출시키는 단계와, 상기 주변영역의 활성영역 측면이 노출된 기판 결과물 상에 게이트절연막과 게이트도전막을 차례로 형성하는 단계와, 상기 셀영역과 주변영역에서의 게이트도전막의 높이가 같아지도록 상기 게이트도전막을 평탄화하는 단계와, 상기 게이트도전막과 게이트절연막을 식각하여 셀영역에 제1게이트를 형성함과 아울러 주변영역에 활성영역의 측면도 채널영역으로 포함하는 제2게이트를 형성하는 단계를 포함한다. 본 발명에 따르면, 주변영역에 형성되는 제2게이트는 유효 채널폭이 증가되므로 전류 구동 능력과 단채널 여유도가 향상된다.The present invention relates to a method for manufacturing a semiconductor device, the method comprising: providing a semiconductor substrate having a field oxide film partitioned into a cell region and a peripheral region and defining an active region, and recessing a portion of the field oxide layer formed on the peripheral region; Exposing side surfaces of the active region of the peripheral region, sequentially forming a gate insulating film and a gate conductive layer on the substrate resulting from the active region side of the peripheral region, and heights of the gate conductive layers in the cell region and the peripheral region. Planarizing the gate conductive layer to be equal to, forming a first gate in the cell region by etching the gate conductive layer and the gate insulating layer, and forming a second gate including a side surface of the active region as a channel region in a peripheral region. It includes a step. According to the present invention, since the effective channel width of the second gate formed in the peripheral region is increased, current driving capability and short channel margin are improved.

Description

반도체 소자의 제조방법{METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE}Manufacturing method of semiconductor device {METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE}

도 1a 내지 도 1c는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정별 사시도 및 단면도.1A to 1C are perspective views and cross-sectional views of processes for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.

도 2a 및 도 2b는 본 발명의 다른 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정별 사시도 및 단면도.2A and 2B are perspective and cross-sectional views of processes for explaining a method of manufacturing a semiconductor device, according to another embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

11 : 반도체기판 15 : 필드산화막11: semiconductor substrate 15: field oxide film

16 : 홈 17 : 게이트산화막16: groove 17: gate oxide film

19 : 폴리실리콘막 21 : 도전성 금속막19 polysilicon film 21 conductive metal film

22 : 하드마스크막 23 : 제1게이트 22: hard mask film 23: the first gate

25 : 제2게이트 C1, C2 : 셀영역 25: second gate C1, C2: cell region

P1, P2 : 주변영역P1, P2: Peripheral Area

본 발명은 반도체 소자의 제조방법에 관한 것으로서, 특히, 메모리 셀영역 내의 셀을 선택하거나 셀에 데이터 전달을 위한 구동소자가 주변 영역에 형성되는 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device in which a driving device for selecting a cell in a memory cell area or transferring data to a cell is formed in a peripheral area.

일반적으로 메모리장치를 포함하는 반도체장치의 고밀도화가 진행됨에 따라 작은 면적을 갖는 소자의 높은 전류 구동 능력(current drivability) 및 단채널 여유도(short channel margin)을 확보를 위해 서브-드레쉬홀드 스윙(sub-threshold swing) 및 DIBL(Drain Induced Barrier Lowing) 값이 낮은 셀을 형성하는 것이 매우 중요한 문제가 되고 있다.In general, as the semiconductor device including the memory device is increased in density, the sub-threshold swing (H) may be used to secure a high current drivability and a short channel margin of a small-area device. The formation of cells having low sub-threshold swing and drain induced barrier lowing (DIBL) values has become a very important problem.

종래에는 셀영역 내의 트랜지스터는 구동 전류를 확보하기 위해 얇은 게이트 산화막 및 낮은 얇은 접합 깊이 등에 의해 유효 채널폭(effective channel width)을 증가시키거나, 또는, 오프시 누설전류를 감소하기 위한 단채널 여유도를 증가시키기 위해 리세스 게이트를 이용하여 유효 채널 길이(effective channel length)를 중가시킬 수 있다.Conventionally, transistors in a cell region have an effective channel width due to a thin gate oxide film and a low thin junction depth, etc. to secure a driving current, or a short channel margin for reducing leakage current when turned off. The recess gate may be used to increase the effective channel length in order to increase.

그러나, 주변영역의 트랜지스터는 유효 채널폭(effective channel width)을 증가시키는데 한계가 있어 전류 구동 능력이 낮고 단채널 여유도를 확보하기 어려운 문제점이 있었다.However, the transistors in the peripheral region have a limit in increasing the effective channel width, which results in low current driving capability and difficulty in securing short channel margins.

따라서, 본 발명의 목적은 주변영역의 트랜지스터의 유효 채널폭(effective channel width)을 증가시켜 높은 전류 구동 능력과 단채널 여유도를 향상시킬 수 있는 반도체 소자의 제조방법을 제공함에 있다.Accordingly, it is an object of the present invention to provide a method of manufacturing a semiconductor device capable of increasing the effective channel width of a transistor in a peripheral region to improve high current driving capability and short channel margin.

상기 목적을 달성하기 위해 본 발명에 따른 반도체 소자의 제조방법은, 셀영역과 주변영역으로 구획되고, 활성영역을 한정하는 필드산화막이 구비된 반도체기판을 제공하는 단계; 상기 주변영역 상에 형성된 필드산화막 부분을 리세스하여 주변영역의 활성영역 측면을 노출시키는 단계; 상기 주변영역의 활성영역 측면이 노출된 기판 결과물 상에 게이트절연막과 게이트도전막을 차례로 형성하는 단계; 상기 셀영역과 주변영역에서의 게이트도전막의 높이가 같아지도록 상기 게이트도전막을 평탄화하는 단계; 및 상기 게이트도전막과 게이트절연막을 식각하여 셀영역에 제1게이트를 형성함과 아울러 주변영역에 활성영역의 측면도 채널영역으로 포함하는 제2게이트를 형성하는 단계;를 포함한다. According to an aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method comprising: providing a semiconductor substrate having a field oxide film partitioned into a cell region and a peripheral region and defining an active region; Recessing a portion of the field oxide layer formed on the peripheral region to expose an active region side of the peripheral region; Sequentially forming a gate insulating film and a gate conductive film on a substrate resultant in which side surfaces of the active region of the peripheral region are exposed; Planarizing the gate conductive layer so that the heights of the gate conductive layers in the cell region and the peripheral region are the same; And etching the gate conductive layer and the gate insulating layer to form a first gate in a cell region, and to form a second gate including a side surface of the active region as a channel region in a peripheral region.

여기서, 상기 필드산화막 부분을 리세스하는 단계는 주변영역의 필드산화막의 전영역의 일부 두께를 리세스한다. Here, the step of recessing the field oxide portion recesses a part thickness of the entire region of the field oxide layer in the peripheral region.

상기 필드산화막 부분을 리세스하는 단계는 주변영역의 필드산화막 부분 중 게이트가 형성될 필드산화막 부분의 일부 두께를 리세스한다.Recessing the field oxide layer portion recesses a part thickness of the field oxide layer portion in which a gate is to be formed among the field oxide layer portions in the peripheral region.

상기 리세스는 습식식각 또는 건식식각 방식으로 수행한다.The recess is performed by wet etching or dry etching.

이때, 상기 습식식각은 BOE 또는 HF 용액을 이용하여 수행한다.In this case, the wet etching is performed using a BOE or HF solution.

상기 필드산화막 부분을 리세스하는 단계는 주변영역에 형성될 게이트의 채널 폭이 조절되도록 필드산화막의 리세스 두께를 조절하면서 수행한다.The step of recessing the field oxide layer portion is performed while adjusting the recess thickness of the field oxide layer so that the channel width of the gate to be formed in the peripheral region is adjusted.

삭제delete

여기서, 상기 평탄화는 CMP 또는 에치백 방식으로 수행한다. Here, the planarization is performed by CMP or etch back.

(실시예)(Example)

이하에서는, 첨부한 도면을 참조하여 본 발명의 실시예를 자세하게 설명하도 록 한다. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 도 1c는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 도시한 사시도 및 단면도이다.1A to 1C are perspective and cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 1a를 참조하면, 셀영역(C1)과 주변영역(P1)을 갖는 반도체기판(11) 상에 통상의 STI(Shallow Trench Isolation) 방법에 의해 소자의 활성영역을 한정하는 필드산화막(15)을 형성한다. Referring to FIG. 1A, a field oxide film 15 is formed on a semiconductor substrate 11 having a cell region C1 and a peripheral region P1 to define an active region of a device by a conventional shallow trench isolation (STI) method. Form.

상기에서 필드산화막(15)은 반도체기판(11)의 필드 예정 영역을 이방성 식각 또는 경사 식각하여 트렌치를 형성한 후, 상기 트렌치를 채우도록 실리콘산화막을 화학기상증착(CVD) 방법으로 증착한 다음, 상기 실리콘산화막을 화학기계적연마(CMP) 방법으로 평탄화하여 형성한다. The field oxide film 15 is formed by forming an trench by anisotropically etching or obliquely etching a field predetermined region of the semiconductor substrate 11, and then depositing a silicon oxide film by chemical vapor deposition (CVD) to fill the trench. The silicon oxide film is formed by planarization by chemical mechanical polishing (CMP).

도 1b를 참조하면, 주변영역(P1)의 필드산화막(15)을 선택적으로 노출시키는 마스크패턴(미도시)을 형성한 후, 노출된 주변영역(P1) 필드산화막(15)의 일부 두께를 리세스한다. 이 때, 주변영역(P1)의 활성영역 측면이 노출된다.Referring to FIG. 1B, after forming a mask pattern (not shown) for selectively exposing the field oxide film 15 of the peripheral region P1, the thickness of the exposed peripheral region P1 field oxide layer 15 is reduced. Seth. At this time, the active region side surface of the peripheral region P1 is exposed.

상기 필드산화막(15)의 리세스는 BOE 또는 HF 등의 식각 용액을 이용한 습식식각 방식으로 수행한다. 본 발명에서는, 상기한 바와 같이, 필드산화막(15)을 습식식각 방식으로 리세스하였지만, 필요에 따라서는, 상기 습식식각 방식 대신에 RIE 또는 플라즈마 식각 등의 건식식각 방식으로 필드산화막(15)의 리세스 공정을 수행할 수도 있다. The recess of the field oxide layer 15 is performed by a wet etching method using an etching solution such as BOE or HF. In the present invention, as described above, the field oxide film 15 is recessed by a wet etching method. However, if necessary, the field oxide film 15 may be replaced by a dry etching method such as RIE or plasma etching instead of the wet etching method. A recess process may be performed.

또한, 상기 필드산화막(15)을 리세스하는 단계는 주변영역(P1)에 형성될 게이트의 채널 폭이 조절되도록 필드산화막(15)의 리세스 두께를 조절하여 수행할 수 있다. In addition, the recess of the field oxide layer 15 may be performed by adjusting the recess thickness of the field oxide layer 15 so that the channel width of the gate to be formed in the peripheral region P1 is adjusted.

도 1c의 사시도 및 단면도를 참조하면, 상기 주변영역(P1)의 필드산화막(15) 일부 두께가 식각된 기판(11) 상에 열산화 방법에 의해 게이트산화막(17)을 형성한다. 이 때, 주변영역(P1)의 활성영역의 노출된 측면 부분에도 상기 게이트산화막(17)이 형성된다.Referring to the perspective view and the cross-sectional view of FIG. 1C, the gate oxide layer 17 is formed on the substrate 11 where the thickness of a portion of the field oxide layer 15 of the peripheral region P1 is etched. In this case, the gate oxide layer 17 is formed on the exposed side surface of the active region of the peripheral region P1.

여기서, 상기 게이트산화막(17)은 통상적인 습식 또는 건식 산화방식으로 형성할 수 있으며, 단차 피복성(step coverage)을 향상시키기 위해서 ISSG(In-situ Steam Generation) 또는 LPRO(Low Pressure Radical Oxidation) 방식으로 형성할 수도 있다. Here, the gate oxide film 17 may be formed by a conventional wet or dry oxidation method, in order to improve step coverage, an in-situ steam generation (ISSG) or a low pressure radial oxidation (LPRO) method. It can also be formed.

또한, 상기 게이트산화막(17)은 HfO2, HfxSiyO, Ta2O5, Al2O3 및 ZrO2와 같은 고유전(High k) 물질막으로 형성할 수 있고, 상기 게이트산화막(17)을 형성한 후, N2 플라즈마를 사용하여 그 표면을 질화시킬 수 도 있다. In addition, the gate oxide layer 17 may be formed of a high k material layer such as HfO 2, Hf x Si y O, Ta 2 O 5, Al 2 O 3, and ZrO 2, and after forming the gate oxide layer 17, N 2 Plasma can also be used to nitride the surface.

그런다음, 상기 게이트산화막(17) 상에 폴리실리콘막(19)을 증착하되, 이때, 상기 폴리실리콘막(19)의 증착은 필드산화막(15)의 일부 두께가 식각된 주변영역(P1)을 완전히 매립하도록 충분히 두꺼운 두께로 형성한다. 여기서, 상기 증착된 폴리실리콘막(19)은 최종적인 게이트 폴리실리콘막 두께 보다 충분히 두꺼우며, 셀영역(C1)과 주변영역(P1)에서 단차를 갖고 형성된다. 그러므로, 다음 공정으로, 셀영역(C1)과 주변영역(P1)에서의 폴리실리콘막(19)의 높이 차를 극복하기 위해 CMP 또는 에치백 방식으로 상기 폴리실리콘막(19)을 평탄화하여, 셀영역(C1)과 주변영 역(P1)에서의 폴리실리콘막(19) 높이를 동일하게 맞춰준다. Then, a polysilicon layer 19 is deposited on the gate oxide layer 17, wherein the deposition of the polysilicon layer 19 is performed by forming a peripheral region P1 in which a part thickness of the field oxide layer 15 is etched. It is formed thick enough to be completely embedded. Here, the deposited polysilicon film 19 is thicker than the final gate polysilicon film thickness and is formed with steps in the cell region C1 and the peripheral region P1. Therefore, in the next step, the polysilicon film 19 is planarized by a CMP or etch back method to overcome the height difference between the polysilicon film 19 in the cell region C1 and the peripheral region P1. The height of the polysilicon film 19 in the region C1 and the peripheral region P1 is equally adjusted.

그런다음, 상기 폴리실리콘막(19) 상에 도전성 금속막(21)과 하드마스크막(22)을 순차적으로 증착한 후, 상기 하드마스크막(22), 도전성 금속막(21), 폴리실리콘막(19) 및 게이트산화막(17)을 게이트 형태로 패터닝하여 셀영역(C1)과 주변영역(P1)에 각각 제1게이트(23)와 제2게이트(25)를 형성한다. Then, the conductive metal film 21 and the hard mask film 22 are sequentially deposited on the polysilicon film 19, and then the hard mask film 22, the conductive metal film 21, and the polysilicon film are deposited. The gate 19 and the gate oxide layer 17 are patterned to form first gates 23 and second gates 25 in the cell region C1 and the peripheral region P1, respectively.

이때, 주변영역(P1)의 제2게이트(25)는 활성영역의 측면도 채널영역이 되므로 활성영역의 상부면만 채널영역으로 사용하였던 종래에 비해 채널영역의 폭이 증가된다. 그러므로, 주변영역(P1)에 형성되는 제2게이트(25)를 포함하는 소자의 유효 채널폭이 증가되고, 전류 구동 능력과 단채널 여유도가 향상된다.At this time, the second gate 25 of the peripheral region P1 also becomes a channel region, so that the width of the channel region is increased compared to the conventional case in which only the upper surface of the active region is used as the channel region. Therefore, the effective channel width of the element including the second gate 25 formed in the peripheral region P1 is increased, and the current driving capability and short channel margin are improved.

한편, 도 2a 및 도 2b는 본 발명의 다른 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정별 사시도 및 단면도이다.2A and 2B are perspective and cross-sectional views of processes for describing a method of manufacturing a semiconductor device, according to another embodiment of the present invention.

도 2a를 참조하면, 셀영역(C2)과 주변영역(P2)을 갖는 반도체기판(11) 상에 도 1a와 동일한 공정을 진행하여 트렌치(13) 내에 필드산화막(15)을 형성한다.Referring to FIG. 2A, the field oxide film 15 is formed in the trench 13 by performing the same process as that of FIG. 1A on the semiconductor substrate 11 having the cell region C2 and the peripheral region P2.

그리고, 상기 기판 결과물 상에 주변영역(P2)의 필드산화막(15) 부분 중 게이트가 형성될 영역의 필드산화막(15) 부분을 선택적으로 노출시키는 마스크패턴(미도시)을 형성한 후, 상기 마스크패턴을 식각장벽으로 이용하여 노출된 필드산화막(15) 부분의 일부 두께를 리세스하여, 활성영역의 양측면을 노출시키는 홈(16)을 형성한다. 여기서, 상기 홈(16)을 형성하기 위한 필드산화막(15)의 리세스는, 전술한 실시예의 경우와 같이, BOE 또는 HF 용액을 이용한 습식식각 방식이나, 건식식각 방식으로 수행할 수 있다. A mask pattern (not shown) for selectively exposing a portion of the field oxide layer 15 of the region where the gate is to be formed in the portion of the field oxide layer 15 of the peripheral region P2 is formed on the substrate resultant, and then the mask is formed. A portion of the exposed portion of the field oxide film 15 is recessed using the pattern as an etch barrier to form grooves 16 exposing both sides of the active region. Here, the recess of the field oxide layer 15 for forming the groove 16 may be performed by a wet etching method using a BOE or HF solution or a dry etching method as in the above-described embodiment.

또한, 상기 홈(16)의 높이를 조절하여 노출되는 활성영역의 측면 높이를 조절하고, 이에 의해, 이 후에 형성될 게이트의 유효 채널 폭을 조절할 수 있다.In addition, the height of the side surface of the exposed active region may be adjusted by adjusting the height of the groove 16, thereby adjusting the effective channel width of the gate to be formed later.

도 2b의 사시도 및 단면도를 참조하면, 상기 기판 결과물 상에 열산화 방법에 의해 게이트산화막(17)을 형성한다. 이 때, 주변영역(P2)의 활성영역의 노출된 측면 부분에도 상기 게이트산화막(17)이 형성된다.Referring to the perspective view and the cross-sectional view of FIG. 2B, a gate oxide layer 17 is formed on the substrate resultant by thermal oxidation. In this case, the gate oxide layer 17 is formed on the exposed side surface of the active region of the peripheral region P2.

여기서, 상기 게이트산화막(17)은 통상적인 습식 또는 건식 산화방식으로 형성할 수 있으며, 단차 피복성(step coverage)을 향상시키기 위해서 ISSG(In-situ Steam Generation) 또는 LPRO(Low Pressure Radical Oxidation) 방식으로 형성할 수도 있다. Here, the gate oxide film 17 may be formed by a conventional wet or dry oxidation method, in order to improve step coverage, an in-situ steam generation (ISSG) or a low pressure radial oxidation (LPRO) method. It can also be formed.

또한, 상기 게이트산화막(17)은 HfO2, HfxSiyO, Ta2O5, Al2O3 및 ZrO2와 같은 고유전(High k) 물질막으로 형성할 수 있고, 상기 게이트산화막(17)을 형성한 후, N2 플라즈마를 사용하여 그 표면을 질화시킬 수 도 있다. In addition, the gate oxide layer 17 may be formed of a high k material layer such as HfO 2, Hf x Si y O, Ta 2 O 5, Al 2 O 3, and ZrO 2, and after forming the gate oxide layer 17, N 2 Plasma can also be used to nitride the surface.

그런다음, 상기 게이트산화막(17) 상에 상기 홈(16)을 채우도록 충분한 두께로 폴리실리콘막(19)을 증착하고 평탄화한다. Then, the polysilicon film 19 is deposited and planarized to a thickness sufficient to fill the groove 16 on the gate oxide film 17.

이어서, 상기 폴리실리콘막(19) 상에 도전성 금속막(21)과 하드마스크막(22)을 순차적으로 증착하고나서, 상기 막들(22, 21, 19, 17)을 차례로 패터닝하여 셀영역(C2)과 주변영역(P2)에 각각 제1게이트(23) 및 제2게이트(25)를 형성한다. Subsequently, the conductive metal film 21 and the hard mask film 22 are sequentially deposited on the polysilicon film 19, and then the films 22, 21, 19, and 17 are sequentially patterned to form a cell region C2. ) And the first gate 23 and the second gate 25 in the peripheral region P2, respectively.

이 때, 주변영역(P2)의 제2게이트(25)는 활성영역의 측면도 채널영역이 되므로 활성영역의 상부면만 채널영역으로 사용하였던 종래에 비해 채널영역의 폭이 증 가된다. 그러므로, 주변영역(P1)에 형성될 제2게이트(25)를 포함하는 소자의 유효 채널폭이 증가되고, 전류 구동 능력과 단채널 여유도가 향상된다.At this time, the second gate 25 of the peripheral region P2 also becomes a channel region, so that the width of the channel region is increased compared to the conventional case in which only the upper surface of the active region is used as the channel region. Therefore, the effective channel width of the element including the second gate 25 to be formed in the peripheral region P1 is increased, and the current driving capability and short channel margin are improved.

한편, 상기 폴리실리콘막(19)은 최종적인 게이트 폴리실리콘막(19)의 두께 보다 두껍게 형성하고 나서, 셀영역(C2)과 주변영역(P2)에서의 폴리실리콘막(19)의 높이 차를 극복하기 위해 CMP 또는 에치백 방식으로 평탄화한다. On the other hand, the polysilicon film 19 is formed thicker than the thickness of the final gate polysilicon film 19, the height difference between the polysilicon film 19 in the cell region (C2) and the peripheral region (P2). To overcome, planarize by CMP or etch back method.

이상에서 설명한 바와 같이, 본 발명에 따른 반도체 소자의 제조방법은 주변영역의 활성영역의 측면이 노출되도록 주변영역의 필드산화막을 리세스하되, 주변영역의 필드산화막의 전영역의 일부 두께를 리세스하거나, 주변영역의 필드산화막 부분 중 게이트가 형성될 필드산화막 부분의 일부 두께를 리세스한다. 이에 따라, 주변영역의 게이트는 활성영역의 측면도 채널영역이 되므로 활성영역의 상부면만 채널영역으로 사용하였던 종래에 비해 채널영역의 폭이 증가된다. As described above, the method of manufacturing a semiconductor device according to the present invention recesses the field oxide film of the peripheral area so that the side surface of the active area of the peripheral area is exposed, but recesses a part thickness of the entire area of the field oxide film of the peripheral area. Alternatively, some thicknesses of the field oxide film portion in which the gate is to be formed are recessed in the field oxide film portion in the peripheral region. Accordingly, the width of the channel region is increased compared to the conventional case in which only the upper surface of the active region is used as the channel region because the gate of the peripheral region becomes the channel region of the active region.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

따라서, 본 발명은 주변영역에 형성되는 제 2 게이트는 유효 채널폭이 증가되므로 전류 구동 능력과 단채널 여유도가 향상되는 잇점이 있다.Accordingly, in the present invention, since the effective channel width of the second gate formed in the peripheral region is increased, current driving capability and short channel margin are improved.

Claims (8)

셀영역과 주변영역으로 구획되고, 활성영역을 한정하는 필드산화막이 구비된 반도체기판을 제공하는 단계; Providing a semiconductor substrate divided into a cell region and a peripheral region, the semiconductor substrate having a field oxide film defining an active region; 상기 주변영역 상에 형성된 필드산화막 부분을 리세스하여 주변영역의 활성영역 측면을 노출시키는 단계; Recessing a portion of the field oxide layer formed on the peripheral region to expose an active region side of the peripheral region; 상기 주변영역의 활성영역 측면이 노출된 기판 결과물 상에 게이트절연막과 게이트도전막을 차례로 형성하는 단계; Sequentially forming a gate insulating film and a gate conductive film on a substrate resultant in which side surfaces of the active region of the peripheral region are exposed; 상기 셀영역과 주변영역에서의 게이트도전막의 높이가 같아지도록 상기 게이트도전막을 평탄화하는 단계; 및 Planarizing the gate conductive layer so that the heights of the gate conductive layers in the cell region and the peripheral region are the same; And 상기 게이트도전막과 게이트절연막을 식각하여 셀영역에 제1게이트를 형성함과 아울러 주변영역에 활성영역의 측면도 채널영역으로 포함하는 제2게이트를 형성하는 단계;Etching the gate conductive layer and the gate insulating layer to form a first gate in a cell region, and to form a second gate including a side surface of the active region as a channel region in a peripheral region; 를 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.Method of manufacturing a semiconductor device comprising a. 제 1 항에 있어서, 상기 필드산화막 부분을 리세스하는 단계는 주변영역의 필드산화막의 전영역의 일부 두께를 리세스하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the recessing of the field oxide film portion recesses a part thickness of an entire region of the field oxide film in the peripheral region. 제 1 항에 있어서, 상기 필드산화막 부분을 리세스하는 단계는 주변영역의 필드산화막 부분 중 게이트가 형성될 필드산화막 부분의 일부 두께를 리세스하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the recessing of the field oxide layer portion recesses a part thickness of the field oxide layer portion in which a gate is to be formed among the field oxide layer portions of the peripheral region. 제 2 항 또는 제 3 항에 있어서, 상기 리세스는 습식식각 또는 건식식각 방식으로 수행하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 2, wherein the recess is performed by a wet etching method or a dry etching method. 제 4 항 있어서, 상기 습식식각은 BOE 또는 HF 용액을 이용하여 수행하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 4, wherein the wet etching is performed using a BOE or HF solution. 제 1 항에 있어서, 상기 필드산화막 부분을 리세스하는 단계는 주변영역에 형성될 게이트의 채널 폭이 조절되도록 필드산화막의 리세스 두께를 조절하여 수행하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the recessing of the field oxide layer portion is performed by adjusting a recess thickness of the field oxide layer to adjust a channel width of a gate to be formed in the peripheral region. 삭제delete 제 1 항에 있어서, 상기 평탄화는 CMP 또는 에치백 방식으로 수행하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the planarization is performed by CMP or etch back.
KR1020050058568A 2005-06-30 2005-06-30 Method of manufacturing semiconductor device KR100753410B1 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH102005A (en) * 1996-06-18 1998-01-06 Daiko Kagaku Kogyo Kk Method and tool for fitting mesh panel
KR20050002259A (en) * 2003-06-30 2005-01-07 삼성전자주식회사 Method for fabricating a finfet in a semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH102005A (en) * 1996-06-18 1998-01-06 Daiko Kagaku Kogyo Kk Method and tool for fitting mesh panel
KR20050002259A (en) * 2003-06-30 2005-01-07 삼성전자주식회사 Method for fabricating a finfet in a semiconductor device

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