CN114725108A - Semiconductor structure and preparation method thereof - Google Patents

Abstract

The invention relates to a semiconductor structure and a preparation method thereof. The preparation method of the semiconductor structure comprises the following steps: providing a substrate; forming a groove in the substrate, wherein the bottom and the side wall of the groove are covered by a dielectric layer; forming a sacrificial layer in the dielectric layer; forming a conductive layer, wherein the upper surface of the conductive layer is lower than the upper surface of the substrate; removing the sacrificial layer to form air side walls on two opposite sides of the conductive layer; and forming an insulating protection layer, wherein the insulating protection layer covers the upper surface of the conductive layer and the top of the air side wall. According to the preparation method of the semiconductor structure, the conducting layer with larger height is formed in the groove, so that the cross-sectional area of the conducting layer can be increased under the condition that the line width of the word line structure is not changed, the resistance of the word line is greatly reduced, the on-state current of the word line is improved, and the response speed of a transistor is improved; in addition, the air side walls are formed on the two opposite sides of the conducting layer, so that an electric field between the grid electrode and the drain electrode can be reduced, GIDL is reduced, the crystal power consumption of the transistor is reduced, and the reliability of the transistor is improved.

Description

Semiconductor structure and preparation method thereof

Technical Field

The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a preparation method thereof.

Background

With the development of DRAMs toward high speed, high integration density, and low power consumption, the size of DRAM device structures is becoming smaller, and especially in the process of manufacturing DRAM devices with smaller line widths, higher requirements are placed on the material, morphology, size, electrical properties, and the like of word lines.

The critical dimension of the word line structure is continuously reduced, but the electrical performance requirement of the transistor is not reduced, which tends to generate a large gate induced drain leakage current (GIDL) in the transistor, and seriously affects the reliability of the transistor. Meanwhile, the resistance of the word line is closely related to the response speed of the semiconductor device, and along with the further reduction of the line width of the word line, the resistance of the word line is increased rapidly, so that the response speed of the semiconductor device is reduced.

Disclosure of Invention

Therefore, it is necessary to provide a semiconductor structure and a method for manufacturing the same to reduce the resistance of the word line structure, reduce the GIDL current, and improve the reliability and response speed of the device, in order to solve the problems of increased word line resistance, increased GIDL current, and the like caused by the miniaturization of the word line structure.

One embodiment of the present application discloses a semiconductor structure, comprising: the substrate is provided with grooves, the grooves comprise a first groove close to the surface of the substrate and a second groove far away from the surface of the substrate, and the width of the first groove is larger than that of the second groove; the dielectric layer covers the bottom and the side wall of the groove; the conducting layer is positioned in the groove, and the upper surface of the conducting layer is lower than the upper surface of the substrate; the air side walls are positioned in the first grooves and positioned on two opposite sides of the conducting layer; and the insulating protection layer covers the upper surface of the conductive layer and the top of the air side wall.

According to the semiconductor structure, the air side walls are arranged on the two sides of the conducting layer, and the air side walls are applied to the transistor structure, so that an electric field between the grid electrode and the drain electrode can be reduced, GIDL leakage current is reduced, static power consumption of the transistor is reduced, the service life of a device is prolonged, and the reliability of the transistor is improved.

In one embodiment, an upper surface of the conductive layer is flush with a middle or middle upper portion of the first trench.

According to the semiconductor structure, the conducting layer with the larger height is formed, so that word line resistance can be reduced under the condition that the word line width is not changed, word line conduction current is improved, and the response speed of a semiconductor device is improved.

In one embodiment, the conductive layer comprises a metal layer and a metal barrier layer covering the bottom and the side wall of the metal layer.

In one embodiment, the air side wall is located between the side wall of the conductive layer and the dielectric layer, and the top of the air side wall is flush with the upper surface of the conductive layer.

In one embodiment, the air side wall is a space formed by the conductive layer, the insulating protective layer and the dielectric layer in a closed manner.

A method of fabricating a semiconductor structure, comprising: providing a substrate; forming a groove in the substrate, wherein the bottom and the side wall of the groove are covered by a dielectric layer; forming a sacrificial layer in the dielectric layer; forming a conductive layer, wherein the upper surface of the conductive layer is lower than the upper surface of the substrate; removing the sacrificial layer to form air side walls on two opposite sides of the conductive layer; and forming an insulating protection layer, wherein the insulating protection layer covers the upper surface of the conducting layer and the top of the air side wall.

According to the preparation method of the semiconductor structure, the conducting layer with larger height is formed in the groove, so that the cross-sectional area of the conducting layer can be increased under the condition that the line width of the word line structure is not changed, the resistance of the word line is greatly reduced, the on-state current of the word line is improved, and the response speed of a transistor is improved; in addition, the air side walls are formed on the two opposite sides of the conducting layer, so that an electric field between the grid electrode and the drain electrode can be reduced, GIDL is reduced, the crystal power consumption of the transistor is reduced, and the reliability of the transistor is improved.

In one embodiment, the dielectric layer comprises a first dielectric layer and a second dielectric layer; forming a trench in the substrate, wherein the bottom and sidewalls of the trench are covered by a dielectric layer, comprising: forming a first trench in the substrate, the first trench having a first width; forming the first dielectric layer on the bottom and the side wall of the first groove; removing the first dielectric layer at the bottom of the first trench, and forming a second trench at the bottom of the first trench, wherein the second trench has a second width, and the second width is smaller than the first width; and forming the second dielectric layer, wherein the second dielectric layer covers the bottom and the side wall of the second groove and the side wall of the first dielectric layer.

In one embodiment, the first dielectric layer and the second dielectric layer comprise a silicon oxide layer.

In one embodiment, the thickness of the first dielectric layer comprises 5nm to 15 nm; the thickness of the second dielectric layer comprises 5nm-15 nm.

In one embodiment, the forming a sacrificial layer in the dielectric layer includes: doping a first component into the dielectric layer to obtain the sacrificial layer; and the thickness of the sacrificial layer is smaller than that of the dielectric layer.

In one embodiment, the first component comprises phosphorus.

In one embodiment, the doping the dielectric layer with the first component includes: and doping the first component into the second dielectric layer positioned on the side wall of the first dielectric layer to obtain the sacrificial layer.

In one embodiment, the thickness of the sacrificial layer is equal to the thickness of the second dielectric layer.

In one embodiment, the forming the conductive layer includes: forming a metal barrier layer, wherein the metal barrier layer covers the surfaces of the sacrificial layer and the dielectric layer; forming a metal layer, wherein the metal layer fills the groove and covers the upper surface of the substrate; removing the metal layer on the upper surface of the substrate, and reducing the thickness of the metal layer in the groove to enable the upper surface of the metal layer to be lower than the upper surface of the substrate; and removing part of the metal barrier layer so that the top of the metal barrier layer is flush with the upper surface of the metal layer.

In one embodiment, the upper surface of the metal layer is flush with the middle or middle upper portion of the sacrificial layer.

In one embodiment, the removing the sacrificial layer to form air side walls on two opposite sides of the conductive layer includes: and removing the sacrificial layer by adopting an etching process to form the air side wall, wherein the air side wall exposes the side wall of the first dielectric layer, the top of the second dielectric layer and part of the side wall of the conductive layer.

In one embodiment, the forming the insulating protection layer includes: forming a layer of insulating material covering the top of the air sidewalls, the upper surface of the conductive layer, and the upper surface of the substrate; removing the insulating material layer on the upper surface of the substrate to obtain the insulating protective layer; wherein an upper surface of the insulating protection layer is flush with an upper surface of the substrate.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain drawings of other embodiments without creative efforts based on the drawings.

FIG. 1 is a block flow diagram of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

FIG. 2 is a cross-sectional view of a semiconductor structure after forming a patterned photoresist layer on a substrate according to an embodiment of the present application;

FIG. 3 is a cross-sectional view of a semiconductor structure after forming a first trench in an embodiment of the present application;

FIG. 4 is a cross-sectional view of a semiconductor structure after forming a first dielectric layer in an embodiment of the present application;

FIG. 5 is a cross-sectional view of a semiconductor structure after forming a second trench in an embodiment of the present application;

FIG. 6 is a cross-sectional view of a semiconductor structure after forming a second dielectric layer in an embodiment of the present application;

FIG. 7 is a cross-sectional view of a semiconductor structure after forming a sacrificial layer in a dielectric layer on one side of a trench in accordance with an embodiment of the present application;

FIG. 8 is a cross-sectional view of a semiconductor structure after a sacrificial layer is formed in a dielectric layer on the other side of a trench in accordance with an embodiment of the present invention;

FIG. 9 is a cross-sectional view of a semiconductor structure after forming a metal barrier layer according to an embodiment of the present application;

FIG. 10 is a cross-sectional view of a semiconductor structure after forming a metal layer according to an embodiment of the present application;

FIG. 11 is a cross-sectional view of a semiconductor structure after reducing the height of a metal barrier layer in an embodiment of the present application;

FIG. 12 is a schematic cross-sectional view illustrating a semiconductor structure after forming an air sidewall in an embodiment of the present application;

fig. 13 is a schematic cross-sectional view of a semiconductor structure after an insulating protection layer is formed according to an embodiment of the present application.

The reference numbers illustrate:

10. a substrate; 11. patterning the photoresist layer; 20. a trench; 21. a first trench; 22. a second trench; 30. a dielectric layer; 31. a first dielectric layer; 32. a second dielectric layer; 33. a sacrificial layer; 40. a conductive layer; 41. a metal layer; 42. a metal barrier layer; 50. an air side wall; 60. and an insulating protective layer.

Detailed Description

To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

In describing positional relationships, unless otherwise specified, when an element such as a layer, film or substrate is referred to as being "on" another layer, it can be directly on the other layer or intervening layers may also be present. Further, when a layer is referred to as being "under" another layer, it can be directly under, or one or more intervening layers may also be present. It will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

Where the terms "comprising," "having," and "including" are used herein, another element may be added unless an explicit limitation is used, such as "only," "consisting of … …," etc. Unless mentioned to the contrary, terms in the singular may include the plural and are not to be construed as being one in number.

With the development of DRAMs toward high speed, high integration density, and low power consumption, the size of DRAM device structures is becoming smaller, and especially in the process of manufacturing DRAM devices with smaller line widths, higher requirements are placed on the material, morphology, size, electrical properties, and the like of word lines. The critical dimension of the word line structure is continuously reduced, but the requirement of electrical performance is not reduced, which tends to generate a large gate induced drain leakage current (GIDL) in the transistor, and thus the reliability of the transistor is seriously affected. Meanwhile, the resistance of the word line is closely related to the response speed of the semiconductor device, and along with the further reduction of the line width of the word line, the resistance of the word line is increased rapidly, so that the response speed of the semiconductor device is reduced.

In order to solve the above problem, an embodiment of the present application discloses a method for manufacturing a semiconductor structure, as shown in fig. 1, including:

s10: providing a substrate;

s20: forming a groove in the substrate, wherein the bottom and the side wall of the groove are covered by a dielectric layer;

s30: forming a sacrificial layer in the dielectric layer;

s40: forming a conductive layer, wherein the upper surface of the conductive layer is lower than the upper surface of the substrate;

s50: removing the sacrificial layer to form air side walls on two opposite sides of the conductive layer;

s60: and forming an insulating protection layer, wherein the insulating protection layer covers the upper surface of the conductive layer and the top of the air side wall.

According to the preparation method of the semiconductor structure, the air side wall is formed between the dielectric layer and the conducting layer, so that an electric field between the grid electrode and the drain electrode can be reduced, the GIDL effect of the device is effectively improved, the leakage current of the device in a closed state is reduced, the static power consumption is reduced, and the service life of the device is prolonged.

For example, the above method for fabricating a semiconductor structure may be used for fabricating a word line structure, such as a buried word line structure. Specifically, the substrate 10 may include, but is not limited to, a silicon substrate or a silicon-on-insulator substrate. In step S20, the trenches 20 include a first trench 21 close to the surface of the substrate 10 and a second trench 22 far from the surface of the substrate 10, and the dielectric layer 30 includes a first dielectric layer 31 and a second dielectric layer 32. Referring to fig. 2 to 6, the specific steps of forming the trench 20 and the dielectric layer 30 include:

s21: a first trench 21 is formed in the substrate 10, the first trench 21 having a first width.

For example, as shown in fig. 2, a patterned photoresist layer 11 may be formed on the upper surface of the substrate 10, and the position and line width of the first trench 21 may be defined by using the pattern in the patterned photoresist layer 11. The first trench 21 has a first width, which may be, for example, 30nm to 100nm, for example, 30nm, 50nm, 70nm, or 100 nm.

Optionally, in some embodiments, a hard mask layer may also be formed between the patterned photoresist layer 11 and the substrate 10 to improve the quality and accuracy of the pattern transfer.

Illustratively, as shown in fig. 3, an etching process is used to form a first trench 21 in the substrate 10. As an example, the substrate 10 may be etched using BCl3 gas and Cl gas, and the rf bias power used for the etching process may be 100 w to 700 w, such as 100 w, 300 w, 500 w, or 700 w; the etch pressure may be 5 mtorr to 20 mtorr, such as 5 mtorr, 10 mtorr, 15 mtorr, or 20 mtorr; the etching temperature may be 20 degrees celsius to 100 degrees celsius, such as 20 degrees celsius, 50 degrees celsius, 70 degrees celsius, or 100 degrees celsius. As an example, the depth of the first trench 21 may be 50nm to 100nm, e.g. 50nm, 70nm or 100 nm.

Alternatively, in some embodiments, after the first trench 21 is formed, a cleaning process may be further used to remove by-products or impurity particles remaining on the surface of the first trench 21. For example, the cleaning process may include, but is not limited to, an SPM cleaning process, and the ambient temperature for performing the cleaning process may be 25 to 50 degrees celsius, such as 25, 30, 40, or 50 degrees celsius.

Alternatively, in some embodiments, the first trench 21 may be formed in the substrate 10 by using a Self-Aligned double Patterning (SADP) process or a Self-Aligned Quadruple Patterning (SAQP) process.

S22: a first dielectric layer 31 is formed on the bottom and sidewalls of the first trench 21, as shown in fig. 4.

For example, the first dielectric layer 31 may be deposited in the first trench 21 by an in-situ water vapor growth process, an atomic layer deposition process, or a combination thereof, and the first dielectric layer 31 covers the bottom and the sidewalls of the first trench 21. As an example, the first dielectric layer 31 may be a layer of material with a relatively high dielectric constant, such as a silicon dioxide layer. The thickness of the first dielectric layer 31 may be 5nm to 15nm, for example 5nm, 7nm, 10nm or 15 nm. The upper surface of the first dielectric layer 31 is flush with the upper surface of the substrate 10.

S23: the first dielectric layer 31 at the bottom of the first trench 21 is removed, and a second trench 22 is formed at the bottom of the first trench 21, where the second trench 22 has a second width smaller than the first width, as shown in fig. 5.

For example, the first dielectric layer 31 at the bottom of the first trench 21 may be removed first by using a directional etching process, and for example, the first dielectric layer 31 may be etched in a vertical direction by using an anisotropic plasma etching process to expose the bottom of the first trench 21. Then, the substrate 10 is continuously etched by using the remaining first dielectric layer 31 and the patterned photoresist layer 11 as mask layers, and a second trench 22 having a second width smaller than the first width is formed at the bottom of the first trench 21. As an example, the second width may be 20nm to 70nm, such as 20nm, 30nm, 50nm or 70 nm. The process parameters for forming the second trench 22 by etching may refer to the process parameters for forming the first trench 21 in step S21, and are not described herein again.

S24: a second dielectric layer 32 is formed, the second dielectric layer 32 covering the bottom and sidewalls of the second trench 22, and the sidewalls of the first dielectric layer 31, as shown in fig. 6.

For example, the second dielectric layer 32 and the first dielectric layer 31 may be made of the same material, for example, silicon dioxide layers. The process of forming the second dielectric layer 32 includes an in-situ water vapor generation process and an atomic layer deposition process. The thickness of the second dielectric layer 32 is 5nm to 15nm, such as 5nm, 7nm, 10nm or 15 nm. As shown in fig. 6, the upper surface of the second dielectric layer 32 is flush with the upper surface of the substrate 10, and the first dielectric layer 31 and the second dielectric layer jointly constitute a dielectric layer 30 covering the bottom and the sidewalls of the trench 20.

In step S30, a first component may be doped into the dielectric layer 30 to obtain the sacrificial layer 33; wherein the thickness of the sacrificial layer 33 is less than the thickness of the dielectric layer 30, as shown in fig. 7 and 8.

Illustratively, the first component includes phosphorus ions, and the phosphorus ions may be implanted into the dielectric layer 30 by using an inclined angle phosphorus ion implantation method, and the formed phosphorus ion implanted layer is used as the sacrificial layer 33. As an example, the implantation dose may be 1011 to 1012/cm2, the implantation energy may be 5keV to 25keV, and the implantation depth may be 5nm to 15 nm. The depth of the ion implantation can be adjusted as desired to obtain sacrificial layers 33 of different thicknesses. In fig. 7, the angle of ion implantation is inclined 15 ° to 60 ° to the left in the vertical direction; in fig. 8, the angle of the ion implantation is inclined 15 ° to 60 ° to the right in the vertical direction. The phosphorus ion injection layer and the dielectric layer undoped with phosphorus ions have different etching selection ratios, so that the phosphorus ion injection layer can be selectively removed in the subsequent etching process, and the dielectric layer 30 undoped with phosphorus ions is reserved.

In some embodiments, the second dielectric layer 32 located at the sidewall of the first dielectric layer 31 may be doped with a first composition to obtain the sacrificial layer 33, as shown in fig. 7 and 8. Wherein the thickness of the sacrificial layer 33 is equal to the thickness of the second dielectric layer 32.

In step S40, referring to fig. 9 to 11, the specific steps of forming the conductive layer 40 include:

s41, a metal barrier layer 42 is formed, wherein the metal barrier layer 42 covers the surfaces of the sacrificial layer 33 and the dielectric layer 30, as shown in fig. 9.

Illustratively, the metal barrier layer 42 may include, but is not limited to, a titanium nitride layer. A physical vapor deposition process or a chemical vapor deposition process may be used to form a titanium nitride layer with a certain thickness in the trench 20 to serve as the metal barrier layer 42. The materials used to prepare the titanium nitride layer include TiCl4, NH3, and N2. In some embodiments, a Rapid Thermal Nitridation (RTN) process may be used to improve the barrier properties of the titanium nitride layer. By way of example, the thickness of the metallic barrier layer 42 may be 2nm to 10nm, such as 2nm, 5nm, or 10 nm.

After the formation of the metal barrier layer 42, the patterned photoresist layer is removed, resulting in the structure shown in fig. 9.

S42: a metal layer 41 is formed, and the metal layer 41 fills the trench 20 and covers the upper surface of the substrate 10.

Illustratively, the metal layer 41 may include, but is not limited to, Ge (germanium), W (tungsten), Cu (copper), or Au (gold). Taking the tungsten layer as an example, a physical vapor deposition process may be used to form a tungsten layer in the trench 20, and the tungsten layer fills the trench 20 and covers the upper surface of the substrate 10.

S43, the metal layer 41 on the upper surface of the substrate 10 is removed and the thickness of the metal layer 41 in the trench 20 is reduced so that the upper surface of the metal layer 41 is lower than the upper surface of the substrate 10, as shown in fig. 10.

For example, the metal layer 41 may be planarized using a Chemical Mechanical Polishing (CMP) process, and the upper surface of the metal layer 41 may be polished until the upper surface of the metal layer 41 is flush with the upper surface of the substrate 10. In some embodiments, an End point detection (End point detection) system may be used to control the polishing process of a CMP process. For example, the upper surface of the substrate 10 may be used as an end point for detecting, and when the upper surface of the substrate 10 is polished, the CMP process is precisely terminated, so as to prevent the substrate 10 from being damaged by the CMP process.

Further, the metal layer 41 in the trench 20 is etched back by using an etching process to reduce the height of the metal layer 41, so that the upper surface of the metal layer 41 is lower than the upper surface of the substrate 10. As an example, the distance between the upper surface of the metal layer 41 and the upper surface of the substrate 10 is 20nm to 40nm, for example 20nm, 30nm or 40 nm.

S44, a portion of metal barrier layer 42 is removed so that the top of metal barrier layer 42 is flush with the upper surface of metal layer 41, as shown in fig. 11.

For example, metal barrier layer 42 (e.g., a titanium nitride layer) may be etched using an SPM cleaning process to reduce the height of metal barrier layer 42, so that the top of metal barrier layer 42 is flush with the upper surface of metal layer 41. The temperature at which the SPM cleaning process is performed is 25 to 50 degrees celsius. As shown in fig. 11, metal barrier layer 42 and metal layer 41 together constitute conductive layer 40.

As shown in fig. 11, a conductive layer 40 is located in the trench 20 with its upper surface lower than the upper surface of the substrate 10 but higher than the second trench 22. Optionally, the upper surface of the conductive layer 40 is flush with the middle of the first trench 21, or higher than the middle of the first trench 21, for example flush with the middle upper portion of the first trench 21.

According to the preparation method of the semiconductor structure, the conducting layer 40 with the larger height is formed in the groove 20, so that the cross-sectional area of the conducting layer 40 can be increased under the condition that the line width of the word line structure is not changed, the word line resistance is greatly reduced, the word line conduction current is increased, and the response speed of a transistor is increased.

In step S50, the sacrificial layer 33 is removed, and air spacers 50 are formed on two opposite sides of the conductive layer 40, as shown in fig. 12. And removing the sacrificial layer 33 by using an etching process to form an air sidewall spacer 50, wherein the air sidewall spacer 50 exposes the side wall of the first dielectric layer 31, the top of the second dielectric layer 32 and a part of the side wall of the conductive layer 40.

Because the sacrificial layer 33 and the dielectric layer 30 which is not doped with phosphorus ions have different etching selection ratios, the sacrificial layer 33 can be selectively removed in an etching process, and the dielectric layer 30 which is not doped with phosphorus ions is reserved. Illustratively, the sacrificial layer 33 may be removed using a wet etching process. When the thickness of the sacrificial layer 33 is the same as that of the second dielectric layer 32, the result shown in fig. 12 can be obtained after removing the sacrificial layer 33, and the air spacers 50 expose the sidewalls of the first dielectric layer 31, the top of the second dielectric layer 32 and a portion of the sidewalls of the conductive layer 40.

Optionally, in some other embodiments, the thickness of the sacrificial layer 33 may be adjusted according to the requirement for the thickness of the air sidewall 50, so that the air sidewall 50 with the target thickness is formed between the conductive layer 40 and the dielectric layer 30 after the sacrificial layer 33 is removed.

In step S60, an insulating protection layer 60 is formed, wherein the insulating protection layer 60 covers the upper surface of the conductive layer 40 and the top of the air sidewall 50, as shown in fig. 13. The method comprises the following specific steps:

s61: a layer of insulating material is formed covering the tops of the air sidewalls 50, the upper surface of the conductive layer 40 and the upper surface of the substrate 10.

Illustratively, the layer of insulating material may include, but is not limited to, a silicon nitride layer. A silicon nitride layer may be deposited on the upper surface of the conductive layer 40 by a chemical vapor deposition process to cover the top of the air sidewall 50, the upper surface of the conductive layer 40 and the upper surface of the substrate 10. As an example, raw materials for preparing a silicon nitride layer include TiCL4 and NH 3.

S62: removing the insulating material layer on the upper surface of the substrate 10 to obtain an insulating protection layer 60; wherein the upper surface of the insulating protective layer 60 is flush with the upper surface of the substrate 10, as shown in fig. 13.

For example, the insulating material layer may be polished and planarized by a chemical mechanical polishing process, and the upper surface of the substrate 10 is used as an end point, and the polishing is stopped when the polishing is detected to reach the upper surface of the substrate 10, so as to form the insulating protection layer 60 flush with the upper surface of the substrate 10.

According to the preparation method of the semiconductor structure, the air side wall 50 is formed between the dielectric layer 30 and the conducting layer 40, so that the GIDL effect of the device can be effectively improved, the leakage current of the device in a closed state is reduced, the static power consumption is reduced, and the service life of the device is prolonged; in addition, by forming the conductive layer 40 with a larger height in the trench 20, the cross-sectional area of the conductive layer 40 can be increased under the condition that the line width of the word line structure is not changed, so that the word line resistance is greatly reduced, the word line on-current is increased, and the response speed of the transistor is increased

As shown in fig. 13, an embodiment of the present application further discloses a semiconductor structure, including: a substrate 10, wherein the substrate 10 has a trench 20 therein, the trench 20 includes a first trench 21 close to the surface of the substrate 10 and a second trench 22 far from the surface of the substrate 10, and the width of the first trench 21 is greater than that of the second trench 22; a dielectric layer 30 covering the bottom and sidewalls of the trench; a conductive layer 40 located in the trench 20, an upper surface of the conductive layer 40 being lower than an upper surface of the substrate 10; the air side walls 50 are positioned in the first grooves 21 and positioned on two opposite sides of the conductive layer 40; and an insulating protective layer 60 covering the upper surface of the conductive layer 40 and the top of the air sidewall 50.

In the semiconductor structure, the air side walls are arranged on the two sides of the conducting layer, and the air side walls are applied to the transistor structure, so that an electric field between a grid electrode and a drain electrode can be reduced, GIDL leakage current is reduced, static power consumption of a transistor is reduced, the service life of a device is prolonged, and the reliability of the device is improved.

By way of example, the substrate 10 may include, but is not limited to, a silicon substrate or a silicon-on-insulator substrate. Trenches 20 are arranged in parallel spaced apart in substrate 10. As an example, the trench 20 may be a word line trench. The trenches 20 include a first trench 21 near the surface of the substrate 10 and a second trench 22 far from the surface of the substrate 10, and a dielectric layer 30 covers sidewalls of the first trench 21 and bottom and sidewalls of the second trench 22. By way of example, dielectric layer 30 may include, but is not limited to, a silicon oxide layer.

In some embodiments, conductive layer 40 may include a metal layer 41 and a metal barrier layer 42 covering the bottom and sidewalls of metal layer 41. Illustratively, the material forming the metal layer 41 may include, but is not limited to, Ge (germanium), W (tungsten), Cu (copper), or Au (gold). The material forming the metal barrier layer 42 may be, for example, a titanium layer or a titanium nitride layer. The metal barrier layer 42 is used to separate the metal layer 41 from the silicon layer in the substrate 10, and prevent the metal layer 41 and the silicon layer from mutually permeating, which may affect the product performance.

As shown in fig. 13, the conductive layer 40 fills the second trench 22 and extends to the first trench 21, wherein an upper surface of the conductive layer 40 is lower than an upper surface of the substrate 10. Illustratively, the upper surface of the conductive layer 40 is flush with the middle upper portion of the first trench 21. Optionally, in some other embodiments, the upper surface of the conductive layer 40 is flush with the middle of the first trench 21.

In the semiconductor structure, the conductive layer 40 at least fills more than half of the trench 20, so that the cross-sectional area of the conductive layer is increased, the conductive resistance is reduced, the on-state current is increased, and the response speed of the device is increased under the condition of keeping the line width unchanged.

In some embodiments, the air sidewall spacers 50 are located between the sidewalls of the conductive layer 40 and the dielectric layer 30, and the tops of the air sidewall spacers 50 are flush with the upper surface of the conductive layer 40.

As shown in fig. 13, air spacers 50 are disposed in the first trench 21 on opposite sides of the conductive layer 40 to separate the conductive layer 40 from the dielectric layer 30. The air sidewall 50 is a space formed by the conductive layer 40, the insulating protection layer 60 and the dielectric layer 30.

For example, the semiconductor structure may be a word line structure, for example, a buried word line structure. The word line structure can be applied to a Dynamic Random Access Memory (DRAM) to improve the response speed of the device, reduce static power consumption and extend the service life and reliability of the DRAM device.

The application also discloses a semiconductor device comprising the semiconductor structure in any one of the embodiments. Illustratively, the semiconductor device may comprise a DRAM device, or other device comprising a transistor structure.

It should be understood that, although the steps in the flowchart of fig. 1 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a portion of the steps in FIG. 1 may include multiple steps or stages. These steps or phases are not necessarily performed at the same time, but may be performed at different times, and the order of performing these steps or phases is not necessarily sequential, but may be performed alternately or at least partially with other steps or steps among other steps.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that various changes and modifications can be made by those skilled in the art without departing from the spirit of the invention, and these changes and modifications are all within the scope of the invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (17)

1. A semiconductor structure, comprising:

the substrate is provided with grooves, the grooves comprise a first groove close to the surface of the substrate and a second groove far away from the surface of the substrate, and the width of the first groove is larger than that of the second groove;

the dielectric layer covers the bottom and the side wall of the groove;

the conducting layer is positioned in the groove, and the upper surface of the conducting layer is lower than the upper surface of the substrate;

the air side walls are positioned in the first grooves and positioned on two opposite sides of the conducting layer;

and the insulating protection layer covers the upper surface of the conductive layer and the top of the air side wall.

2. The semiconductor structure of claim 1, wherein an upper surface of the conductive layer is flush with a middle or upper middle portion of the first trench.

3. The semiconductor structure of claim 1, wherein the conductive layer comprises a metal layer and a metal barrier layer covering a bottom and sidewalls of the metal layer.

4. The semiconductor structure of claim 1, wherein the air sidewall is located between the sidewall of the conductive layer and the dielectric layer, and a top of the air sidewall is flush with an upper surface of the conductive layer.

5. The semiconductor structure of claim 1, wherein the air side wall is a space enclosed by the conductive layer, the insulating protection layer and the dielectric layer.

6. A method for fabricating a semiconductor structure, comprising:

providing a substrate;

forming a groove in the substrate, wherein the bottom and the side wall of the groove are covered by a dielectric layer;

forming a sacrificial layer in the dielectric layer;

forming a conductive layer, wherein the upper surface of the conductive layer is lower than the upper surface of the substrate;

removing the sacrificial layer to form air side walls on two opposite sides of the conductive layer;

and forming an insulating protection layer, wherein the insulating protection layer covers the upper surface of the conducting layer and the top of the air side wall.

7. The method of claim 6, wherein the dielectric layer comprises a first dielectric layer and a second dielectric layer; forming a trench in the substrate, wherein the bottom and sidewalls of the trench are covered by a dielectric layer, comprising:

forming a first trench in the substrate, the first trench having a first width;

forming the first dielectric layer on the bottom and the side wall of the first groove;

removing the first dielectric layer at the bottom of the first trench, and forming a second trench at the bottom of the first trench, wherein the second trench has a second width, and the second width is smaller than the first width;

and forming the second dielectric layer, wherein the second dielectric layer covers the bottom and the side wall of the second groove and the side wall of the first dielectric layer.

8. The method of claim 7, wherein the first dielectric layer and the second dielectric layer comprise a silicon oxide layer.

9. The method of claim 7, wherein the thickness of the first dielectric layer comprises 5nm to 15 nm; the thickness of the second dielectric layer comprises 5nm-15 nm.

10. The method of claim 7, wherein the forming a sacrificial layer in the dielectric layer comprises:

doping a first component into the dielectric layer to obtain the sacrificial layer;

and the thickness of the sacrificial layer is smaller than that of the dielectric layer.

11. The method of claim 10, wherein the first component comprises phosphorus.

12. The method of claim 10, wherein the doping the dielectric layer with a first composition comprises:

and doping the first component into the second dielectric layer positioned on the side wall of the first dielectric layer to obtain the sacrificial layer.

13. The method of claim 12, wherein the sacrificial layer has a thickness equal to a thickness of the second dielectric layer.

14. The method of claim 13, wherein the forming the conductive layer comprises:

forming a metal barrier layer, wherein the metal barrier layer covers the surfaces of the sacrificial layer and the dielectric layer;

forming a metal layer, wherein the metal layer fills the groove and covers the upper surface of the substrate;

removing the metal layer on the upper surface of the substrate, and reducing the thickness of the metal layer in the groove to enable the upper surface of the metal layer to be lower than the upper surface of the substrate;

and removing part of the metal barrier layer so that the top of the metal barrier layer is flush with the upper surface of the metal layer.

15. The method of claim 14, wherein an upper surface of the metal layer is flush with a middle or middle-upper portion of the sacrificial layer.

16. The method of claim 15, wherein the removing the sacrificial layer to form air spacers on two opposite sides of the conductive layer comprises:

and removing the sacrificial layer by adopting an etching process to form the air side wall, wherein the air side wall exposes the side wall of the first dielectric layer, the top of the second dielectric layer and part of the side wall of the conductive layer.

17. The method for fabricating a semiconductor structure according to any one of claims 6 to 16, wherein the forming of the insulating protective layer comprises:

forming a layer of insulating material covering the top of the air sidewalls, the upper surface of the conductive layer, and the upper surface of the substrate;

removing the insulating material layer on the upper surface of the substrate to obtain the insulating protective layer; wherein an upper surface of the insulating protection layer is flush with an upper surface of the substrate.

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