CN100346483C - 场效应晶体管以及包括场效应晶体管的集成电路 - Google Patents

场效应晶体管以及包括场效应晶体管的集成电路 Download PDF

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CN100346483C
CN100346483C CNB2004100576012A CN200410057601A CN100346483C CN 100346483 C CN100346483 C CN 100346483C CN B2004100576012 A CNB2004100576012 A CN B2004100576012A CN 200410057601 A CN200410057601 A CN 200410057601A CN 100346483 C CN100346483 C CN 100346483C
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effect transistor
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陈华杰
布鲁斯·B·多利斯
菲利普·J·奥尔迪奇
王新琳
朱慧珑
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Abstract

场效应晶体管(FET)、包括FET的集成电路(IC)芯片。器件具有薄沟道，例如超薄(小于或等于10纳米(10nm))绝缘体上硅(SOI)层。源/漏区域位于薄沟道每一端的凹进中，比薄沟道厚得多(例如30nm)。源/漏扩展部分和相应的源/漏区域与FET栅和薄沟道自对准。

Description

场效应晶体管以及包括场效应晶体管的集成电路
技术领域
本发明涉及半导体器件和制造，更特定地涉及高性能场效应晶体管(FET)和制造高性能FET的方法。
背景技术
典型的半导体集成电路(IC)设计目标包括以最小功率获得高的性能和密度。为了使半导体电路功耗最小化，大多数IC是以众所周知的互补绝缘栅场效应晶体管(FET)技术——即通常所说的CMOS——来制作的。典型的CMOS电路驱动纯或几乎纯电容负载，包括成对的互补器件，即，n型FET(NFET)与相应的p型FET(PFET)成对，通常在栅极加相同的信号。性能取决于CMOS电路能将电容负载多快地充电和放电，即电路的开关速度。由于器件对具有基本彼此相反的工作特性，当某一器件(例如NFET)为开并导通(简单模拟为闭合的开关)时，另一器件(PFET)为关，不导通(理想地模拟为简单的断开的开关)，反之亦然。这样，理想上，在典型的CMOS电路中不存在静电或DC电流路径，电路负载的开关与某一开关能闭合和另一开关能断开的速度一样快。
例如，CMOS反相器是一个PFET和NFET对，它们串连在电源电压(Vdd)和地(GND)之间。它们在栅极加相同的输入并且驱动同一电容负载。在某一输入信号状态，PFET开，将输出拉高，PFET开电流使负载电容充电至Vdd。在相反的输入信号状态，NFET开，将输出拉低，NFET开电流使负载电容放电回到地电位。器件开电流与栅、源和漏电压有关，取决于这些电压，器件可以模拟作一个电压控制电流源或一个电阻。由于电流流过器件时串连电阻——即器件漏或源中的——会使电压有所下降，串连电阻影响器件电压，从而影响(降低)器件电流，减慢电容负载的充电或放电。当栅-源电压(Vgs)的大小小于关于其源的某些阈值电压(VT)时，开关断开，即器件关。因此，理想上，NFET在VT之下关，而在VT之上开，导通电流。类似地，PFET在其栅高于其VT——即更少的负数——时关，而在VT之下开。
半导体技术和芯片制造向更高电路开关频率(电路性能)和更多晶体管(电路密度)以在相同面积上获得更多功能的推进已经导致芯片特征尺寸以及相应的电源电压的不断下降。一般地，当所有其它因素都为常数时，给定单元所消耗的有效功率随着开关频率线性上升。这样，无论芯片电源电压是否降低，芯片功耗同样增大。无论在芯片级别还是系统级别，芯片功率的这一增大自然导致了冷却和封装成本的迅速上升。
不幸地，随着FET部件的缩小，器件泄漏——包括栅泄漏(即栅到沟道、栅到源或漏以及栅所引起的漏泄漏(GIDL))和源/漏结泄漏——变得明显起来。在众所周知的体效应技术中，例如，会发生短沟效应，部分是因为注入到器件源/漏区域中的掺杂剂呈放射状向外扩散，从而源/漏区域延伸到器件沟道之下。这导致了源/漏区域之间的掩埋泄漏路径，并且，在某些情形中，导致了表面下沟道短路。随着，例如，源和漏结阻挡层之间——即从反偏结——的距离的下降，会出现其它泄漏源。通常，阈值下效应包括称作阈值下泄漏电流的那些，即在栅偏置对于NFET低于阈值而对于PFET高于阈值时从漏流向源的电流(Ids)。此外，对于特定器件，阈值下电流随着器件漏-源电压(Vds)大小的增大而增大，而随着器件VT大小的增大而减小，漏所引入的势垒降低。除了泄漏之外，短沟效应还包括称作VT衰减的那些，其中短沟器件的电流-电压(I-V)曲线显示出下降的清晰度。
轻掺杂漏(LDD)是减小短沟问题的一个方法。要点在于沿源/漏区处的FET栅形成隔离层。隔离层阻挡或削弱了栅处的掺杂剂注入，将源/漏扩散从栅隔离开。轻掺杂区域——通常在隔离层形成之前注入——在更重掺杂的源/漏区域和栅之间形成以完成器件。不幸地，这些轻掺杂区域加大了每个器件的源和漏处的串连电阻，减小了器件电流，降低了器件性能。此外，随着器件沟道长度缩小到一微米(1μm)一下，阈值下问题变得更显著，轻掺杂漏不能解决这些问题。
短沟效应随着体厚度的减小而增大。因此，通过减薄表面硅层，即器件层，阈值下泄漏和其它短沟效应在绝缘体上硅(SOI)中得到控制和减小。在超薄SOI晶片通称为完全耗尽(FD)SOI的中，硅层小于50nm。超薄SOI是将栅缩小到深亚40nm或更小的最主要的候选方式。超薄SOI器件工作在更低有效电压。结果，可对器件进行掺杂以得到更高的迁移率，这反过来增大了器件电流，提高了性能。此外，Vgs降到VT之下，超薄SOI器件具有更陡峭的阈值下电流摆动，电流急剧下降。然而，不幸地，由于源/漏区域由同一超薄SOI层制成，器件具有更大的外部电阻。
因此，为了减小这一超薄SOI器件外部电阻，使用，例如选择外延硅生长将半导体表面层选择加厚，以形成凸起的源和漏(RSD)区域。凸起的源/漏区域具有更大的剖面积从而具有更低的单位面积电阻(薄层电阻)，从而在克服外部电阻问题上更有效。不幸地，硅层表面上的凸起源/漏在栅的每一侧形成了平行表面区域，需要在栅的侧壁处的间隙(例如隔离层)来防止短路，并且，同时引起栅和RSD区域之间寄生栅电容增大。例如，对于具有10nm侧壁隔离层的超薄(～10nm)FET来说，取决于隔离层材料，30纳米(30nm)的RSD区域可使交叠电容增大多至25-50％(每微米宽度0.08-0.2飞法(fF))。此外，侧壁隔离层加入器件面积，使得RSD区域不能置于沟道端部。这样，RSD需要在降低外部电阻和接受增大的寄生电容之间寻求折衷。
授予Yu题为“具有凹进源和漏区域的超薄体SOI MOS晶体管(Ultra-Thin Body SOI MOS Transistors Having Recessed SourceAnd Drain Regions)”的美国专利No.6,420,218 B1以及授予Xiang等人题为“具有凹进源和漏的绝缘体上半导体晶体管(Semiconductor-on Insulator Transistor with Recessed Source andDrain)”的美国专利No.6,437,404 B1给出凹进源/漏区域作为避免或减小寄生电容的方法。不幸地，Xiang等人容许了电阻扩展，它们将器件沟道与凹进源/漏区域相连并起与LDD类似的作用，增加了串连源/漏电阻。Yu给出在已确定的源/漏凹进上形成超薄沟道，并源/漏凹进之间、在两层之下形成FET栅。由于Yu将栅与源/漏凹进对准，即，由于Yu的器件不是自对准的，Yu以相对较大的工艺偏差(即沟道长度和源/漏交叠)制作FET，这导致电路性能的更大分散，即大量电路/芯片所导致的对标定设计点的偏离。这样，从前，面临着接受寄生器件电容、串连沟道电阻和/或更宽松的设计容差。
这样，需要对超薄SOI器件减小外部电阻同时使器件开电阻最小化。
发明内容
本发明的一个目的在于提高超薄SOI的性能；
本发明的另一目的在于减小超薄SOI器件的外部电阻；
本发明的又一目的在于减小超薄SOI器件中的外部电阻而不增大器件寄生电容。
本发明涉及场效应晶体管(FET)、包括FET的集成电路(IC)和形成FET的方法。器件具有薄的沟道，例如超薄(小于或等于10纳米(10nm))的绝缘体上硅(SOI)层。源/漏区域位于薄沟道两端处的凹进中，比薄沟道厚得多(例如30nm)。源/漏扩展部分和相应的源/漏区域自对准于FET栅和薄沟道。
本发明提供了一种场效应晶体管，包含：薄沟道，具有第一厚度；栅，置于所述薄沟道之上；源/漏区域，位于所述薄沟道每一端的凹进中，比所述薄沟道实质上更厚；以及源/漏扩展部分，处于所述薄沟道和相应的所述源/漏区域之间，每个所述源/漏扩展部分和所述相应的源/漏区域与所述栅和所述薄沟道自对准。
本发明还提供了一种集成电路，在绝缘体上硅(SOI)芯片上，所述集成电路包括许多置于绝缘层上的场效应晶体管，所述绝缘层在半导体衬底上，所述场效应晶体管中的每一个包含：薄沟道，所述薄沟道为薄半导体层，具有第一厚度；栅，置于所述薄沟道之上；源/漏区域，位于所述薄沟道每一端的凹进中，比所述薄沟道实质上更厚；以及源/漏扩展部分，处于所述薄沟道和相应的所述源/漏区域之间，每个所述源/漏扩展部分和所述相应的源/漏区域与所述栅和所述薄沟道自对准。
附图说明
从下面参考附图对本发明优选实施方案的详细描述可更好地理解前述和其它目的、方面和优点，其中：
图1A-C每一幅示出根据本发明的优选实施方案场效应晶体管(FET)的一个实施例；
图2示出根据本发明优选实施方案在超薄SOI晶片上形成具有自对准凹进的扩展部分和源/漏(ESD)区域的FET的步骤的流程图实施例；
图3示出SOI键合晶片的剖面；
图4A-C示出器件确定步骤的实施例；
图5A-C示出在形成凹进ESD之前确定并密封超薄沟道的实施例；
图6A-B示出下切超薄层以形成凹进ESD的实施例；
图7示出填充源/漏空隙以形成凹进源/漏扩展部分的实施例；
图8示出除去剩余保护层以进行随后的典型半导体工艺步骤。
具体实施方式
现在参看附图，更特定地，参看图1A-C，每一幅示出根据本发明优选实施方案的具有自对准凹进源/漏区域和扩展部分的场效应晶体管(FET)100、102、104的一个实施例，相似元素一致标出。特别地，FET 100、102、104可以是电路中的典型器件，例如超薄(小于或等于15纳米(10nm))绝缘体上半导体(SOI)CMOS芯片上的CMOS电路。
因此，在图1A的FET 100实施例中，栅106在每一侧都具有隔离层108。优选地，栅106为多晶硅、金属、硅锗(SiGe)、硅化物或它们的组合，隔离层108为氮化物。栅106位于栅介电层110(例如氧化物)上，后者位于超薄沟道112——应变硅(SSi)、锗(Ge)、SiGe或，优选地，硅(Si)的超薄半导体层——上。超薄沟道112短于40nm，优选地2-3倍于沟道厚度，或30nm。凹进源/漏区域114形成在超薄沟道112的两端。栅106与具有基本均匀的厚度的凹进源/漏(ESD)114没有明显的直接交叠。源/漏区域114在超薄硅沟道112下延伸进绝缘体(例如氧化物)层116中至少5nm，优选地20-30nm，总的源/漏厚度50-70nm。在这一实施方案中，扩展部分在沟道112两端自然形成，从而器件100自对准于凹进源/漏区域116和扩展部分。扩展部分用于使短沟效应最小化，从而无需高阻轻掺杂漏(LDD)区域，因此，可以使器件电阻和交叠电容都最小化。
在图1B的FET 102实施例中，自对准扩展部分118形成在沟道112’的两端，其中栅106与源/漏凹进114交叠，也具有基本均匀的厚度，例如50-70nm。再次，由于栅106与自对准扩展部分118交叠，串连沟道电阻被最小化。在图1C的FET 104实施例中，自对准扩展部分119也形成在沟道112”两端，其中栅106与源/漏凹进114交叠。然而，在这一实施例中，源/漏凹进114具有不均匀、阶梯状厚度，从而在扩展部分119处稍厚。
图2在流程图120中示出根据本发明优选实施方案在超薄SOI晶片上形成具有ESD区域114的自对准FET(例如100)的步骤的实施例。首先是晶片122，在步骤124中形成器件区域以确定器件位置，例如，在器件区域处构图栅106并使用浅沟隔离(STI)来隔离出器件区域。沟槽延伸通过薄的硅表面层进入下层到至少等于ESD 114所需厚度的深度，优选地延伸到下层半导体衬底。沉积绝缘材料，例如氮化物来填充沟槽。沟槽材料在随后的工艺步骤中使栅和沟道层保持位置。接下来，在步骤126中，确定源/漏区域以便形成ESD 114。在步骤128中，下切源/漏区域，开出延伸进下层绝缘层116的小孔。在步骤130中，用半导体材料，例如硅填充源/漏区域114，然后按通常的方法继续器件制作，例如，源/漏注入和扩散、金属化，等等。
图3-7示出在超薄SOI晶片上如图2的步骤120中所给出的那样形成具有自对准ESD区域的FET的第一优选实施方案方法140。图3示出SOI晶片140的剖面，它是与半导体衬底142键合的晶片，优选地为硅，可以是SSi、Ge、SiGe或应变硅/硅锗(SSi/SiGe)。绝缘层144(优选地为氧化物)将牺牲层146(优选地为50nm的未掺杂硅层)与半导体衬底142分隔开。薄的绝缘层148(优选地为50nm氮化物层)将超薄沟道层150与牺牲层146分隔开。
图4A-C示出器件确定步骤124的实施例。图4A示出俯视图，在图4B和4C中分别示出沿BB和CC的剖面。从而，在超薄沟道层150上形成栅介电或氧化物层152。栅介电层152可以是氧化物、氧氮化物或任何合适的高K介电材料层，为讨论简便，此处称之为栅氧化物。在栅氧化物层152上形成金属、掺杂多晶硅、硅化物或其组合的导电栅层。然后，使用合适的确定技术——例如半导体制造中众所周知的那些——构图栅层以确定栅154。形成浅沟槽156环绕器件周围，从而STI确定了器件区域158。优选地，STI沟槽156被腐蚀，向下穿过超薄沟道层150、薄绝缘层148、牺牲层146和绝缘层144并腐蚀进硅衬底层142。在栅154之上形成薄绝缘层并填充浅沟槽156。薄绝缘层被各向异性腐蚀以形成沿栅154的隔离层160，STI沟槽156依旧填充有绝缘体。
最后，在多晶硅栅154中注入掺杂剂，由箭头162表示。注入对牺牲层146处于多晶硅栅154两侧的部分164进行掺杂。优选地，掺杂剂162可以是优选地以20KeV/1015注入的硼，或以100KeV/1015注入的BF2。然后，晶片退火(优选地在900-1000℃退火5-10秒)以活化牺牲层146中的硼掺杂剂。可选地，如果需要更厚的隔离层160以在随后的步骤中除去下层材料时改善表面层150，掺杂剂注入162可以在形成更厚的隔离层160之前完成。可使用两步注入来使图1C中的FET 104的源/漏区域114和扩展部分118凹进。首先，在形成隔离层160之前，可以以低能量——例如7KeV/(5×1014)——注入硼，或以35KeV/(5×1014)注入BF2。然后，形成隔离层160并以更高的能量——例如20KeV/1015——注入硼，或以100KeV/1015注入BF2。
接下来，图5A-C示出图2中确定源/漏凹进区域164并由此确定超薄沟道的步骤126的实施例。图5A示出俯视图，在图5B和5C分别示出沿BB和CC的剖面。首先，利用选择腐蚀，例如反应离子刻蚀(RIE)，在器件区域158的两端开出小孔165直到硅衬底层142。接下来，使用湿法腐蚀除去牺牲层之下的氧化层144，在牺牲层之下部分形成空隙166。在上晶片表面168上定向沉积薄的保护层167，优选地为氧化物，以保护超薄层150。利用，例如，高密度等离子体沉积(HDP)，可以仅在表面顶上沉积薄层氧化物，层146底部没有氧化物。然后，将牺牲层未掺杂的部分选择腐蚀掉，在掺杂部分164之间形成间隙170。使用选择性腐蚀来腐蚀未掺杂层，其腐蚀硼掺杂硅的速度比腐蚀未掺杂材料的速度慢得多。除去未掺杂部分完成了空隙166并在其上确定了沟道172，剩下的牺牲部分164确定了源/漏区域。沟道172掩埋在超薄沟道层150中，包含在下面的薄绝缘层148和上面的栅氧化物152之间。如果按上述两步的掺杂剂来掺杂牺牲层146，那么掺杂部分164的剖面与图1C的凹进源/漏区域114就非常相像。
图6A-B示出图2中下切源/漏区域以形成凹进ESD的步骤128的实施例。用低k材料——例如氧化物174——填充空隙166以降低短沟效应。然后，内腐蚀任何过剩氧化物，优选地暴露牺牲层部分164的侧面。接下来，向牺牲层部分164注入砷，由箭头176表示，剂量应当足以使牺牲层部分164从p型(p+)转化为n型(n+)。利用HDP定向沉积另一薄层氧化物177以保护多晶硅栅154和表面层150。将晶片进行退火以使p型部分164转化为n型，优选地使载流子浓度至少达到每立方厘米(cm3)1020。然后，利用对n型材料的腐蚀速率快于未掺杂材料的选择性湿法腐蚀来除去n型部分164，在沟道172的两端部分形成源/漏下切178。可选地，稍微除去一点氧化物174以使源/漏空隙178延伸到栅154两侧之下，就像图1B中的FET 102或图4C中的FET的实施例中那样。优选地，这通过稍微改变硼注入(图4B中的162)倾角，改变硼的角度朝向栅的两端来完成。然而，作为替代，可以稍微腐蚀一点氧化物174，尽管通常说来，难以控制腐蚀，尤其是在栅下的腐蚀。优选地，湿法腐蚀还除去了n型部分164以前位置之上的键合层148，以完成源/漏下切178。然而，作为替代，用合适的附加湿法腐蚀除去键合层(通过除去n型部分164’而)暴露的部分，以完成源/漏下切178。
图7示出图2中填充源/漏空隙178以形成凹进源/漏扩展部分180的步骤130的实施例。优选地，选择外延生长硅以填充源/漏下切178，从而形成在沟道172两端具有凹进源/漏和扩展部分区域180的自对准器件。在图8中，在湿法腐蚀之后，剥去剩余保护层，完成器件用于随后通常的半导体工艺步骤，例如，注入n型和p型源/漏扩散、金属化，等等。
有利地，优选实施方案FET是自对准的，外部串连电阻和寄生电容都最小化了。此外，随着超薄表面硅层减薄至10nm及以下并且随着器件沟道长度缩小到40nm以下，本发明可用于超薄SOI。而且，优选器件结构是器件以更低有效场工作的结构，从而可以有更大的载流子迁移率以及相应的更大的沟道电流。另外，优选实施方案超薄SOI器件改善了短沟效应特性，包括更陡峭的阈值下电流摆动，改善了性能。此外，优选实施方案器件在没有导致现有技术的器件中会发生的沟道电阻和寄生电容恶化的情况下获得了这一结果。
虽然依据优选实施方案描述了本发明，但是本领域技术人员将会承认，本发明能够以所附实施方案的精神和范围内的调整来实践。

Claims (28)

1.场效应晶体管，包含：
薄沟道，具有第一厚度；
栅，置于所述薄沟道之上；
源/漏区域，位于所述薄沟道每一端的凹进中，比所述薄沟道更厚；以及
源/漏扩展部分，处于所述薄沟道和相应的所述源/漏区域之间，每个所述源/漏扩展部分和所述相应的源/漏区域与所述栅和所述薄沟道自对准。
2.根据权利要求1的场效应晶体管，其中所述凹进在所述每一端处延伸到所述栅之下。
3.根据权利要求1的场效应晶体管，其中所述凹进在所述每一端处部分延伸到所述栅之下。
4.根据权利要求1的场效应晶体管，其中每一所述源/漏区域的上表面与所述薄沟道的上表面共面。
5.根据权利要求1的场效应晶体管，其中所述薄沟道为选自下列的半导体材料：硅、锗、硅锗和应变硅。
6.根据权利要求5的场效应晶体管，其中所述薄沟道为应变硅。
7.根据权利要求5的场效应晶体管，其中所述栅由包含多晶硅的材料制成。
8.根据权利要求5的场效应晶体管，其中所述栅由包含硅化物的材料制成。
9.根据权利要求1的场效应晶体管，其中所述薄沟道小于15nm厚。
10.根据权利要求9的场效应晶体管，其中所述薄沟道厚10nm。
11.根据权利要求9的场效应晶体管，其中所述薄沟道短于40nm。
12.根据权利要求11的场效应晶体管，其中所述薄沟道长30nm。
13.根据权利要求9的场效应晶体管，其中所述凹进的下表面在所述薄沟道之下超过5nm。
14.根据权利要求13的场效应晶体管，其中所述下表面在所述薄沟道之下40nm。
15.根据权利要求1的场效应晶体管，其中所述场效应晶体管沉积在绝缘层上，所述绝缘层沉积在半导体衬底上。
16.根据权利要求15的场效应晶体管，其中所述半导体衬底包含硅衬底。
17.根据权利要求15的场效应晶体管，其中所述半导体衬底包含应变硅/硅锗衬底。
18.集成电路，在绝缘体上硅芯片上，所述集成电路包括许多置于绝缘层上的场效应晶体管，所述绝缘层在半导体衬底上，所述场效应晶体管中的每一个包含：
薄沟道，所述薄沟道为薄半导体层，具有第一厚度；
栅，置于所述薄沟道之上；
源/漏区域，位于所述薄沟道每一端的凹进中，比所述薄沟道更厚；以及
源/漏扩展部分，处于所述薄沟道和相应的所述源/漏区域之间，每个所述源/漏扩展部分和所述相应的源/漏区域与所述栅和所述薄沟道自对准。
19.根据权利要求18的集成电路，其中所述凹进在所述每一端处延伸到所述栅之下。
20.根据权利要求18的集成电路，其中所述凹进在所述每一端处部分延伸到所述栅之下。
21.根据权利要求18的集成电路，其中所述薄半导体层为一层选自下列的半导体材料：硅、锗、硅锗和应变硅。
22.根据权利要求21的集成电路，其中所述薄沟道为硅而所述栅为多晶硅。
23.根据权利要求22的集成电路，其中所述薄沟道为应变硅。
24.根据权利要求22的集成电路，其中所述薄沟道厚度小于15nm。
25.根据权利要求24的集成电路，其中每个所述凹进的下表面在所述薄沟道之下超过5nm。
26.根据权利要求25的集成电路，其中所述薄沟道短于40nm。
27.根据权利要求26的集成电路，其中所述半导体衬底为硅衬底。
28.根据权利要求27的集成电路，其中所述半导体衬底为应变硅/硅锗衬底。
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