CN100346327C - 具有混合并行/串行总线接口的用户设备 - Google Patents

具有混合并行/串行总线接口的用户设备 Download PDF

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Publication number
CN100346327C
CN100346327C CNB028231155A CN02823115A CN100346327C CN 100346327 C CN100346327 C CN 100346327C CN B028231155 A CNB028231155 A CN B028231155A CN 02823115 A CN02823115 A CN 02823115A CN 100346327 C CN100346327 C CN 100346327C
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China
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serial
data
block
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Expired - Fee Related
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CNB028231155A
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English (en)
Chinese (zh)
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CN1589437A (zh
Inventor
约瑟·葛瑞丹
艾佛瑞·史达福利
堤摩西·A·亚瑟尼司
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InterDigital Technology Corp
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InterDigital Technology Corp
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Priority claimed from US09/990,060 external-priority patent/US7069464B2/en
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Publication of CN1589437A publication Critical patent/CN1589437A/zh
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Publication of CN100346327C publication Critical patent/CN100346327C/zh
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00—Parallel/series conversion or vice versa
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/14—Channel dividing arrangements, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Information Transfer Systems (AREA)
  • Communication Control (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Dc Digital Transmission (AREA)
CNB028231155A 2001-11-21 2002-11-18 具有混合并行/串行总线接口的用户设备 Expired - Fee Related CN100346327C (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US09/990,060 US7069464B2 (en) 2001-11-21 2001-11-21 Hybrid parallel/serial bus interface
US09/990,060 2001-11-21
US10/080,899 2002-02-22
US10/080,899 US6823469B2 (en) 2001-11-21 2002-02-22 User equipment (UE) having a hybrid parallel/serial bus interface

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CNA2007101274916A Division CN101079855A (zh) 2001-11-21 2002-11-18 具有混合并行/串行总线接口的用户设备

Publications (2)

Publication Number Publication Date
CN1589437A CN1589437A (zh) 2005-03-02
CN100346327C true CN100346327C (zh) 2007-10-31

Family

ID=26764107

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB028231155A Expired - Fee Related CN100346327C (zh) 2001-11-21 2002-11-18 具有混合并行/串行总线接口的用户设备

Country Status (12)

Country Link
EP (1) EP1446722A4 (fr)
JP (1) JP2005510800A (fr)
CN (1) CN100346327C (fr)
AT (2) ATE397323T1 (fr)
AU (1) AU2002352773A1 (fr)
CA (1) CA2467841C (fr)
DE (1) DE60226910D1 (fr)
HK (1) HK1069905A1 (fr)
MX (1) MXPA04004742A (fr)
NO (1) NO20042522L (fr)
TW (2) TWI285316B (fr)
WO (1) WO2003046737A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1329850C (zh) * 2004-01-20 2007-08-01 凌阳科技股份有限公司 多重路径总线资料传输方法及系统
CN1321382C (zh) * 2004-01-20 2007-06-13 宏达国际电子股份有限公司 串行/并行数据转换模块及相关计算机系统

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6122683A (en) * 1997-04-10 2000-09-19 International Business Machines Corp. Handshake minimizing serial-to-parallel interface with shift register coupled by parallel bus to address logic and control logic
CN1589532A (zh) * 2001-11-21 2005-03-02 美商内数位科技公司 混合并行/串行总线接口

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH056335A (ja) * 1991-06-27 1993-01-14 Nec Eng Ltd 装置間インタフエース方式
JPH05160819A (ja) * 1991-12-03 1993-06-25 Nec Eng Ltd データ転送装置
JPH05250316A (ja) * 1992-03-05 1993-09-28 Nec Eng Ltd 装置間インタフェース方式
US5602780A (en) * 1993-10-20 1997-02-11 Texas Instruments Incorporated Serial to parallel and parallel to serial architecture for a RAM based FIFO memory
US5768529A (en) * 1995-05-05 1998-06-16 Silicon Graphics, Inc. System and method for the synchronous transmission of data in a communication network utilizing a source clock signal to latch serial data into first registers and a handshake signal to latch parallel data into second registers

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6122683A (en) * 1997-04-10 2000-09-19 International Business Machines Corp. Handshake minimizing serial-to-parallel interface with shift register coupled by parallel bus to address logic and control logic
CN1589532A (zh) * 2001-11-21 2005-03-02 美商内数位科技公司 混合并行/串行总线接口

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
SUE PONIATOWSKI CHANNEL LINK MOVING AND SHAPING INFORMATION INPOINT-TO-POINT APPLICATIONS NATIONAL SEMICONDUCTOR TIM NOVAK 1996 *

Also Published As

Publication number Publication date
CA2467841A1 (fr) 2003-06-05
JP2005510800A (ja) 2005-04-21
NO20042522L (no) 2004-06-16
EP1446722A4 (fr) 2005-04-20
TW200402240A (en) 2004-02-01
CA2467841C (fr) 2008-05-13
TW200419359A (en) 2004-10-01
WO2003046737A1 (fr) 2003-06-05
DE60226910D1 (de) 2008-07-10
CN1589437A (zh) 2005-03-02
ATE388525T1 (de) 2008-03-15
EP1446722A1 (fr) 2004-08-18
MXPA04004742A (es) 2004-08-02
ATE397323T1 (de) 2008-06-15
HK1069905A1 (en) 2005-06-03
AU2002352773A1 (en) 2003-06-10
TWI260172B (en) 2006-08-11
TWI285316B (en) 2007-08-11

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